Title:
SHIFT REGISTER, SCANNING SIGNAL LINE DRIVE CIRCUIT, DISPLAY PANEL, AND DISPLAY DEVICE
Document Type and Number:
WIPO Patent Application WO/2013/002229
Kind Code:
A1
Abstract:
In a holding circuit (11a) of each stage of a shift register, when a clock signal (CK) is at a high level, the input terminal of an inverter INV1 and the output terminal of an inverter INV2 are electrically connected to each other, and the output terminal of the inverter INV1 and the input terminal of the inverter INV2 are electrically connected to each other. The size of the shift register circuit can thus be reduced.
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Inventors:
MURAKAMI YUHICHIROH
FURUTA SHIGE
YOKOYAMA MAKOTO
SASAKI YASUSHI
GYOUTEN SEIJIROU
FURUTA SHIGE
YOKOYAMA MAKOTO
SASAKI YASUSHI
GYOUTEN SEIJIROU
Application Number:
PCT/JP2012/066302
Publication Date:
January 03, 2013
Filing Date:
June 26, 2012
Export Citation:
Assignee:
SHARP KK (JP)
MURAKAMI YUHICHIROH
FURUTA SHIGE
YOKOYAMA MAKOTO
SASAKI YASUSHI
GYOUTEN SEIJIROU
MURAKAMI YUHICHIROH
FURUTA SHIGE
YOKOYAMA MAKOTO
SASAKI YASUSHI
GYOUTEN SEIJIROU
International Classes:
G11C19/28; G09G3/20; G09G3/36; G11C19/00
Domestic Patent References:
| WO2010146740A1 | 2010-12-23 |
Foreign References:
| JP2005228459A | 2005-08-25 | |||
| JPS61217998A | 1986-09-27 | |||
| JPH08256044A | 1996-10-01 | |||
| JPS61269412A | 1986-11-28 | |||
| JPH01243296A | 1989-09-27 |
Attorney, Agent or Firm:
HARAKENZO WORLD PATENT & TRADEMARK (JP)
Patent business corporation Hara [Kenzo] international patent firm (JP)
Patent business corporation Hara [Kenzo] international patent firm (JP)
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Claims: