Title:
SHIFT REGISTER
Document Type and Number:
WIPO Patent Application WO/2011/148655
Kind Code:
A1
Abstract:
Provided is a shift register that connects a unit circuit (11) in multiple stages. One of the electrodes of a capacitor (Cap2) contained in the unit circuit (11) is connected to a gate terminal (node (N1)) of a transistor (T2), and the other electrode is connected to a node (N2). A compensation circuit composed of transistors (T3 to T5) sends a clock signal (CKB) to the node (N2) when the potential of the node (N1) is low, and applies a low potential to the node (N2) when the potential of the node (N1) is high. As a result of this configuration, even when the gate potential of the transistor (T2) changes with a change in a clock signal (CK), a signal offsetting this change is sent via the capacitor (Cap2), and the gate potential of the transistor (T2) is stabilized. Thus, changes in the potential of a control terminal of an output transistor associated with changes in a clock signal are prevented.
Inventors:
KIKUCHI, Tetsuo (())
菊池 哲郎 (())
TANAKA, Shinya (())
田中 信也 (())
菊池 哲郎 (())
TANAKA, Shinya (())
田中 信也 (())
Application Number:
JP2011/050088
Publication Date:
December 01, 2011
Filing Date:
January 06, 2011
Export Citation:
Assignee:
SHARP KABUSHIKI KAISHA (22-22, Nagaike-cho Abeno-ku, Osaka-sh, Osaka 22, 〒5458522, JP)
シャープ株式会社 (〒22 大阪府大阪市阿倍野区長池町２２番２２号 Osaka, 〒5458522, JP)
KIKUCHI, Tetsuo (())
菊池 哲郎 (())
TANAKA, Shinya (())
シャープ株式会社 (〒22 大阪府大阪市阿倍野区長池町２２番２２号 Osaka, 〒5458522, JP)
KIKUCHI, Tetsuo (())
菊池 哲郎 (())
TANAKA, Shinya (())
International Classes:
G11C19/28; G09G3/20; G09G3/36; G11C19/00
Attorney, Agent or Firm:
SHIMADA, Akihiro (Shimada Patent Firm, Manseian Building 1-10-3, Yagi-cho, Kashihara-sh, Nara 78, 〒6340078, JP)
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