SHUFFLE PATTERN GENERATING CIRCUIT, PROCESSOR, SHUFFLE PATTERN GENERATING METHOD, AND INSTRUCTION

Title:

SHUFFLE PATTERN GENERATING CIRCUIT, PROCESSOR, SHUFFLE PATTERN GENERATING METHOD, AND INSTRUCTION

Document Type and Number:

WIPO Patent Application WO/2013/057872

Kind Code:

A1

Abstract:

A shift duplicating unit carries out a one-bit left bit shift of individual indexes on the basis of an index line (702) of four (bit width of eight bits) indexes that have been inputted, and outputs an index line (902) obtained by making two-by-two duplicates of each index. An adder then outputs a shuffle pattern (703) obtained by adding the values of 1, 0, 1, 0, 1, 0, 1, 0 in order from the left end to the index line (902).

Inventors:

UEDA KYOKO
BABA DAISUKE

Application Number:

PCT/JP2012/005819

Publication Date:

April 25, 2013

Filing Date:

September 13, 2012

Export Citation:

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Assignee:

PANASONIC CORP (JP)
UEDA KYOKO
BABA DAISUKE

International Classes:

G06F9/315; G06F7/76; G06F9/30

Foreign References:

JP2008513903A	2008-05-01
JP2007526536A	2007-09-13
US20020035678A1	2002-03-21
JP2004303203A	2004-10-28
JP2005174301A	2005-06-30

Other References:

CRAIG HANSEN: "MicroUnity's MediaProcessor Architecture", IEEE MICRO, August 1996 (1996-08-01), pages 34 - 41, XP000596511

Attorney, Agent or Firm:

NAKAJIMA, Shiro et al. (JP)
Shiro Nakajima (JP)

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