Title:
SiC WAFER MANUFACTURING METHOD
Document Type and Number:
WIPO Patent Application WO/2020/022415
Kind Code:
A1
Abstract:
In this SiC wafer (40) manufacturing method, a SiC wafer (40) is manufactured wherein a work-affected layer removal step for removing a work-affected layer generated on the surface and interior of the SiC wafer (40) has been performed and at least a portion of the work-affected layer has been removed. In the work-affected layer removal step, the SiC wafer (40), following a polishing step in which a reaction product is generated on the SiC wafer (40) by using an oxidizing agent and the reaction product is removed using abrasive grains, is etched by an etching amount of no more than 10 μm by heating under Si vapor pressure to remove the work-affected layer. In the SiC wafer (40) following the polishing step, internal stress attributable to the work-affected layer is generated inward of the work-affected layer, and by removing the work-affected layer in the work-affected layer removal step, the internal stress of the SiC wafer (40) is reduced.
Inventors:
YABUKI NORIHITO (JP)
NAKASHIMA YUJI (JP)
SAKAGUCHI TAKUYA (JP)
NOGAMI SATORU (JP)
KITABATAKE MAKOTO (JP)
NAKASHIMA YUJI (JP)
SAKAGUCHI TAKUYA (JP)
NOGAMI SATORU (JP)
KITABATAKE MAKOTO (JP)
Application Number:
PCT/JP2019/029161
Publication Date:
January 30, 2020
Filing Date:
July 25, 2019
Export Citation:
Assignee:
TOYO TANSO CO (JP)
International Classes:
H01L21/304; B24B37/00; H01L21/302
Domestic Patent References:
| WO2010090024A1 | 2010-08-12 | |||
| WO2015151411A1 | 2015-10-08 |
Foreign References:
| JP2008016691A | 2008-01-24 | |||
| JP2008166329A | 2008-07-17 | |||
| JP2017105697A | 2017-06-15 |
Attorney, Agent or Firm:
KATSURAGAWA, Naoki (JP)
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