METHOD THEREOF

TECHNICAL FIELD OF THE INVENTION

This invention relates to technical field of analog-to-digital converter (ADC) and, in particular, to a sigma-delta modulator based analog-to-digital converter and a dithering method thereof.

BACKGROUND OF THE INVENTION

Sigma-delta modulator (SDM) is one of critical parts in an oversampling analog-to-digital converters (ADCs) which is a type of ADC that requires multiple samplings for the complete conversion process. Sigma-delta modulator, whichever order it might be, by its nature, can introduce limit cycle at multiple input levels. The limit cycle produces repeating output pattern from the integrator as well as at the quantizer output. The output pattern, if it has frequencies components that fall inside a passband of an ADC, the output signal of the ADC can appear to be unstable even if the input signal is stable. This is called tones. Furthermore, a non-desirable limit cycles which produces tones, additionally causes undesired distortions, errors, or variations in the output signal as taught by, for example, Schreier, R., & Temes, G. C. (2004). Understanding Delta-Sigma Data Converters. The limit cycles can be reduced or eliminated by the process of dithering.

As well known by the person skilled in the art, dithering has been taught as adding a uniform random signal, called dither noise, which is the output signal of digital dither generator S _di , into the sigma-delta modulator loop at the input of the quantizer as shown in FIG. 1. The output pattern from limit cycles might be destroyed by the dither noise. The dither noise, as taught and as mathematically modelled, is also suggested to have a plurality of amplitudes which must be uniformly distributed and zero average over the ADC's operating period. It can be produced by, for example, multi-bit pseudo-random generator or true-random generator. One example of the analog apparatus of dither noise injection, as disclosed in this invention and some prior arts, can be to change the quantizer's input-referred offset level randomly.

Referring to the U.S. Patent No. 9,356,617 B2, the disclosed quantizer can be configured to receive a plurality of digital dither signals by a plurality of transistors in series with a plurality of input transistors configured to receive a signal from the integrator. This introduces a set of drawbacks i.e., the plurality of input transistors introduces a fixed load capacitance to the integrator, resulting in more power consumption from the integrator circuit. While the digital dither signal changes value, the kickback noise from the quantizer will be subsequently changed, depending on the digital dither signal value at a certain moment.

Referring to the U.S. Patent No. 6,473,019 Bl, the disclosed quantizer has an extra apparatus coupled directly to the output terminal of the input stage of the quantizer. The apparatus functions as a plurality of current sources or sinks, where the apparatus can be configured to receive a plurality of digital dither signals through the use of a current digital-to-analog converter. This requires both extra power and peripheral circuits to operate.

According to problems in the prior arts, the present invention aims to solve such problems including load capacitance, kickback noise variation with the dither noise and extra power consumption by integrating the disclosed apparatus of the present invention with the input stage of the quantizer while maintaining the input transistor's function. The input stage with the disclosed apparatus can be coupled to many suitable subsequence stages, as one example, the apparatus disclosed in U.S. Pat. No. 6,473,019 Bl. The features of the present invention will be described in the following detailed description and drawings which set illustrative embodiments in which the principles of the invention are utilized.

SUMMARY OF THE INVENTION

The present invention relates to a sigma-delta modulator based analog-to-digital converter (ADC) (100), comprising: a digital dither generator (101) configured to provide a plurality of digital dither signals Sdi. The digital dither generator (101) comprises a dither pattern generator (601) and a binary decoder (602); a sigma-delta modulator loop (102) configured to receive an input analog signal S _m and the plurality of digital dither signals Sdi, and to provide a quantizer output signal S _q ; and a processor (103) configured to provide a digital representation of the input analog signal S _m ; where the sigma-delta modulator loop (102) comprises: an integrator (104) configured to provide an integrator output signal S _mt ; a feedback digital to analog converter (DAC) (105) configured to receive the quantizer output signal S _q and to produce a feedback signal Sn,; and a quantizer (106) configured to receive the integrator output signal Smt and the plurality of digital dither signals Sdi and to output the quantizer output signal S _q , where the quantizer 106 comprises: an input stage (201) configured to receive the integrator output signal S _mt and the plurality of digital dither signals S _di and to provide an output signal S _CmP ; and a gain stage (202) configured to receive the output signal S _CmP and to output the quantizer output signal S _q . where input stage (201) comprises: a current source (301); a pair of input transistors (302) configured to produce first and second output current signals S _C urr_a, S _CU rr_b in relation to the integrator output signal Smt and a threshold signal St _hreshoid ; a load network (303) configured to convert the first and second output current signals S _C urr_a, Scurr_b into the output signals S _cmp _a, S _cmp _b of the input stage (201); and an analog dither circuit (304) characterized in that the analog dither circuit (304) coupled in series between the current source (301) and the pair of input transistors (302) and configured to receive the plurality of digital dither signals S _di and to divide a bias current from the current source (301) to each transistor of the pair of input transistors (302)

According to the present invention, the analog dither circuit (304) comprises a plurality of resistors (401) coupled in series and configured to provide resistance; and a plurality of transistors as switches (402) configured to function as switches. According to the present invention, the plurality of resistors (401) provide resistance between a first source terminal S _SO urce_a of the pair of input transistors (302) to an output Scmrent of the current source (301) and a second source terminal S _SO mce_b of the pair of input transistors (302) to the output S _c mr _e n _t of the current source (301).

According to the present invention, the plurality of resistors (401) providing resistance depending on current division ratio of the divided current.

According to the present invention, the transistors of the plurality of transistors as switches (402) are coupled with terminals of resistors of the plurality of resistors (401) at drain terminals.

According to the present invention, the plurality of transistors as switches (402) are coupled with the plurality of digital dither signals Sdi at control terminals (405).

According to the present invention, the plurality of transistors as switches (402) are coupled with the output S _c mr _e n _t of the current source (301) at source terminals (406).

According to the present invention, each transistor of the plurality of transistors as switches (402) is configured to provide a current path from the output S _c mr _e n _t of the current source (301) to one of the terminals of the plurality of resistors (401) when one of the transistors of the plurality of transistors as switches (402) is turned on.

According to the present invention, the transistor of the plurality of transistors as switches (402) providing the current path is controlled by the plurality of digital dither signals Sdi.

According to the present invention, each transistor of the plurality of transistors as switches (402) is configured to receive each signal of the plurality of digital dither signals Sdi.

According to the present invention, the plurality of digital dither signals S _di is generated from the binary decoder (602) and then received by the analog dither circuit (304).

According to the present invention, the binary decoder (602) is N-to-M binary decoder (701) configured to decode a plurality of binary representation of a dither pattern S _di-b m and to produce the plurality of digital dither signal Sdi, wherein a number of decoded output bits (M) are correlated to a number of a binary coded input (N), calculated as M = 2 ^N .

According to the present invention, the analog dither circuit (304), coupled in series between the first and second source terminals S _SO mce_a, S _SO mce_b of the pair of input transistors (302) and to the output S _c mr _e n _t of the current source (301).

According to the present invention, left and right terminals of the plurality of resistors (403, 404) are coupled to the first and second source terminals S _SO mce_a, S _SO mce_b respectively of the pair of input transistors (302).

According to the present invention, a number of the plurality of transistors as switches (402) are the same as a number of the plurality of digital dither signals S _di ; and a number of the plurality of resistors (401) are at least one more than the number of the plurality of transistors as switches (402).

According to the present invention, the plurality of resistors (401) can be replaced by a plurality of transistors, configured to function as resistors, biased in linear region.

According to the present invention, all resistors in the plurality of resistors (401) can be of the same predetermined values.

According to the present invention, each transistor of the plurality of transistors as switches (402) is only coupled with one digital dither signal from the plurality of digital dither signals Sdi. According to the present invention, the current division ratio of the divided current depends on the plurality of digital dither signals Sdi.

According to the present invention, the plurality of digital dither signals S _di control the current division ratio by controlling which transistor, belonging to the plurality of transistors as switches (402), to turn on.

According to the present invention, the current division ratio from the first and second source terminals S _SO urce_a, S _SOU rce_b of the pair of input transistors (302) affects the first and second output current signals S _CU rr_a, S _CU rr_b.

According to the present invention, the first and second output current signals S _CU rr_a, S _CU rr_b affects, in proportional values, the first and second output signals S _c p_a, S _c p_b of the input stage (201).

According to the present invention, only one digital dither signal from the plurality of digital dither signals S _di can be of logic HIGH at a given time.

According to the present invention, only one digital dither signal from the plurality of digital dither signals S _di to be logic HIGH can control a transistor in the plurality of transistors as switches (402) to turn on.

The present invention also relates to a dithering method of sigma-delta based modulator analog-to-digital converter (ADC), comprising: receiving an input analog signal Sm and a feedback signal S«, at an integrator (104) to provide an integrator output signal S _mt ; receiving the integrator output signal Smt and a plurality of digital dither signal Sdi at an input stage (201) of the quantizer (106) and comparing the integrator output signal Smt and the plurality of digital dither signals S _di against a threshold signal S _threshoid to produce an output signal S _cmp of the input stage (201); amplifying the output signal S _{c p} of the input stage (201) at a gain stage (202) to produce a quantizer output signal S _q ; receiving the quantizer output signal S _q at a processor (103) to produce a plurality of output digital signals S _ou t as a digital representation of the input analog signal Sm characterized in that receiving the plurality of digital dither signals S _di at control terminals (405) of a plurality of transistors as switches (402) to control the plurality of transistors as switches (402) as turning on or off; providing current from a current source (301) to first and second source terminals Ssource_a, S _S oiirce_b of a pair of input transistors (302) through the plurality of transistors as switches (402) and the plurality of resistors (401), respectively; receiving the integrator output signal Smt and the threshold signal Sthreshoid at control terminals (305) of the pair of input transistors (302); producing first and second output current signals S _CU rr_a, S _CU rr_b in relation to the integrator output signal Smt and the threshold signal Sthreshoid; and converting the first and second output current signals S _CU rr_a, S _CU rr_b at a load network (303) to the output signals S _cm p_a, S _cm p_b of the input stage (201).

According to the present invention, the dithering method of sigma-delta based modulator analog-to-digital converter (ADC), further comprising generating the plurality of digital dither signals Sdi at a binary decoder (602) of a digital dither generator (101). According to the present invention, generating the plurality of digital dither signals S _di includes generating logic HIGH and LOW of the plurality of digital dither signals S _di ; and propagating the logic HIGH and LOW of the plurality of digital dither signals S _di wherein controlling the plurality of transistors as switches (402) to turn on or off.

According to the present invention, controlling the plurality of transistors as switches (402) is turned on if logic HIGH and controlling the plurality of transistors as switches (402) is turned off if logic LOW.

According to the present invention, the dithering method of sigma-delta based modulator analog-to-digital converter (ADC), further comprising providing current path by one of transistors of the plurality of transistors as switches (402) turned on, from an output S _current of the current source (301) to one of the terminals of the plurality of resistors (401).

According to the present invention, the dithering method of sigma-delta based modulator analog-to-digital converter (ADC), further comprising dividing current between the first and second source terminals S _SO urce_a, S _SOU rce_b of the pair of input transistors (302) according to the current division ratio of the divided current, wherein controlled by transistor of the plurality of transistors as switches (402) which is turned on.

The general purpose of this invention is to provide multi-level analog dither signals using the analog dither circuit (304) with the plurality of digital dither signals to prevent, reduce or eliminate limit cycle in a sigma-delta modulator based ADC (100).

Another purpose of this invention is to provide multi-level analog dither signals using the analog dither circuit (304) while an offset effect of the integrator (104) and the quantizer (106) in the sigma-delta modulator based ADC (100) can be reduced or eliminated by configuring the plurality of digital dither signals S _di to have a specific average value that can reduce or eliminate the offset effect of the integrator (104) and the quantizer (106) in the sigma-delta modulator based ADC (100).

These purposes are achieved in accordance with the circuit features which have been briefly summarized above and which will be described in further detail with reference to the accompanying drawings.

BREIF DESCRIPTION OF THE DRAWING

Fig. 1 is an example block diagram of a sigma-delta modulator based ADC having a digital dither generator according to the invention.

Fig. 2 is an example block diagram of a quantizer of the sigma-delta modulator based ADC according to the invention.

Fig. 3 is an example implementation of an input stage of the quantizer of the sigma-delta modulator based ADC according to the invention.

Fig. 4 is an example implementation of an analog dither circuit of the quantizer of the sigma-delta modulator based ADC according to the invention having X dither signal levels.

Fig. 5 is an example embodiment of an analog dither circuit of the quantizer of the sigma-delta modulator based ADC according to the invention having seven dither signal levels.

Fig. 6 is an example block diagram of a digital dither generator of the sigma-delta modulator based ADC according to the invention.

Fig. 7 is an example implementation of a binary decoder, N-to-M binary decoder, of the digital dither generator of the sigma-delta modulator based ADC according to the invention. Fig. 8 is an example embodiment of the binary decoder as 3-to-8 binary decoder of the digital dither generator of the sigma-delta modulator based ADC according to the invention.

DETAILED DESCRIPTION

As recognized by the inventors of the U.S. Patent No. 9,356,617 B2, in order to sufficiently eliminate the effect of limit cycles in sigma-delta modulator based analog-to-digital converter (ADC), a dither signal with multiple levels added to the input of the quantizer is required. A general example of a first-order, sigma-delta modulator based ADC is presented here, however the working principle of this method and apparatus holds true for a higher order of sigma-delta modulator based ADC.

A general example of a sigma-delta modulator based ADC (100) is illustrated in Fig 1. The sigma-delta modulator based ADC (100) comprises a digital dither generator (101), a sigma-delta modulator loop (102) and a processor (103). A digital dither generator (101) is configured to provide a plurality of digital dither signals S _di . The sigma-delta modulator loop (102) is configured to receive an input analog signal S _m and the plurality of digital dither signals S _di of digital dither generator (101) to provide a quantizer output signal S _q . The bitstream representation is then processed via the processor (103); for example, a digital filter, to produce a plurality of output digital signals S _out as a digital representation of the input analog signal S _m . The sigma-delta modulator loop (102) comprises an integrator (104), a feedback digital to analog converter (DAC) (105) and a quantizer (106).

The quantizer (106) is coupled to an integrator (104) via an integrator output signal S _mt - The feedback DAC (105) is coupled to the quantizer (106) via the quantizer output signal S _q . The integrator (104) is also coupled to the feedback DAC (105) via a feedback signal S _fb .

The input analog signal S _m is received by the integrator (104). The integrator (104), when receiving the input analog signal S _m and the feedback signal S _fb , produces the integrator output signal S _mt representing an integration of a summation product of the input analog signal S _m and the feedback signal S _fb , to the quantizer (106).

In another embodiment according to this invention, the integrator (104) can produce the integrator output signal S _mt up to 2 signals.

The quantizer (106) receives the integrator output signal S _mt from the integrator (104) and receives a plurality of digital dither signals S _di from the digital dither generator (101). The quantizer (106) can be a single-bit or a multi-bit quantizer. For example, the quantizer (106) as single-bit quantizes the integrator output signal S _mt with a particular single threshold in combination with the plurality of digital dither signals S _di and outputs the quantizer output signal S _q as a representation of the input analog signal S _m and the plurality of digital dither signals S _di .

In another embodiment, the quantizer (106) as multi-bit quantizes the integrator output signal S _mt with a plurality of thresholds in combination with the plurality of digital dither signals S _di and outputs the quantizer output signal S _q as a representation of the input analog signal S _m and the plurality of digital dither signals S _di .

In some examples, the plurality of digital dither signals S _di can be used to alter the single threshold or the plurality of thresholds of the quantizer (106) to produce dithering with analog dither circuit (304).

In some further examples, the plurality of digital dither signals S _di is configured to prevent limit cycles from the sigma-delta modulator based ADC (100). The feedback DAC (105) receives the quantizer output signal S _q to produce the feedback signal S«, as the sigma-delta modulator loop feedback.

In an example of a sigma-delta modulator based ADC (100), the feedback DAC (105) can be configured as a direct feedback path.

In an example, the feedback DAC (105) can be configured as a direct feedback path in the sigma-delta modulator loop (102) with the single-bit quantizer.

The quantizer (106), as an example according to this invention, comprises an input stage (201) and a gain stage (202) as illustrated in Fig.2. The input stage (201) can receive two input signals, comprising the integrator output signal Smt and the plurality of digital dither signals Sdi from the digital dither generator (101). The input stage (201) is configured to compare the integrator output signal Smt and the plurality of digital dither signals Sdi against a threshold signal Sthreshoid to produce an output signal S _c p of the input stage (201) to represent the result of the comparison. In an example, the threshold signal S _threshoid can be generated using a bandgap voltage reference.

In another embodiment, the input stage (201) can be configured to compare the integrator output signal Smt and the plurality of digital dither signals Sdi against a plurality of threshold signals Sthredhoid to produce a plurality of output signals S _c p of the input stage (201) to represent the result of the comparison. In an example, the plurality of threshold signals S _thredhoid can be generated using a plurality of resistors coupled in series to form a voltage divider.

The gain stage (202) is configured to receive the output signal S _c p of the input stage (201) and then, as an example, to amplify the output signal S _c p of the input stage (201) to produce the quantizer output signal S _q appropriated to be received by the subsequent stage.

In further example, the gain stage (202) can include a latch to produce the quantizer output signal S _q in a dynamic quantizer.

In an example implementation, the input stage (201) comprises a current source (301), a pair of input transistors (302), a load network (303) and an analog dither circuit (304) as illustrated in Fig.3. The current source (301) is coupled with the analog dither circuit (304). The analog dither circuit (304) is coupled in series between the current source (301) and the pair of input transistors (302).

The current source (301) has a purpose of maintaining a bias current for the rest of the components in the input stage (201). The pair of input transistors (302) receives the integrator output signal Smt and the threshold signal Sthreshoid at control terminals (305) of the pair of input transistors (302). The pair of input transistors (302) then produces first and second output current signals S _CU rr_a, Scurr_b in relation to the integrator output signal Smt and the threshold signal Sthreshoid respectively to be received by the subsequent load network (303). For example, the first output current signal S _CU rr_a can be higher than the second output current signal S _CU rr_b when the integrator output signal Smt is higher than the threshold signal Sthreshoid-

In another embodiment, the first output current signal S _CU rr_a can be lower than the second output current signal S _CU rr_b when the integrator output signal Smt is lower than the threshold signal Sthreshoid-

The load network (303) serves as a means to convert the first and second output current signals S _CU rr_a, Scurr_b from the pair of input transistors (302) into the first and second output signals Scurr_a, Sciirr_b of the input stage (201) to be amplified by the subsequent stages. As a general example, the load network (303) can be realized by a number of ways, depending on the intended specification and its subsequent stage. In an example embodiment, the load network 303 can be realized as a pair of resistors, where one terminal of the resistors is connected to the power supply and the other is connected to receive the first and second output current signals S _C mr_a, S _C urrj>.

In another embodiment, the load network (303) can be realized by a network of transistors, configured to work in saturation region to achieve a high voltage gain.

The analog dither circuit (304), as an example implementation, is coupled in series between the first and second source terminals s _so ur _ce-a, s _so ur _ce-b of the pair of input transistors (302) and to an output S _c r _e n _t of the current source (301) and is coupled to the plurality of digital dither signals Sdi.

Fig 4 illustrates an example embodiment of the analog dither circuit (304) according to this invention. The analog dither circuit (304) comprises a plurality of resistors (401) biased in linear region, coupled in series, and a plurality of transistors as switches (402). The transistors belonging to the plurality of transistors as switches (402) are configured to function as switches. The plurality of resistors (401) can comprise R0 through RX, coupled in series, all of which can be of the same or different predetermined resistance values. The plurality of transistors as switches (402) comprise M0 through MY. The number of the plurality of transistors as switches (402) must be the same as the number bits of the plurality of digital dither signals Sdi. The number of the plurality of resistors (401) must be at least one more than the number of the plurality of transistors as switches (402).

In another embodiment, the plurality of resistors (401) can be replaced by a plurality of transistors biased in linear region.

Fig. 5 illustrates an example embodiment of the analog dither circuit (304) which is coupled in series between the first and second source terminals S _SO urce_a, S _So m _ce-b Of the pair of input transistors (302) and to the output S _c mr _e n _t of the current source (301) and is coupled to the plurality of digital dither signals Sdi. The analog dither circuit (304) comprises the plurality of resistors (401) biased in linear region, coupled in series and the plurality of transistors as switches (402). The plurality of resistors (401) can comprise a first resistor R0 through an eighth resistor R7, all of which can be of the same or different predetermined resistance values. The plurality of transistors as switches (402) can comprise a first transistor M0 through a seventh transistor M6. The left and right terminals (403, 404) of the plurality of resistors (401) are coupled to the first and second source terminals S _S omce_a, S _S o ce_b respectively of the pair of input transistors (302) Ssomce_a, Sso ce_b· Transistors of the plurality of transistors as switches (402) are coupled with terminals of resistors belonging to the plurality of resistors (401) at drain terminals.

The example embodiment according to Fig.5 is described as follows.

A drain terminal (501) of first transistor M0 is coupled to the terminal between the first resistor R0 and a second resistor Rl. A drain terminal (502) of second transistor Ml is coupled to the terminal between the second resistor Rl and a third resistor R2. A drain terminal (503) of third transistor M2 is coupled to the terminal between the third resistor R2 and a fourth resistor R3. A drain terminal (504) of fourth transistor M3 is coupled to the terminal between the fourth resistor R3 and a fifth resistor R4. A drain terminal (505) of fifth transistor M4 is coupled to the terminal between the fifth resistor R4 and a sixth resistor R5. A drain terminal (506) of sixth transistor M5 is coupled to the terminal between the sixth resistor R5 and a seventh resistor R6. And a drain terminal (507) of seventh transistor M6 is coupled to the terminal between the seventh resistor R6 and a eighth resistor R7. The plurality of digital dither signals Sdi are coupled to the plurality of transistors as switches (402) at control terminals (405) such that each transistor of the plurality of transistors as switches (402) is only, but not limited to, coupled with one digital dither signal from the plurality of digital dither signals Sdi. The plurality of transistors as switches (402) are coupled with the output S _cmrent of the current source (301) at source terminals (406).

The analog dither circuit (304) divides the bias current from the current source (301) to each transistor, belonging to the pair of input transistors (302), in which the current division ratio of the divided current depends on the plurality of digital dither signals Sdi. The plurality of digital dither signals Sdi controls the current division ratio by controlling which transistor, belonging to the plurality of transistors as switches (402), to turn on. When one of the transistors, belonging to the plurality of transistors as switches (402), is turned on, the transistor provides a current path from the output S _cmrent of the current source (301) to one of the terminals of the plurality of resistors (401).

In an example of the operation of the analog dither circuit (304) referred to Fig.5, the plurality of digital dither signals Sdi controls the fourth transistor M3 to turn on while the others, first transistor M0 through third transistor M2 and fifth transistor M4 through seventh transistor M6 are turned off. In this example, a current path between the output S _cmrent of the current source (301) and the terminal between the fourth resistor R3 and the fifth resistor R4 is provided by the fourth transistor M3. The current between the first and second source terminals S _SO mce_a, S _source-b of the pair of input transistors (302) is divided equally because the resistance between the first source terminal S _SO mec_a of the pair of input transistors (302) to the output Scmrent of the current source (301) is equal to the resistance between the second source terminal S _SO mce_b of the pair of input transistors (302) and to the output S _cmrent of the current source (301), this assumes that the voltage at the first and second source terminals S _SO mce_a, S _S omce_b of the pair of input transistors (302) are the same.

In further example of the operation of the analog dither circuit (304) referred to Fig.5, the plurality of digital dither signals Sdi controls the second transistor Ml to turn on while the others, first transistor M0 and third transistor M2 through seventh transistor M6 are turned off. In this example, a current path between the output S _cmrent of the current source (301) and the terminal between the second resistor R1 and the third resistor R2 is provided by the second transistor Ml. The current between the first and second source terminals S _SO mce_a, S _SO mce_b of the pair of input transistors (302) is divided with a ratio of 3:1 because the resistance between the first source terminal S _SO mce_a of the pair of input transistors (302) to output Scmrent of the current source (301) is three times less than the resistance between the second source terminal S _SO mce_b of the pair of input transistors (302) to output Scmrent of the current source (301), this assumes that the voltage at the first and second source terminals S _S omce_a, S _SO mce_b of the pair of input transistors (302) are the same. Such difference in current values between the first and second source terminals S _SO mce_a , S _SO mce_b of the pair of input transistors (302), controlled by the plurality of digital dither signals Sdi, also affects, regarding their values, the first and second output current signals S _C mr_a, S _C mr_B, according to the current division ratio from the first and second source terminals S _SO mce_a, S _SO mce_b of the pair of input transistors (302), which affects, regarding their values, the first and second output signals S _c p_a, S _c p_b of the input stage (201) proportional to the first and second output current signals S _C mr_a, S _C mr_b, regarding their values, respectively. Fig.6 illustrates an example block diagram of the digital dither generator (101) according to this invention. The digital dither generator (101) comprises a dither pattern generator (601) and a binary decoder (602) which are coupled together. The binary decoder (602) is configured to receive, for example, a plurality of binary representation of a dither pattern S _di-bm from the dither pattern generator (601) and to output the plurality of digital dither signals Sdi.

The dither pattern generator (601) generates the plurality of binary representation of a dither pattern Sdi_bm- The dither pattern generator (601) can comprise, for example, a pseudo random pattern generator.

The plurality of binary representation of a dither pattern S _di-bm from the dither pattern generator (601) can have a set of preferable characteristics such as a uniform amplitude distribution, multi levels of amplitude representation, or a random pattern or combination of the mentioned.

The plurality of binary representation of a dither pattern S _di-bm is received by the binary decoder (602) which generates the plurality of digital dither signals Sdi, received by the analog dither circuit (304).

Fig 7 illustrates example implementation of the binary decoder (602) of the digital dither generator (101) according to the invention. The binary decoder (602) mainly comprises a N-to- M binary decoder (701) for decoding the plurality of binary representation of a dither pattern Sdi_bin, which is as a plurality of binary coded inputs, aO to a(N-l). The N-to-M binary decoder (701), then produces the plurality of digital dither signals Sdi, which is as a plurality of decoded outputs, bO to b(M-l). A number of decoded output bits (M) are correlated to a number of binary coded input bits (N) and can be calculated as M = 2 ^N . The state of the plurality of decoded outputs corresponds to the binary value of the plurality of binary coded inputs. The plurality of decoded outputs with the number of decoded output bits equal to M can be referred to as a M -bit decoded output. The plurality of binary coded inputs with the number of binary coded input bits equal to N can be referred to as a N-bit binary coded input.

As would be well known by the person skilled in the art, a suitable value for M is dictated by the required number of levels of amplitude of dithering, which depends on the requirement of the practical system.

Fig.8 illustrates an example embodiment of the binary decoder (602) according to this invention suitable for, but not limited to, the analog dither circuit (304) referred to Fig.5. In this example, the binary decoder (602) comprises a 3-to-8 binary decoder (801) which receives a 3- bit binary coded input (also meaning three representations of a dither pattern of the plurality of representation of a dither pattern) and then produces an 8-bit decoded output (also meaning eight digital dither signals of the plurality of digital dither signals Sdi). In a certain example of the 3-to-8 binary decoder (801), the 3-to-8 binary decoder (801) can include three NOT gates (901) and eight three-input AND gates (902), connected in a specific way, as shown in Fig.8. The 8-bit decoded output, which is able to refer to in this example as the plurality of digital dither signals Sdi, is coupled to the control terminals (405) of the plurality of transistors as switches (402), where one of the 8-bit decoded output is to be intentionally left unconnected because the number of transistors belonging to the plurality of transistors as switches (402) is seven while the number of decoded output bits is equal to eight.

As an example, referring to Fig.5 and Fig.8, some signals belonging to the plurality of decoded outputs, for example bl to b7, are respectively coupled to the transistors, for example MO to M6, belonging to the plurality of transistors as switches (402) where, in this example, bO is to be intentionally left uncoupled. If, for example, the state of the inputs belonging to the plurality of binary coded inputs have the digital logic LOW at aO, the digital logic HIGH at al and the digital logic LOW at a2, only the decoded output b2, belonging to the plurality of decoded outputs, has the digital logic HIGH, which turns the transistor Ml belonging to the plurality of transistors as switches (402) on since the decoded output b2 is directly coupled with the transistor Ml, belonging to the plurality of transistors as switches (402). While the decoded outputs bl, b3, b4, b5, b6 and b7, belonging to the plurality of decoded outputs have the digital logic LOW which turn the transistors MO, M2, M3, M4, M5 and M6 belonging to the plurality of transistors as switches (402) off.

Noted that for the plurality of decoded outputs which is as the plurality of digital dither signals Sdi, only one of the plurality of the decoded outputs can be of logic HIGH at a given time. The decoded output (also called digital dither signal) of the plurality of decoded outputs which is of logic HIGH, controls only one transistor, coupled with the decoded output, in the plurality of transistors as switches (402) to turn on, while turning off for other transistors in the plurality of transistors as switches (402).

In a practical system, depending on the dithering requirement of the sigma-delta modulator based ADC (100), the number of bits generated from the digital dither generator (101) can be less for simplicity and relatively lower cost and for more uniform distribution of the plurality of digital dither signals Sdi. The number of the binary coded input bits must be the same as the number of bits generated from the dither pattern generator (601). The number transistors, belonging to the plurality of transistors as switches (402) in the analog dither circuit (304) must be the same as the number of the decoded output bits.