Field

The present disclosure generally relates to signal distribution circuitry and, more particularly, to methods and transceiver circuits for distributing a Local Oscillator (LO) signal to one or more antenna elements.

Background

In various circuits, one or more signals may need to distributed from one circuit portion to one or more other circuit portions. In Multiple-Input Multiple- Output (MIMO) transceiver systems, for example, an LO signal usually needs to be distributed over a distance of several millimeters to each antenna. This can mean a quite large amount of capacitance to drive, especially in IQ (I = Inphase, Q = Quadrature) transmission systems. Voltage domain signaling often needs several repeaters to keep the signal swing, known as power consuming and less immune to supply noise. Conventional current domain LO distribution usually suffers from low intermediate swing, therefore phase noise penalty, which is important for the transceiver system. Some systems use inductors as current to voltage converters to increase the swing. However, this can occupy more chip area with an additional risk of electromagnetic interference (EMI) and isolation problems. This is undesired in a multi-synthesizer MIMO system.

Brief description of the Figures

Some examples of apparatuses and/or methods will be described in the following by way of example only, and with reference to the accompanying figures, in which

Fig. 1 shows a conventional current domain clock signal distribution circuit;

Fig. 2 shows a signal distribution circuit according to a first example;

Fig. 3 shows a differential signal distribution circuit according to a second example;

and Fig. 4 shows a block diagram of a Wireless Local Area Network (WLAN) device according to an example. Detailed Description

Various examples will now be described more fully with reference to the accompanying drawings in which some examples are illustrated. In the figures, the thicknesses of lines, layers and/or regions may be exaggerated for clarity.

Accordingly, while further examples are capable of various modifications and alternative forms, some particular examples thereof are shown in the figures and will subsequently be described in detail. However, this detailed description does not limit further examples to the particular forms described. Further examples may cover all modifications, equivalents, and alternatives falling within the scope of the disclosure. Like numbers refer to like or similar elements throughout the description of the figures, which may be implemented identically or in modified form when compared to one another while providing for the same or a similar functionality. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, the elements may be directly connected or coupled or via one or more intervening elements. If two elements A and B are combined using an "or", this is to be understood to disclose all possible combinations, i.e. only A, only B as well as A and B. An alternative wording for the same combinations is "at least one of A and B". The same applies for combinations of more than 2 Elements.

The terminology used herein for the purpose of describing particular examples is not intended to be limiting for further examples. Whenever a singular form such as "a," "an" and "the" is used and using only a single element is neither explicitly or implicitly defined as being man- datory, further examples may also use plural elements to implement the same functionality. Likewise, when a functionality is subsequently described as being implemented using multiple elements, further examples may implement the same functionality using a single element or processing entity. It will be further understood that the terms "comprises," "comprising," "includes" and/or "including," when used, specify the presence of the stated features, integers, steps, operations, processes, acts, elements and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, processes, acts, elements, components and/or any group thereof. Unless otherwise defined, all terms (including technical and scientific terms) are used herein in their ordinary meaning of the art to which the examples belong.

As semiconductor technologies become densely integrated into Systems-on-Chip (SoC) and operate at increasingly higher frequencies, the importance of clocking becomes more empha- sized. It has been observed that clock trees account for considerable amount of a chip's total power consumption. In addition, a clock signal integrity of global interconnects is affected due to increased noise and delay in the Very Deep Submicron (VDSM) domain. This can be overcome by implementing the global interconnects as a separate communication network, called Networks-on-Chip (NoC). Due to its regular geometry, the electrical and physical prop- erties of the interconnection network are potentially much more predictable. Hence, NoCs present a reliable platform for data transmission and clock distribution, using conventional voltage mode signaling techniques.

However, with system frequencies of 10GHz and more, voltage mode signaling techniques, which face serious limitations in operating beyond 5GHz, reach their limits. Hence, alternative signaling techniques, such as current domain signaling, which can provide faster and reliable performance in these high frequencies need to be explored. The high-bandwidth, low power consumption and increased noise immunity over voltage mode circuits make the current mode signaling technique an appropriate choice for a clock network.

Fig.l shows a conventional current domain signaling approach which can be applied for Net- work-on-Chip (NoC) clock distribution. As shown in Fig.1 , the circuit 100 uses a bidirectional voltage to current conversion circuit, and a modified trans-impedance amplifier. When input Vin is 'high' , it works like a normal cascode amplifier, the output V _ou t goes 'low' . When input Vin is 'low', it opens the cascode device MN2 to let the current charging from supply Vdd through a diode to load impedance, end up with output voltage level V _X one threshold VGS below supply Vdd. An appropriately sized CMOS inverter is as driver 1 10. Interconnects 120 between driver 1 10 and receiver circuit 130 are modeled as RLC wires. The receiver circuit 130 comprises a modified transimpedance amplifier and a series of inverters that produce a full swing voltage output that drive connected loads. The transistor MNI serves to provide a low impedance path to ground for current sourced by the driver 1 10. The width of the transistor is increased and positive feedback from the output V _Rx is fed to its gate to make it operate in saturation, thus providing a matched impedance. Transistor Mp ₂ provides a constant current bias thus regulating the transconductance of the input transistor MN2. The current signal from the 120 interconnect is fed to the source terminal of transistor MN2. The direction of current in the inter- connect determines the source voltage and hence the region of operation of MN2. The transistor MN2 turns on when the source voltage is low (current sunk by driver 1 10) and pulls the output V _Rx low. When current is sourced by the driver 1 10, the source voltage of transistor MN2 rises thus turning it off. Now the current flows through the load transistor MN3 to the load capacitance, thus charging it up to Vdd - Vth,MN3. The operation of the transistor MN2 is aided by the negative feedback provided by transistor Mpi which turns the gate of MN2 on and off as required and helps in modulating the input impedance. Transistor Mp2 is diode-connected and hence acts as a constant current bias. The output voltage generated by the receiver circuit 130 is ensured to have a rail-to-rail swing by passing it through a series of two inverters 131 , 132 sized appropriately.

The conventional clock distribution circuit 100 has two drawbacks when applying it to a Radio Frequency (RF) transceiver system. Firstly, the output swing can only go as high as to one threshold below supply (Vdd-VGs), which could be even lower in case the input is not CMOS signal driven (e.g. 'high',/'low') or the signal at the drain of Mpi is not high enough to open the cascode device MN2. Secondly, there is nearly no current flowing through the transmission line (TML) between the current mode driver and the receiver circuit when input Vi _n is low, where the magnetic coupling could show up in a differential signal transmission system like the RF transceiver. And since there is no current flowing through TML on one half of the duty-cycle of the input signal, a Root Mean Square (RMS) current will flow through TML, therefore IR drop needs to be considered in the signal line design.

Fig. 2 shows an example of a signal distribution circuit 200 according to the present disclosure. The signal distribution circuit 200 can be used for current domain NoC clock distribution, for example. The example signal distribution circuit 200 comprises an input circuit portion 210 configured to convert an input voltage signal Vp to a current signal 215. The input circuit portion 210 comprises at least a first and a second input amplifier device 211, 212. In the illustrated ex- ample, the input circuit portion 210 is implemented as a CMOS inverter.

The signal distribution circuit 200 also comprises an output circuit portion 220 coupled to the input circuit portion 210 and configured to convert the current signal 215 to an output voltage signal outp. The output circuit portion 220 comprises at least a first and a second output am- plifier device 221, 222. The signal distribution circuit 200 is configured to form a first cascode of a first pair of input and output amplifier devices 211, 221 during a first time interval of the input voltage signal Vp and to form a second cascode of a different second pair of input and output amplifier devices 212, 222 during a second time interval of the input voltage signal Vp. A control terminal of the output amplifier device 221 of the first cascode is coupled to a constant bias signal Vb.

The skilled person having benefit from the present disclosure will appreciate that amplifier devices can be transistors of different technologies as well as tube amplifier devices, for example. While in the following examples of the present disclosure will be explained using field-effect transistors (FETs), the skilled person having benefit from the present disclosure will appreciate that other transistor technologies, such as bipolar junction transistors (BJTs), may also apply.

The example input circuit portion 210 can be coupled to a Local Oscillator (LO) circuit (not shown) which can generate the sinusoidal input voltage signal Vp. The output circuit portion 220 can be configured to generate a sinusoidal output voltage signal outp in response to the sinusoidal input voltage signal Vp. If the output circuit portion 210 is coupled to one or more antennas, the output voltage signal outp can be used to drive the one or more antennas, for example.

The example signal distribution circuit 200 enables bidirectional voltage to current conversion. Vp can be a single-ended LO signal in voltage domain, usually provided by a synthesizer. Mlp can be a p-channel MOSFET (PMOSFET), Ml can be a n-channel MOSFET (NMOSFET). Together they form a CMOS inverter performing the voltage to current conversion. The drain terminal of input transistor Mlp is coupled to drain terminal of input transistor Ml. The coupled drain terminals provide the current signal 215, which is transferred to or from output circuit portion 220 via transmission line (TML) 230.

Transistor M3 can be a NMOSFET. Rb, coupled between a constant biasing voltage Vb and the gate of M3, can be a resistor used for biasing M3. RL, coupled between Vdd and drain of M3, is the resistor to change current to voltage. Transistor M5 can be a PMOSFET in diode connection (gate and drain coupled to ground), which provides a low impedance path for current sinking when input (Vp) is low. The source terminal of output transistor M3 is coupled to source terminal of output transistor M5. The coupled source terminals provide the current signal 215, which is transferred to or from input circuit portion 210 via transmission line (TML) 230. In other words, the drain terminals of input transistors Mlp and Ml are coupled to the source terminals of output transistors M3 and M5 via TML 230.

The example signal distribution circuit 200 works in the following way: when input voltage signal Vp is high, the input p-channel MOSFET (PMOSFET) 212 is open, while the input n- channel MOSFET (NMOSFET) 211 conducts. The input NMOSFET 211 converts voltage to current which reaches the drain of output NMOSFET 221 via transmission line (TML) 230. In applications related to Wireless Local Area Network (WLAN) transceivers, the transmission line 230 can have lengths over 2 mm or even over 3 mm. Output NMOSFET 221 is common gate connected. Its gate terminal is connected to a constant bias voltage Vb. In this phase of the input voltage signal Vp, the pair of common-source input transistor 211 and common-gate output transistor 221 form the first cascode. Output NMOSFET 221 delivers the current 215 to load resistor 224, generating the output voltage outp. In this phase of the input voltage signal Vp, the voltage on the drain of output PMOSFET 222 is low, hence PMOSFET 222 is open. Current through TML 230 is from output circuit portion 220 to input circuit portion 210. When input voltage signal Vp is low, the input PMOSFET 212 conducts, while the input NMOSFET 211 is open. Input PMOSFET 212 converts the voltage to current. Since the voltage on the source of output NMOSFET 221 is high, leading to V _G s<Vth, the output NMOSFET 221 is not conductive during this phase of the input voltage signal Vp output PMOSFET 222 sinks the current 215 to ground during this phase of the input voltage signal Vp and current through TML 230 is from the input circuit portion 210 to the output circuit portion 220. In this phase of the input voltage signal Vp, the pair of common-source input transistor 212 and common-gate output transistor 222 form the second cascode. Since output NMOSFET 221 is open, current from supply Vdd goes over load resistor 224 charging load capacitance (e.g. of antenna) to supply.

As has been explained in the section above, the signal distribution circuit 200 is configured for a current flow from the output circuit portion 220 to the input circuit portion 210 during the first time interval (e.g. Vp > 0) and a current flow from the input circuit portion 210 to the output circuit portion 220 during the second time interval (e.g. Vp < 0).

While Fig. 2 relates to a circuit example for single-ended signals, the present disclosure also addresses differential signaling. A circuit example for differential signaling, which can also be used for current domain NoC clock distribution, is shown in Fig. 3.

The example signal distribution circuit 300 of Fig. 3 also comprises an input circuit portion 210 configured to convert a differential input voltage signal Vp/Vn to a differential current signal 215/215' . The input circuit portion 210 comprises a first and a second input amplifier device 211, 212 for the Vp signal portion and corresponding third and fourth input amplifier devices 211 ', 212' for the complementary Vn signal portion. In the illustrated example, the input circuit portion 210 is implemented as a differential inverter.

The signal distribution circuit 300 also comprises an output circuit portion 220 being differentially coupled to the input circuit portion 210 and configured to convert the differential current signal 215 to a differential output voltage signal outp/outn. The output circuit portion 220 comprises a first and a second output amplifier device 221, 222 for the outp signal portion and corresponding third and fourth output amplifier devices 221 ', 222' for the complementary outn signal portion. The coupling between the input amplifier devices 211, 212 and the output amplifier devices 221, 222 as well as the input amplifier devices 21 Γ, 212' and the output amplifier devices 221 ', 222' corresponds to the single-ended coupling of Fig. 2, respectively.

The signal distribution circuit 300 is configured to form a first cascode of a first pair of input and output amplifier devices 211, 221 during a first time interval of the input voltage signal Vp and to form a second cascode of a different second pair of input and output amplifier devices 212, 222 during a second time interval of the input voltage signal Vp. Likewise, the signal distribution circuit 300 is configured to form a first cascode of a first pair of input and output amplifier devices 211 ', 22 during a first time interval of the complementary input voltage signal Vn and to form a second cascode of a different second pair of input and output amplifier devices 212' , 222' during a second time interval of the complementary input voltage signal Vn. Control terminals of the output amplifier devices 221, 221 ' of the first cascode are coupled to a constant bias signal Vb

In the example of Fig. 3, Vp and Vn is the differential LO signal in voltage domain, usually provided by a synthesizer. Mlp, M2p are PMOS transistors, Ml, M2 are NMOS transistors, together they make the differential voltage to current conversion. In order to suppress the surrounding noise and also not affect the other signals, differential lines are used for signal transmission. TML is the lines, which is usually several millimeter long, surrounded by metals connected to ground for isolation in RF systems.

M3 and M4 are NMOS transistors, together with optional capacitors Cc 225, 225', forming a cross coupled pair to boost the gain, which means increase the output swing. In the illustrated example, optional capacitor 225 is coupled in the path between the source of transistor M4 and the gate of transistor M3. Likewise, optional capacitor 225' is coupled in the path between the source of transistor M3 and the gate of transistor M4. Rb, coupled between a constant biasing voltage Vb and the gates of M3, M4, is a resistor used for biasing M3 and M4, and Vb is the biasing voltage. RL, coupled between Vdd and the drains of M3 and M4, is the resistor to change current to voltage. M5 and M6 are transistors in diode connection, which provides a low impedance path for current sinking when input (Vp/Vn) is low.

Examples replace the load transistor MN3 of Fig. 1 with resistor RL 224 to eliminate the threshold lose on the output swing. The diode connected PMOS transistor M5 (/M6) can provide a low impedance path to sink the current when V2I input is low and stop the current flowing through cascode device M3 (/M4). This can enable the output node charging to Vdd. Bidirectional current flowing through TML 230 can cancel the magnetic coupling on the differential signal lines for RF transceiver systems.

Examples of the present disclosure can make the current domain LO distribution possible in WLAN 1 lax RF transceiver development, which can save 40% of current in block level (from 40mA/ Antenna to 24mA/ Antenna) compared to former WLAN generation while keeping the PN performance. And it also makes the cooling of the whole chip much easier. IEEE 802.1 lax is a type of WLAN in the IEEE 802.11 set of types of WLANs. It is designed to improve overall spectral efficiency, especially in dense deployment scenarios. It is still in a very early stage of development, but is predicted to have a top speed of around 10 Gb/s. IEEE 802.1 lax is designed to operate in the already existing 2.4 GHz and 5 GHz spectrums. In addition to utilizing MIMO and MU-MIMO, the new amendment introduces OFDMA to improve overall spectral efficiency, and higher order 1024 QAM modulation support for increased throughput. Though the nominal data rate is just 37 % higher than IEEE 802.1 lac, the new amendment is expected to achieve a 4 x increase to user throughput— due to more efficient spectrum utilization.

Thus, one example of the present disclosure is also a WLAN device, such as a WLAN access point for example. A high-level block diagram of an example WLAN device 400 is shown in Fig. 4.

The WLAN device 400 comprises at least one or, in case of MIMO, more antenna elements 402. The WLAN device 400 also comprises a Local Oscillator circuit 404 configured to generate an oscillating LO voltage signal 406. A signal distribution circuit 410 of the WLAN device 400 is configured to distribute the LO voltage signal 406 from the LO circuit 404 to the one or more antenna elements 402. Thereby the signal distribution circuit can be implemented according to one of the above examples 200 or 300.

The following examples pertain to further embodiments.

Example 1 is a signal distribution circuit. The signal distribution circuit comprises an input circuit portion configured to convert an input voltage signal to a current signal. The input circuit portion comprises at least a first and a second input amplifier device. The signal distribution circuit also comprises an output circuit portion coupled to the input circuit portion and configured to convert the current signal to an output voltage signal. The output circuit portion comprises at least a first and a second output amplifier device. The signal distribution circuit is configured to form a first cascode of a first pair of input and output amplifier devices during a first time interval of the input voltage signal and to form a second cascode of a different second pair of input and output amplifier devices during a second time interval of the input voltage signal. A control terminal of the output amplifier device of the first cascode is coupled to a constant bias signal.

In Example 2, the signal distribution circuit of Example 1 can have a input circuit portion comprising at least one CMOS inverter device comprising an input NMOS and PMOS FET.

In Example 3, the signal distribution circuit of Examples 1 or 2 can have an output circuit portion comprising at least one common-gate NMOS output transistor and at least one common-gate PMOS output transistor.

In Example 4, the gate of the common-gate NMOS output transistor of Example 3 is connected to a constant bias voltage.

In Example 5, the gate of the common-gate PMOS output transistor of Examples 3 or 4 is connected to ground.

In Example 6, a drain and a gate terminal of the common-gate PMOS output transistor of Example 5 are coupled to ground. In other words, the common-gate PMOS output transistor can be in diode connection.

In Example 7, the signal distribution circuit of any one of Examples 3 to 6 is configured to form the first cascode using a pair of input and output NMOS transistors during the first time interval and to form the second cascode using a pair of input and output PMOS transistors during a second time interval of the input voltage signal.

In Example 8, an input terminal of the output circuit portion of any one of Examples 3 to 7 is coupled to a source terminal of the common-gate NMOS output transistor and coupled to a source terminal of the common-gate PMOS output transistor. In Example 9, a drain terminal of the common-gate NMOS output transistor of any one of Examples 3 to 8 is coupled to a supply terminal via a resistor.

In Example 10, a gate terminal of the common-gate NMOS output transistor of any one of Examples 3 to 9 is coupled to a capacitor and/or to a resistor. In Example 11, the output circuit portion of any one of the previous Examples is coupled to the input circuit portion via at least one transmission line extending over more than 2 mm or even more than 3 mm.. In Example 12, the transmission line of Example 12 is coupled between a first and a second amplifier stage of the first cascode and of the second cascode.

In Example 13, the input circuit portion of any one of the previous Examples is coupled to a LO circuit generating a sinusoidal input voltage signal and wherein the output circuit portion is configured to generate a sinusoidal output voltage signal in response to the sinusoidal input voltage signal.

In Example 14, the output circuit portion of any one of the previous Examples is coupled to one or more antennas to drive the one or more antennas using the output voltage signal.

In Example 15, the input and out voltage signals of any one of the previous Examples are differential signals, respectively, and the signal distribution circuit of any one of the previous Examples comprises a respective input and output circuit portion of any one of the previous Examples for both signal components of the differential signals.

In Example 16, the signal distribution circuit of any one of the previous Examples is configured for a current flow from the output circuit portion to the input circuit portion during the first time interval and a current flow from the input circuit portion to the output circuit portion during the second time interval.

Example 17 is a WLAN device. The WLAN device comprises one or more antenna elements. The WLAN device also comprises a Local Oscillator circuit configured to generate an LO voltage signal. A signal distribution circuit of the WLAN device is configured to distribute the LO voltage signal from the LO circuit to the one or more antenna elements. Thereby the signal distribution circuit comprises an input circuit portion configured to convert the LO voltage signal to a current signal. For that purpose the input circuit portion comprises at least a first and a second input amplifier device. An output circuit portion of the signal distribution circuit is coupled to the input circuit portion via a transmission line and is configured to convert the current signal to an output voltage signal. The output circuit portion comprises at least a first and a second output amplifier device. The signal distribution circuit is configured to form a first cascode of a first pair of input and output amplifier devices during a first time interval of the LO voltage signal and to form a second cascode of a different second pair of input and output amplifier devices during a second time interval of the LO voltage signal.

In Example 18, a control terminal of the output amplifier device of the first cascode is coupled to a constant bias signal.

In Example 19, the signal distribution circuit of Example 17 or 18 is configured for a current flow from the output circuit portion to the input circuit portion during the first time interval and a current flow from the input circuit portion to the output circuit portion during the second time interval.

The aspects and features mentioned and described together with one or more of the previously detailed examples and figures, may as well be combined with one or more of the other examples in order to replace a like feature of the other example or in order to additionally introduce the feature to the other example.

The description and drawings merely illustrate the principles of the disclosure. Furthermore, all examples recited herein are principally intended expressly to be only for pedagogical purposes to aid the reader in understanding the principles of the disclosure and the concepts con- tributed by the inventor(s) to furthering the art. All statements herein reciting principles, aspects, and examples of the disclosure, as well as specific examples thereof, are intended to encompass equivalents thereof.

A functional block denoted as "means for ..." performing a certain function may refer to a circuit that is configured to perform a certain function. Hence, a "means for s.th." may be implemented as a "means configured to or suited for s.th.", such as a device or a circuit configured to or suited for the respective task.

Functions of various elements shown in the figures, including any functional blocks labeled as "means", "means for providing a signal", "means for generating a signal.", etc., may be implemented in the form of dedicated hardware, such as "a signal provider", "a signal processing unit", "a processor", "a controller", etc. as well as hardware capable of executing software in association with appropriate software. When provided by a processor, the functions may be provided by a single dedicated processor, by a single shared processor, or by a plurality of individual processors, some of which or all of which may be shared. However, the term "processor" or "controller" is by far not limited to hardware exclusively capable of executing software, but may include digital signal processor (DSP) hardware, network processor, application specific integrated circuit (ASIC), field programmable gate array (FPGA), read only memory (ROM) for storing software, random access memory (RAM), and nonvolatile storage. Other hardware, conventional and/or custom, may also be included.

A block diagram may, for instance, illustrate a high-level circuit diagram implementing the principles of the disclosure. Similarly, a flow chart, a flow diagram, a state transition diagram, a pseudo code, and the like may represent various processes, operations or steps, which may, for instance, be substantially represented in computer readable medium and so executed by a computer or processor, whether or not such computer or processor is explicitly shown. Methods disclosed in the specification or in the claims may be implemented by a device having means for performing each of the respective acts of these methods.

It is to be understood that the disclosure of multiple acts, processes, operations, steps or functions disclosed in the specification or claims may not be construed as to be within the specific order, unless explicitly or implicitly stated otherwise, for instance for technical reasons. Therefore, the disclosure of multiple acts or functions will not limit these to a particular order unless such acts or functions are not interchangeable for technical reasons. Furthermore, in some examples a single act, function, process, operation or step may include or may be broken into multiple sub-acts, -functions, -processes, -operations or -steps, respectively. Such sub acts may be included and part of the disclosure of this single act unless explicitly excluded. Furthermore, the following claims are hereby incorporated into the detailed description, where each claim may stand on its own as a separate example. While each claim may stand on its own as a separate example, it is to be noted that - although a dependent claim may refer in the claims to a specific combination with one or more other claims - other examples may also include a combination of the dependent claim with the subject matter of each other de- pendent or independent claim. Such combinations are explicitly proposed herein unless it is stated that a specific combination is not intended. Furthermore, it is intended to include also features of a claim to any other independent claim even if this claim is not directly made dependent to the independent claim.