SIGNAL GENERATOR AND METHOD FOR SIGNAL GENERATION FOR RADIO FREQUENCY RECEIVERS

FIELD OF THE INVENTION

The present invention relates to a signal generator for calibration and a method for calibration of image rejection and second order intercept.

BACKGROUND OF THE INVENTION

In receiver circuits, mixers translate a high input radio frequency (RF) to a lower intermediate frequency (IF). This is generally known as down conversion. In the ideal case, the mixer output signal, amplitude and phase are proportional to the input signal's amplitude and phase, and independent of the local oscillator (LO) signal characteristics. However, non-linearities and unmatched path properties e.g. of the I-path and the Q-path produce undesired mixing products, such as spurious responses, which are caused by undesired signals reaching the mixer's RF input port and producing a response at the IF frequency. One of the common parameters for characterization of the quality of a receiver (a mixer used as receiver) is the second order intercept (IP2) point. For specifying the mixer's IP2, it is assumed that only the fundamental RF and LO frequencies are applied to the mixer's port and that the harmonic distortion is created in the mixer alone. High level input signals create distortion or inter modulation products and can be quantified by calculating the intercept point either at the input or output of the device or system. The input intercept point represents a hypothetical input amplitude at which the desired signal components and undesired components are equal in amplitude. Usually such intercepts (IP2 for the second order intercept, IP3 for the third order intercept) are referred to at the IF output or the RF input of a receiver. The order refers to how fast the amplitudes of the distortion products increase with a rise in input level. For example, the second order inter modulation products will increase in amplitude by 2 dB, when the input signal is raised by IdB. Accordingly, radio frequency applications require receivers, which provide a high image rejection and a high second-order intercept (IP2).

A transmitter may be used for generating a calibration signal for the receiver. If the transceiver uses the same frequency for receiving and transmitting, a single-sideband signal at the transmitter may have the frequency fLo + fiF, wherein fiχ _> is the frequency of the local oscillator (LO), and fπ? is the intermediate frequency. In non-ideal implementations, a

certain amount of feed-through from the LO will occur at the frequency fLo- Further, if a Cartesian transmitter architecture is implemented, any unbalance in the LO or IF path will result in an image signal at fiχ _> + fiF- If the desired component is at fLo+fiF than the image is at fLo-fiF- This image signal limits the achievable calibration accuracy of the receiver to the amount generated by the transmitter. Accordingly, an important characteristic of a receiver is the image rejection.

In order to achieve an appropriate performance of the circuits used for the receivers, the implementations are subject to extensive matching requirements. A major disadvantage of matching electronic components on a silicon substrate consists in the large amount of area necessary to cope with process variations.

Another approach to improve the performance of radio frequency receivers consists in calibration. Calibration has been extensively used in receiver and transmitter circuits to handle the ubiquitous manufacturing variations of integrated devices. Several of the receiver calibration principles require the calibration of the transmitter architecture beforehand. However, calibrating the transmitter requires a calibrated receiver.

Other applications, like television receivers, do not provide integrated transmitters. Accordingly, internal calibration is not available, unless a complete transmitter is integrated for the only purpose of calibrating the receiver. Apparently, this approach is very expensive in terms of silicon area and development time of the integrated circuit. The ideal approach of calibrating the receiver consists in measuring the receiver with a good signal generator. Based on measurements on the basis of test signals, which are provided by the signal generator and which are injected in the receiver, the I and Q unbalance with regard to their amplitudes and phases, the IP2 effects, and the image rejection can be determined. In response to the measurement results, small changes in the I or Q path are applied to counteract the measured non-idealities. However, a separate high performance signal generator providing high quality reference signals entails high costs for the equipment.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a calibration circuitry for a receiver being small and simple to implement. It is also an object of the present invention to provide an effective method for calibrating a receiver.

According to a first aspect of the present invention, a method for calibrating a radio frequency receiver is provided, which includes the following steps: providing a first digital clock signal, adapting the first digital clock signal such that a harmonic of the first

digital clock signal is suitable to be used as a calibration signal for the receiver. Further, the method can include the step of supplying the digital clock signal to an input of the radio receiver in order to calibrate the receiver by use of the harmonic. This aspect of the present invention is particularly advantageous, as digital clock signals are omni-present and easy to generate. Digital clock signals are composed of high order harmonics of the basic oscillating frequency of the digital signal. If the signal is assumed to have a predetermined waveform, the harmonics are predictable. The high order harmonics have smaller amplitudes compared to the amplitudes of the digital clock signal. For calibration, the digital signal is adapted such that the first digital clock signal can be applied to specific inputs of the radio frequency receiver without overdriving the input. The input may be an input of the low noise amplifier or any other entry point in the receiver processing chain dependent on the components, which are to be calibrated. The digital clock signal might be filtered in order to suppress undesired frequency components. However, it is also possible to use integrated filters of the receiver processing chain for the filtering. According to another aspect of the invention the method comprises the step of attenuating the first periodic digital clock signal in order to avoid overloading the input of the receiver, i.e. input components of the receiver. According to this aspect of the invention the whole digital input signal is attenuated in order to prevent that for example the LNA or other components are overdriven by the input signals. The digital signal, so attenuated, can be used without previous filtering and the entire digital calibration signal can be applied to the respective injection point of the receiver.

According to another aspect of the invention, the method includes the step of combining the first periodic digital clock signal with a delayed version of the first periodic digital clock signal, thereby generating a periodic pulse signal to be used as calibration signal. A signal having a short pulses, according to this aspect of the present invention might be more suitable for extracting harmonics, as for example a rectangular digital clock signal. Accordingly, a harmonic of an increased quality can be extracted from the short pulse signal than from signals having other waveforms. The pulse signal can be generated by some digital circuitry, as logic gates and inverters. According to a further aspect of the present invention, the harmonic to be used for calibration is a harmonic of an order greater than 20. This aspect of the invention takes account of the beneficial concept to use a basic digital clock signal of a rather low frequency compared to the radio frequency of the receiver. A GSM (Global System for Mobile Communication) system at 1 GHz, and a first periodic digital clock of 13 MHz results in

harmonic 77 to be used. For GSM-systems using 26 MHz, harmonic 38 is suitable. If, for example, the basic clock signal has a frequency of 25 MHz, the 80 ^th harmonic of the clock signal is in the range of 2 GHz. The harmonics having a respective high order provide still sufficiently large amplitudes for calibration. According to another aspect of the present invention the method comprises the step of using the rising slopes and falling slopes of the periodic pulse signals. Accordingly, the repetition rate of the test signal, i.e. the digital clock signal is increased. The ratio of the peak- value of the digital clock signal versus the rms-value (root mean square) of the desired harmonic can be decreased by increasing the repetition rate. Therefore, this aspect of the invention might be useful for some applications. However, there is a trade-off between increasing repetition rates and the number of possible frequencies for calibration. A lower repetition rate provides more harmonics per given frequency range.

According to an aspect of the present invention the method comprises the step of calibrating the amplitude and calibrating the phase of the receiver, wherein calibrating the amplitude is carried out before calibrating the phase. This is particularly advantageous for example for quadrature down conversion. The amplitude and the phase error are the two possible errors which can be corrected in a receiver having a typical quadrature down converter. If the amplitude is corrected in a first step, the amplitude error can not affect the phase error during the second calibration step. Therefore, the above method steps, in the defined order, are useful for achieving high image rejection levels of 50 - 60 dB. If the phase is corrected first, the amplitude error influences the result and the over-all calibration result is inferior.

According to still another aspect of the invention, the method includes the step of calibrating the delay between two paths of the receiver by determining the amplitude error and the phase error for different oscillating frequency values of the local oscillator. A delay will result in a frequency dependent phase-error. According to this aspect of the invention, the phase error for at least two different frequency values e.g. lOOkHz, and 200 kHz (and maybe 500 kHz, 1 MHz although two measurements should suffice) is measured. Based on this measurement, it is possible to estimate the delay through the relation delay = phase/frequency (in radians).

The object of the present invention is also solved by an electronic device including digital circuitry for generating a first periodic digital clock signal, wherein the first periodic digital clock signal is adapted to be applied to an entry point of a receiver, such that the receiver can be calibrated by use of a harmonic of the first periodic digital clock signal.

The calibration signal can be considered to be the entire digital signal including the harmonic. It is also possible to filter the digital signal in order to suppress some of the undesired signal components. The calibration signal can be injected at any possible input point at the receiver to be calibrated. According to another aspect of the invention, the calibration signal is coupled to an input of a low noise amplifier of the receiver. According to still another aspect of the invention, the electronic device includes a integrated receiver, wherein the digital circuitry for generating the digital periodic clock signal, is integrated together with the receiver. According to this aspect, there is a complete integrated solution including a receiver and the corresponding circuitry for calibration. As the circuitry for calibration is based on small digital circuitry this concepts supports easy manufacturing and a high quality of receivers. External calibration procedures are not needed anymore. In particular, as the receiver is enabled to carry out self-calibration by integrating the calibration circuits in the same device, the whole concept may be used in a beneficial manner for calibrating transmitters by use of calibrated receiver. Further, the concept can also be applied for transceivers.

According to another aspect of the invention, the electronic device includes further digital circuitry for generating a second periodic digital clock signal, the second periodic digital clock signal being coupled with the first digital clock signal for generating a pulse signal. The merits of this configuration are already explained above with respect to the corresponding method steps. Further, the digital circuitry for providing the clock signal can be implemented based on a phase locked loop or a delay locked loop.

The method and circuitry is preferably used to for calibrating the image rejection, the second order intercept, the cut-off frequency of any filtering in the receiver, be it high-pass, low-pass or band-pass filtering.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other aspects of the invention will be apparent from and elucidated with reference to the embodiment(s) described hereinafter. In the following drawings

Fig. 1 shows a simplified schematic of a circuitry to be used as a part of the test signal generator according to a first embodiment of the present invention, Fig. 2 shows a waveform diagram for the circuitry of Fig. 1, Fig. 3 shows the frequency domain signals of the upper waveform (pulse) shown in Fig. 2,

Fig. 4 shows a simplified block diagram of a receiver and possible input points for a calibration signal according to an aspect of the present invention,

Fig. 5 shows a simplified diagram illustrating a receiver architecture with a phase shift for Cartesian signals, Fig. 6 shows a simplified diagram illustrating the correction of amplitude and phase error for quadrature down-conversion according to an aspect of the invention, and

Fig. 7 shows a simplified block diagram relating to a time delay in one path.

DETAILED DESCRIPTION OF EMBODIMENTS Fig. 1 shows a simplified schematic of a possible implementation of a test signal generator according to an aspect of the present invention. Accordingly, the test signal generator includes three invertors INVl to INV3 and a single AND gate. The input signal may be a digital 25 MHz clock signal, which is delayed and inverted by the inverters INVl to INV3. The input signal is also applied to the AND gate by a direct path without further delay or inversion. The AND gate receives a delayed and a non-delayed version of the input clock signal IN. In response to the two input signals, the AND gate produces an output signal OUT in form of a small pulse with a peak-to-peak value of approximately the supply voltage (e.g. 1 Vpp). The repetition rate of the pulse signal corresponds to the period of the input clock signal IN. The frequency of the input signal might be assumed to be 25 MHz. In this case, the repetition rate of the output signal OUT amounts also to 25 MHz.

Fig. 2 shows the waveforms of the input and output signals of the configuration shown in Fig. 1 in a simplified manner. The digital signal S3 after propagating through the inverters INVl to INV3 of Fig. 1 is delayed and inverted with respect to the input signal S2 propagating through the direct path to the AND gate. At the output OUT of the AND gate, a short pulse Sl appears, which has a width being equivalent to the delay of the three inverters INVl to INV3. Fig. 2 serves only to illustrate the principle. The time scale and the proportions of the pulse width versus the period of the signals as indicate in Fig. 2 may deviate considerably from realistic proportions.

Fig. 3 shows the spectrum in the frequency domain of the pulse signal OUT of Fig. 1 and Fig.2. This gives a rough estimate of the signal power of each of the harmonics. Around 2 GHz, the harmonics have a peak value of -42 dBVp or an rms- value of -45 dBVrms or 5.6 mVrms. These considerations are particularly important for the applicability of the present invention. The appropriate input locations for the calibration signals relate to the amplitudes and power levels of the calibration signals. If a signal is to be input at certain

point of the receiver, care has to be taken not to overload the input. This aspect of the invention will be illustrated with respect to Fig. 4.

Fig. 4 shows a simplified diagram for a receiver including an antenna AN, a low noise amplifier LNA, and a front end filter FEF. As an example, there are two possible input points El, E2 indicated in Fig. 4, where a calibration signal could be applied. In order to input the calibration signal at entry point El, it might be necessary to couple the test signal off-chip to the receiver dependent on the implementation of the receiver. This might be undesirable, as additional pins, additional coupling and more possible noise sources occur. Therefore, according to an aspect of the present invention, it is preferred to couple the calibrating signal to entry point E2, i.e. internally on the chip. However, the entire calibration signal will be amplified by the LNA as the signal is entered only after the FEF. For a digital clock signal, which is used as the source for the harmonics, the amplitude levels will be in the range of the supply voltage of the circuitry. Applying such high voltage levels to the LNA will let the LNA overload. For example, if the voltage levels of the digital clock signal used to provide the harmonics (e.g. the amplitudes of the periodic short pulse signal produced by the circuitry shown in Fig. 1) amount to 1 Vpp, the signal will overdrive the complete front-end (e.g. the LNA) in the receiver. If an 1 dB compression level of -30 dBm (or 7 mVrms into 50 Ohm) is assumed, the calibration signal, i.e. the periodic short pulse signal produced by the circuit in Fig. 1 has to be attenuated by factor of 143 or 43 dB. The harmonics of the pulse signal at 2 GHz have a level, which is 45 dBVrms lower than the peak value of 1 Vpp. This is shown in Fig.2. Accordingly, the amplitudes of the approx. 80 ^th harmonic at 2 GHz amount to -45 dBVrms - 43 dBVrms = -88 dBVrms. This value corresponds to -75 dBm on 50 Ohm. A signal, which is attenuated as described above is still applicable for DCS 1800 applications. For the DCS 1800 system, the noise level of the receiver is specified to be around -116 dBm for a 200 kHz bandwidth. If the noise floor of -116 dBm is set in relation to the calibration signal level of -75 dBm, the test signal, i.e. the harmonic used for calibration, provides an SNR of 41 dB. If this SNR is not sufficient, integration over a certain time interval can improve the SNR up to any required value. The same considerations as set out here above in accordance with some aspects of the present invention are similarly applicable to other standards or applications as for example GSM or the like.

The front end filter may provide a filter characteristic for GSM applications in the range of 925 to 960 MHz. According to the GSM standard, a maximum transmission power level of -57 dBm during reception for the purpose of accurate reception is allowed.

The same level is relevant for calibration. The test signal is an in-band signal, which will be directly radiated, if it is coupled to the antenna. A test signal of -75 dBm provides a sufficient margin with respect to this requirement. This is due to regulatory requirements.

Although, the present embodiment of the invention is explained with respect to the two possible injection points El, and E2 for the calibration signal, it is generally possible to inject the test signal at any point in the receiver chain as long the effects, which should be considered for calibration, occur only after the injection point.

Fig. 5 shows a simplified diagram illustrating a receiver architecture for Cartesian radio signals, wherein a phase shift in the A-branch is present In the receiver architecture shown in Fig. 5, only the frequency band of interest is received. RF- or IF-fϊlter limit the frequency range of the input radio signals and attenuate the non-relevant frequency components. If a receiver should be calibrated at a frequency of 2 GHz, which is the 80 ^th harmonic of the 25 MHz test signal, the respective 80 ^th harmonic of the input signal is to be extracted from the digital clock signal. If the intermediate frequency is 200 kHz, the local oscillator is adjusted to 2000.2 MHz. This requires a fractional -n synthesizer. The 2 GHz signals will be mixed down to 200 KHz in the I- and Q-path. A corresponding error in phase and amplitude is present in the I- and Q-path, which can be detected by the digital part of the receiver. Further, the detected errors may be corrected in the analog or digital part of the receiver as described below. If a 25 MHz repetition rate test signal is used, a calibration at every 25 MHz can be performed over the whole frequency range of the receiver.

An important aspect of the present invention is the large amplitude of the test signal and the relatively low amplitude of the harmonics. The large amplitude of the test signal can overload the receiver front end. The ratio of the peak value of the signal versus the root means square (rms) value of the desired frequency component can be reduced by generating pulses with a higher repetition rate. However, this higher repetition rate entails a reduced number of possible frequencies, which are available for calibration. Calibration at multiple intermediate frequencies may be performed by changing the LO frequency. An option to increase the repetition rate of the test signal consists in using both, the up-going and the down-going slopes of the 25 MHz clock signal. Accordingly, the circuit shown in Fig. 1 may be replicated and be used for the inverted signal of the signal used for the circuit of Fig. 1. The outputs of the two end gates can be combined in a third end gate in order to create a pulse repetition rate of 50 MHz. This approach relies basically on digital gates, which allows easy transfer from one technology to another. The test signal generated as described above can be used for calibrating the image rejection, the second order intercept, and the cut off

frequency of any filtering implemented in the receiver. The filter might be a high pass, low pass, or a band pass filter.

Although the circuit shown in Fig. 1 uses a couple of inverters for the delay of the input clock signal, it is also possible to use resistors, inductors, capacitors, or any other kind of slew rate limited inverters in order to realize the delay. Further, there are numerous techniques to increase the repetition rate of the test signal as for example by use of a delay locked loop (DLL) or a phase locked loop (PLL). DLLs and PLLs can be used to generate higher harmonics.

Another possibility to create a higher repetition rate is to use a long inverter- like delay line and combining multiple slopes of multiple inverter outputs. Due to unbalances in the delays, the amplitude distribution of the harmonics may not be equal, which can be solved by implementing a programmable attenuator, through which the test signal is coupled into the receiver.

Although the above description relates mainly to receiver applications, transmitter applications can also benefit from the invention. If the receiver has been calibrated properly according to the above aspects of the invention, an un-calibrated transmitter signal can be connected to the receiver. The received signal can be examined for any mis-alignment in order to calibrate the transmitter in response to any detected deficiencies. As the receiver is tuned to the respective harmonic of the test signal, the filtering in the analog or digital part of the receiver can be used to attenuate any undesired harmonic of the test signal. Accordingly, unwanted frequency components of the test signal are suppressed in order to prevent them from interfering in the calibration procedure.

Fig. 6 shows a simplified diagram illustrating the correction of amplitude and phase error for quadrature down-conversion. The amplitude and phase errors can be assumed to correspond to the errors shown in Fig. 5. In the quadrature down-conversion for a sinusoidal input test signal as shown in Fig.5, A cos (cθLt + cost + φ), where φ is regarded as unknown. Two possible errors are considered within the quadrature down-conversion unit. These are the phase error, which is represented by ε, and an amplitude error, which is represented by α. These are the only possible errors that the system outlined above can detect on the basis of the two sinusoidal signals at the output. The outputs are the signals at the right-hand side of the Figure: Asin(...) for the I-path and Acos(...) for the Q-path. The image produced by this down-conversion unit is best for the smallest phase and amplitude error. The phase and the amplitude error are measured as follows. In order to evaluate the amplitude error, the power in each of the I- and Q- paths is determined and the difference is

calculated. This is carried out by squaring and integrating each signal over a suitable period of time. This can be done without any pre-knowledge of the phase error. In a second step, the phase difference between the two signals is determined. In particular, it is to be determined, how close the two signals are to ideal quadrature. This is usually done by multiplying the I- and Q-signals with each other. This results in the following expression:

αA sin (cost + θ) . A cos (cost - ε + θ) αA ² sin (cost + θ)cos (cost - ε + θ)

= (<xA72) sin ε

If the above product is averaged for a suitable period of time, ε can be determined, since α and A are known from the previous amplitude measurements. According to this aspect of the invention, the amplitude error is determined before the phase error. Accordingly, the amplitude values to be used in the above equation can already be corrected, which reduces the error in the calculated value of ε. This is particularly beneficial for image rejection values of about 50 to 60 dB. If the phase error and the amplitude error are determined, the receiver can be calibrated in order to compensate the measured deficiencies. The adjustment of the circuit is based on the trigonometric identity:

A cos (cost - ε + θ) = A cos (cost + θ) cos ε + A sin (cost + θ) sin ε

According to this aspect of the present invention, the amplitude correction is performed before the phase correction in order to achieve high values of image rejection. Fig. 7 shows a simplified block diagram relating to a time delay in one path. Adding a small amount of the I-path signal to the Q-path signal causes a correction in phase, which is independent of the test frequency COs. Accordingly, it can be assumed that the phase error is independent of the frequency. If no additional measurements were taken at other frequencies, this is rough approximation of the real situation. However, according to another aspect of the invention, it is suggested to improve the performance of the known simple algorithms by measuring at other frequencies. This can be achieved by varying the synthesizer local oscillator frequency LO. If the LO frequency is changed for a small amount, this results in a change of the frequency of the received signal. By measuring the phase error as function of the frequency of the this received signal (or calibration signal) the delay in the I-path or the Q-path can be estimated. One possibility consists in compensating the delay

only during the IF processing as shown in Fig. 7. By measuring a phase error at two or more different samples of COs, an estimate of T can be obtained. In this case, the error is easily cancelled by implementing a specific delay in the respective other path. If the signals propagating in this part of the system are over-sampled, delay compensation can be improved.

The invention described above is useful and beneficial for a wide variety of wireless and wired standards as GSM, CDMA, Edge, WLAN, and BTI-EDR. All systems, which require a high image rejection or a high second-order intermodulation distortion intercept point will profit from one or more aspects of the present invention. While the invention has been illustrated and described in detail in the drawings and foregoing description, such illustration and description are to be considered illustrative or exemplary and not restrictive; the invention is not limited to the disclosed embodiments.

Other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A plurality of clock generation circuits or other units may fulfill the functions of one of the items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measured cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope.