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Title:
SIGNAL PROCESSING APPARATUS AND METHOD, AND ELECTRONIC DEVICE COMPRISING THE APPARATUS
Document Type and Number:
WIPO Patent Application WO/2018/002717
Kind Code:
A1
Abstract:
According to the embodiments in the present invention, there is provided a signal processing method and a signal processing apparatus for measuring latency between signals, and performing latency compensation for a to-be-compensated signal according to a measured latency. By measuring the latency between signals using multiple clock signals of the same frequency but different phases, not only the accuracy of the obtained latency measurement result is made higher, but also design and implementation of a latency-measuring circuit is made less difficult, such that a better system performance can be obtained more easily.

Inventors:
HUANG, Huaming (388# Ningqiao Road, PuDong JinqiaoShanghai, 6, 201206, CN)
DENG, Zongming (388# Ningqiao Road, PuDong JinqiaoShanghai, 6, 201206, CN)
Application Number:
IB2017/000949
Publication Date:
January 04, 2018
Filing Date:
June 19, 2017
Export Citation:
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Assignee:
ALCATEL LUCENT (148/152 Route de la Reine, Boulogne-Billancourt, 92100, FR)
International Classes:
G04F10/00
Foreign References:
US20090296532A12009-12-03
Other References:
QI ZHONG, MENG XIANGTING, LI DEYUAN, YANG LEI, YAO ZEEN, LI DONGCANG: "A high precision TDC based on a multi-phase clock", 4 February 2015 (2015-02-04), Cornell University Library, XP002775219, Retrieved from the Internet [retrieved on 20171031]
ZHOUJIANCHENG YIN ET AL: "A high-resolution time-to-digital converter based on multi-phase clock implement in field-programmable-gate-array", REAL TIME CONFERENCE (RT), 2012 18TH IEEE-NPSS, IEEE, 9 June 2012 (2012-06-09), pages 1 - 4, XP032314370, ISBN: 978-1-4673-1082-6, DOI: 10.1109/RTC.2012.6418217
Attorney, Agent or Firm:
BERTHIER, Karine (Alcatel-Lucent International, Patent BusinessSite Nokia Paris Sacla, route de Villejust Nozay, 92100, FR)
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Claims:
Claims

1. A signal processing method, comprising:

measuring- a latency between & first signal and a second signal using multi le .dock signals of the .same frequency but different phases., to obtain a first set of measurement values;

- determining a second set of measurement values from the first set of .measurement values and phase differences between the multiple clock signals and ¾ zero-p ase-dlfference clock signal;

- selecting a smaller measurement value from the second set of measurement values as the 'latency between the irst signal and the second signal.

2. The method according- to' claim 1,. wherein the first signal is synchronised with the zero»phase--dlfterenee dock signal

3, The method accord ing ia claim 1 or 2, wherein the step of obtaining a first set of measurement values com rises:

- providing multiple counters, each being applied with a respective clock signal the multi le ciock signals, where h each of the counters Is configured to start counting upon arrival -of the first signal, and to: stop counting u on arrival of the second Signal, a d count value of each of the multiple counters Is used as a measurement value in . the first set ofmeasurement values.

4, The method according to. claim i or 2. wherein the step of obtaining 3 first set of measurement vaiues comprises:

- count: r¾g the first signal arid the second signal according to each clock signal in the multiple clock signals;

- calculating, for the. each clock signal, a difference between: count values of the first signal and the second signal as a measurement value in the first set of measurement values, respectively.

5 The method according to cla m 1, wherein the step of determining a second set of measurement values; comprises:

- for each measurement value I the first set of measurement vaiues, addin a phase difference between a ciock signal corresponding to the measurement value in the multiple clock signals and the zero-phase-differenca clock signal to the measurement value, to obtain a .measurement value in the second set of measurement values.,

6. The method according to claim 1, wherein the step of selecting a smaller measurement value from the second set of measur ment values as the latency between the first signal and the second signal comprises:

- selecting a minimum measurement value from the second set. of measurement values as the latency between the first signal and the second signal.

7. The method according to claim X, further comprising:

- compensating a signal according to the determined. latency,, to obtain a compensated signal; the s e comprising;

- compensating: the signal with integer dock periods included 'in said latency, to obtain an integer- ioek-periods compensated, signal;

compensating the integer -dock-periods compensated -signal with a non-integer dock period included in said latency, to obtain the compensated signal, wherein the com ensation with the η-mteger clock period uses a dock signal, in the multiple clock signals, which has a non-integer clock period phase difference with the dock signal used for compensating the signal

8, A signal processing apparatus, comprising:

a first unit configured to measure latency between a first signal and -a second signal using multiple clock signals of the same frequency taut different phases, to obtain a first set of .measurement values;

a second u it configured to. determine a second set of measurement values f rom the first se of measurement values and phase differences between the multiple clock signals and a iero-phase-difference clock signal;

a third unit configured to select a smaller measurement value from the second set of measurement values as the latency between the first signal and the second signal.

9, The signal processing apparatus according o claim 8, Wherein the first signal & '-synchronized with the Zero phase difference clock signal.:

10. The signal processing apparatus according to cisiro 8 or ¾ wherein the first unit comprises: multiple counters, each being applied with a respective clock signal in the multiple clock signals, wherein each of the multiple counters is configured to start counting upon arrival of the first signal, and to stop counting upon arrival of the second signal,

the first unit is configured to.' use a count value of each of the counters as a measurement value in the first set of measurement values.

11. The si s! processing apparatus according to claim 8 or 9, wherein the first unit is configured to count the first signal and the second signal according to each clock signal in the multiple clock signals, respectively; and calculate, for the each ciock signal, a difference between count values of the first signal and the -second signal as a measurement value in the first' set of measurement values, respectively.

12, The signal processing apparatus according to claim 8, wherein the second unit is configured to:

for each measurement valu in the first set of measurement values, add a phase difference between a clock signal corresponding to the measurement value in the multiple clock signals and the iero-phase-difference clock signal to the measurement value, to obtain a measurement valu in the second set of measurement values.

13. The signal processing apparatus according to claim 8, wherein the third unit is configured to select a minimum measurement value from the second set of measurement values as the latency 'between the first signal and the second signal.

14. The signal processing apparatus according io claim 8, further comprising:

a fourth unit configured to perform latency compensatio to a signal according to the determined latency, to obtain a compensated signal;

the compensation operation of the fourth unit comprising;

- Compensating' the signal with integer clock periods included in said latency, to obtain an mteger-eiotfc-persods ompe sate . signal;

- compensating the integer-dock -psr ds compensated signal w th a non- integer clock period included: in said latency, to obtain the compensated signal, wherein the compensation with the non^rsteger clock period uses a dock signal, in the multiple clock signal, which has a non-integer clock period phase difference with the dock signal used for compensating the signal.

15. An electronic device, comprising a signal processing apparatus according to any one of claims 8 So 14.

Description:

apparatus.

[21 I n . circuits Of many electroni devices, it is needed to measure signal latency within a . single board or between boards, and within a ch p or between ' Chi s, and to perform signal processing according to the measured latency between signals, e.g., .performing- latency compensation to a signal.

|3] Gene ally; a digital logic : circuit may be. used to test latency between signals. Typically the frequency of a clock usee! by the logical circuit decides .a measurement accuracy of the signal latency, far example, if the logic circuit uses s 125MHz clock for measuring" latency,, the clock period will be 8 nanoseconds (R.S), and the measured accuracy of the latency between signals is also Sns. In other words, the final latency measurement result can only be an integer multiple of 8ns. For example,, suppose an actual latency between signals is 65ns, while the measurement result Is 72ns {9 times of 8ns), it cause a measu ing error.

[4] Using a dock with a higher frequency helps to Improve the accuracy of latency measurement,: However, it may lead to tight time sequence of the logic circuit, and power Consumption of the circuit may also be. higher. Therefore, ft is an issue worthy of being studied as to how to perform 8 high-precision real-time measurement on the latenc between signals using s ciock signal with a lower frequency.

5} In addition, a value of the latency between signals may also vary with conditions such as an ambient temperature. is is also demanding on real-time performance of latency measurement.

[61 According to the embodiments of the present invention., it is desired to. provide a method and apparatus for measuring latency between signals,, arid more optionally, to perform latency .compensation for a to-be-compensated signs! according to a measured latency.

17} According to an embodiment in one aspect of the present invention, there is provided a sigrsai. rocessing method, comprising;

[SI - measuring « latency between, a first signal and a second signal using multiple clock signals of the same frequency but different phases,, to obtain a first set of measurement values;

[9] - determining a second set of measurement values from the first set of measurement values and phase differences between corresponding clock signals a d a zero-phase-difference clock signal;

(IPS - selecting a smaller measurement vaiue from the second set of measurement values ' to be determined as. the latency between the first signal and the second signal.

ill] According to an embodiment in another aspect of the present invention, there is provided a signal processing apparatus; comprising:

$2) a first. -unit configured to measure a late c be ween a first signal and a-secosd signal using multiple .dock ssgnaSs of the same frequency but different, phases, to obtain a first set of measurement values;

[13J 3 second unit configured to determine a second set of measurement values■ from the first: set of measurement values and phase .differences between corresponding clock signals and a zero- hase-difference dock signal;

114] a third unit eon-figured to select a smaller measurement value from the second set of measurement values to be determined as the latency between the firs -signal and the seco d signal.

[IS] According, to an embodiment in a further aspect of the present invention, there is provided electronic device, comprising a signal processing apparatus as .mentioned above.

{iSj Compared with the prior art, the method and- appa atus according to the embodiments of the present invention have the following advantages:, by measuring 3 latency between signals using multiple clock signals of the same frequency but different phases, not only the accuracy of the obtained latency measurement -result is made higher, hut also design and implementatio of- a latency-measuring circuit is made less difficult, such that a: better system performance can be obtained more easily. Meanwhile, the- measurement result of signal latency can also embody real-time change o an actual latenc .

117} The present, invention will be understood more thoroughly through the ;< taifed depiction and accompanying drawings provided belov¾. : wherein the same elements -are represented by the same reference signals, wherein:

[18] Fig. I illustrates a flow diagram of -a .method for signal processing according to- an e mbodiment in one aspect of the present invention;

191 F gs, 2a . and 2b illustrate schematic diagrams of multiple dock signals of the same frequency but different phases according to an embodiment of the present invention;

[20] Fig. 3 illustrate a schematic diagra of a ¾er j--phase-d;fferenee dock .signal according to an embodiment of the present invention;

[211 fig: 4 illustrates 3 schematic signal diagram of performing latency compensation for a to-be-compensated signal according to an embodiment of the presen invention;

{22] Fig. 5 illustrates a schematic diagram of a time sequence relationship among signals according to an embodiment of the present invention;

[23] Fig. 8 illustrates a structural. schematic diagram of a signal processing apparatus according to an embodiment in another aspect of the present invention.

[24] It should be mentioned that these drawings are intended to illustrate general characteristics of a method., a structure and/or material in .some exemplary embodiments, anil make supplementations to a written ■■ depiction provided hereinafter. However,: these drawings are not drawn by proportion and might not accurately reflect an accurate structure o performance Characteristic of any given embodiment, and should not be construed as defining or limiting the scope of numerical values or attributes covered by the exemplary embodiments. p.5] Although the exemplar embodiments may have, various modifications and alternative manners, some embodiments thereof are illustrated in the drawings as examples, which will be detailed here. However, it should be understood that it Is. not . intended to limit the exemplary emb diments to t e dssdo ' sed specific forms. On the contrary, the exemplary embodiments intend to cover all modifications, equivalent solutions, and alternative- solutions within the scope of the claims. Sams reference numerals always represent same uni s in the depiction, of various d awings.

[261 Before discussing the exemplary embodiments if) more detail,, It should he mentioned that some exemplary ^e bodim nts are described as a processing or .method depicted in the flow diagrams. Although the flow diagrams describe various operations as being sequentially processed,- many operations therei -may be implemented in parallel,- concurrently or simultaneously. Besides, - the ' sequence of various operations may be re-arranged. When the operations are completed, the- -processing may be terminated. However, the processing ma also include additional steps that are not provided Irs the drawings. The processing may correspond to ' 8 ' method, a function, a .specification, a s-ub-routine, a sub-program, etc.

(271 The term "wireless device* or "device" used, here may e regarded as syhobymdos- to the following-, items and sometimes may be infe ed to- as the following items hereinafter: .client user ' device, mobile station, mobile user, , mobile terminal subscriber, user, remote station, access terminal, eceiver, md mobile unit,, etc., esnd may describe a remote user of a wireless resource in a wireless communication network.

2S] Methods discussed later {wherein- some are illustrated through flow, diagrams! may be implemented through hardware, software, firmware, middleware, microcode, hardware depiction language or any -combination thereof. When they are implemented by software, firmware,- ' middleware, or microcode, program code or code segments for implementing; essential tasks may be stored in a- machine -or compuier-readaMe : medi«im |e.g., a storage medium). {One ' or more): processors may implement essential tasks,

[29] The specific structures and functio -details as disclosed here are only representative and used for the purpose of describing the exemplary embodiments of the present invention. However, the present invention may be specifically, implemented through many alternative manners and should riot he construed as being only limited to -the. embodiments he re.

|30| It should, he understood that although terms like "first" and "second" are used here to describe various units, these units should not be, limited by these terms. Use of -these terms is only for distinguishing one uni from another unit. For example, without departing from the scope of these exemplary embodiments, -a first unit may be referred to as a second unit, and similarly, the second unit may be referred to as the firs unit. Th term "and/or" used here includes any of one or more associated -Items as listed and ali combinations, thereof.

[311 The terms used here are only for describing preferred embodiments.- without intending to limit the exemplary embodiments. Unless otherwise indicated in the . context, singular forms "one" and V used here are also intended to- include plurality, it should also- be understood that the terms "comprise' ' ' and/or "include" used here specify existence -.of the stated features, integers, steps, operations, units and/or components, not excluding existence of one: or more other features, integers. Steps, operations, units, components and/or combinations thereof.

1323 It should also be noted that in some alternative implementation ' s, the mentioned functions/ actions may -occur in a sequenc different from what is indicated in the drawings. For example, dependent on the Involved functions/ actions, two successively illustrated drawings actually may be executed substantially simultaneously or executed In a reverse order sometimes. |33] Unless otherwise defined/all terms {including technical .and scientific terms! used here have the -same meanings as ' genera ly .understood by those skiiied ·ίπ the ar to which the exemplary em edments relate.- it .should also be understood that unless explicitly defined: here, those terms defined in common dictionaries should be construed to having meanings consistent with those in the context of a related art, and should not be construed according to ideal .or too formal meanings.

[34] in the depiction hereinafter, illustrative embodiments may e: described with reference to symbol representations {e.g., in the form o flow diagram ' s) of actions and operations that: ay be implemented as program rnodyies or function processing. The program modules or function processing include- routines, programs, objects) components, and data. -structures and the like which implement specific tasks or implement: specific abstract data types, and may be implemented using existing hardware at existing network elements. Such, easting hardware may include one or more central processing units (CPUs), digital signal processors (DSPs), specific integrated circuits, field programmable gate array fFPSA) com uters, etc.

{35) it should also- ' he opted , that software-implemented aspects of the exemplary embodiments are gene all encoded on a .program storage medium of a certain form or implemented through a certain type -of traosmissro mediums. The program storage medium may he a magnetic (e.g.,. a- floppy disk or hard-disk driver) or optical {e.g., CD ROM) storage medium, and may be a read-only or random access storage medium. Similarly, the transmission medium may he a twisted air, co-axial cable, optical -"fiber or certain other appropriate transmission medium well known in the art. The exemplary embodiments are not limited by these aspects in any given implementation, manner.

pSj Hereinafter, embodiments of the present invention, will be described in further detail With reference to the accompanying drawings.

[37} Fig, i illustrates a flow diagram o -a method for signal processing according to an embodiment in one aspect of the present invention.

[3S] Wherein, the method of the present embodiment is mainly implemented through sn electronic device. The electronic device includes, but not limited to, a communication device, a terminal device, a- network device, a medical device,, or a measurement instrument, among other electronic devices. The communication device ' includes, but not limited to, a router, a switch, . ' a- base .station, a core network, 3 wireless local area network controller or etc. The terminal device includes, but not limited to, a smart mobile p ' ho e, -a..tablet computer, a PDA, a PC or etc; The network device includes, but not limited to, a single network server, a server group comprised of multiple network servers, or a cloud computing-based cloud comprised of a considerable number of computers or network servers. Sn the present embodiment, the method for signal processing may process to a digital signal, or an analog signal. If a tp-be-processed signal is aft -analog ' signal, it is preferred to be first subject to. art analog-digital conversion, and -the obtained digital signal, it is subjected to the steps as illustrated in Fig, 1.

[33] The met od accordi g to the present embodiment comprises step SI, step S2, and step S3.

[40] in step SI, an electronic- device measures a latency between a first signaJ ' -and a second signal using multiple clock signals of the same frequency but different phases, to obtain a first set of measurement values.

[41] Before further Introducing , step SI, in order to facilitate understanding,, multiple clock signals involved therein and the concept of iatency between the first signal and the second signal -will be ' Illustrated.

[42! ίΓΐ the preset embodiment, multi le dock signals ar used. The muftipJe clock ssgoafe have the sam frequency, but different phases. The; number of dock,sgnalS: might not' be restricted. Phase differences among dock signals may be equal, i.e., the phase di ferences .between each dock signal and a preceding dock f g i is equal. hen performing latency measurement between signals according to the method of -the press tit inventi on, an accuracy of the measurement result can he determined relatively easily using such multiple dock .signals, for •example, .sup ose there are 10 dock signals each dock frequency is 100 MHz; the phase difference between the each clock s g al n the 10 clock signals and the preceding clock signal is Ins; in this way, an. error of the measurement result may be Ins. The phase differences among dock signals may also be unequal. Far s-xarag!e, suppose there are 8 clock signals with a fre ue cy of lOOWHz; the phase difference between the dock signal i and the clock signal 2 is 3ns; the phase difference between each dock signal in the seven ign l:; from clock signal 2 to dock signal S and the preceding clock signal is Ins. figs. 2a and 2b Illustrate schematic diagrams of multiple dock signal of the same frequency bat different phases according to an embodiment of the present invention. Pig, 2a shows 4 clock signals with a frequency of 125MH¾ I.e., the clock period is Sns; the phase difference between eafch dock signal in the 4 dock signals and a preceding dock signal, is 2ns. Fig. 2b shows 5 clock signals with a frequency of 125 H-?, L-e,, the dock period is 8ns; the phase difference .between- the dock signal ciklb and the clock signs! cik2b2 is 3n¾ the phase, difference between the dock signs! c!k2b2 and the dock signal dk2b3 is 2ns; the: phase difference between the dock signal clk2b3 and the clock signal cMM is Ins; the phase difference between the clock, signal cik2b4 and- the dock signal c!k2bS is Ins; the phase difference between the clock signal c¾2b5 and the dock slgrsal dk2bl Is ins.

[43] The first signal is a signal without latency, While the second signal is a signal with a latency after the first signal is transmitted via ¾ circuit. The first signal and the second signal -are not limited to the digital signals, which may also he analog . .signals. The latency between the first signs! and the second signal may also he represented through. other manners, e.g ^ , a pulse of a digital Signal may be used to Indicate a beginning or end time point of the latency; or a digital level signal may be- .Used to Indicate a beginning or end time point; or a certain fixed hlgh-tew level variation manner m¾y be used to indicate a beginning or end time point. In addition, a to-be-measured latency between the first signal arid the second signal may also be alternatively represented by one signal, e.g,, a rising edge of the signal indicates a beginning time point of the latency, while -a falling edge of the signal Indicates an end point of the latency.. Multiple signals may also be used to indicate a -beginning ' or end time point, e.g., when a stater of the multiple signals is a certain codeword, it indicates a beginning or end time point; or when a state change of the multipie signals, is a certain fixed sequence, it indicates -a beginning or end time point.

[44] For step SI, specifically, the latency between the first signal -and the second signal Is measured by using multiple clock signals of the same frequency- but different phases, respectively; i.e., measuring, the latency using each dock signal of the multiple clock signals., respectively, and an obtained latency measurement result being a measuremen value in the first set of measurement values. The method of latency measurement using a single dock may foe any method of measurin the latency between signals using a single clock. In one preferred embodiment, the step SI provides multiple counters, each being applied with a respective clock signal in the multiple dock signals, wherein each of the counters- is configured to start counting. upon arrival of the first signal, and to stop counting upon arrival . of the second signal and a count value of each of the multiple counters is used, as .a measurement value in t e first set of measurement values:. Specifically, 3 group of counters are used to count. The .number of counters is: identical: to thai of the multiple .dock signals; a dock of each coun er refers to a dock: signal in the multipl deck signals, and the dock signals are ' dif eren from each other. Because the clock, signals of the counters are different from each other, the clock signals ' have the same f equency ut -different phases, and the time sequence relationships of the clock signal with the first signal and the second signs! are also different, the count value of eac counter is also different, hi another preferred embodiment,, the first 'Signal and the second signal are counted, .according to each dock signal in the multiple dock signsis; for the each clock signal, a difference between the first signal count and the second signal count is calculated, as a measurement value in the first set of measurement values, in this, embodiment, with each dock signal in the multiple clock signal of the same frequency but different phases, on measurement value Is o tained through the following manner: the docks of two counters are the same clock signal; one counter starts to . count upon arrival of the first signal; the other counter starts to count upon arrival of the second signal a difference between the two count values is a measurement value in the first set of measurement values. The number of measurement values ' n the first set of measurement values, is identical to the number .of clock signals in the multiple clock signals. Likewise, In the present emboc!irnent, because the phases of respective dock signals are different, the time sequence relationships of respective clock signals with the first signal and the second signal are different from each other; therefore, respective measurement values in the first set of measurement values are also different.

[45] It should be noted that the above method of measuring a latency between signals using a single clock is only an- example, and other existing or future possibly emerging methods of measuring the. latency between signals using a single clock, if applicable to the present invention,, should also be ' included within the protectio scop of the present invention and are incorporated here by reference.

{4-63 ' in step S2„ a second set of measurement values is determined according to the first set of measurement values and phas differences between the multiple clock signals and a zero-phese-difference dock signal.

fj*7] The zero-pbase-diffsrence clock signal refers to a dock signal with a fixed phase, which is artificially determined. Because a dock: signal is a si e or cosine -wave, othe dock signals have the phase difference latency with respect to the∑ero--phase-difference clock signal,

[48} in one preferred embodiment according to the method of the presen : Invention, the first signal is synchronized with the zero-phase differenc dock signal. In the present . Invention, synchronization between the first signal and the zero-phase difference clock signal refers to an inherent time sequenc relationship between the first signal and the zero-phase-difference clock signal,, while the zero-phase-dlfference clock signal refer to a clock signal that i nearest to a beginning time Indicated by the first signal and that ca capture the first signal. Fig. a illustrates a schematic diagram of a sere-phase-differencs. clock signal according to an embodiment of the present invention. The clock signals dk31,. ,dfc3S refer to multiple clock signals of the same frequency but different phases, wherein dk3I refers to the ze a-phase-dlffprence ckick signal, and sig3 first refers So the first signal. The sig3 Jirst signal is synchronljed with dock signa!clk31. 149] Respective measurement values in the first set of measurement values are results of measuring the latency using different dock signals in step Si. Because a phase difference exists between respective clock signal and the, zero-phase-difference dock -signal, phase-difference modification should be performed to the results of the first set of measurement values. In step $2, there are a plurality of manners of determining a second set of measurement, values: from the first set of measurement values and phase differences between corresponding dock signals and the zero-phase-difference dock signal, in a preferred embodiment, for each measurement value in the first set of measurement values, a phase- difference between a dock signal corresponding to the ' measurement value in the multiple dock signals, and the zero-phase-difference dock signal is added t the measurement alue, to Obtain a measurement value in the second set of measurement values. According to step SI. each measuremen valu of the first set f measurement value has its ow corresponding clock signal, which has one phase difference from the zero-phase-difference clock signal; therefore, by adding the measurement value to the phase difference between its clock s¾nal and the Eero-phase-difference clock signal, the sum is used as a measurement result in the second set of measurement values, in another -embodiment, when the first signal is not synchronized with the zero-phase-clifference clock signal, for each measurement value In the first set of measurement values, the modification using the phase difference between the dock signal corresponding to the each measurement value and the zero-phase-difference ock signal should also conside performing add or subtract operation with the phase difference between the first signal and the jero-phase-difference dock signal finally to obtain a . measurement result of the second- set .of measurement values.

[501 In step S3, a smaller measurement value Is selected from the second set of measurement values as the latency between the first signal and the second signal. The second set of measurement values refer to the measurement values thai result from measuring latency aceording to respective clock signals of different phases and are adjusted with respect to dock phase differences. Because the latency relationships of respective dock signals with the first signal and the second signal are different from each other, respective measurement results in the second .set of measurement: values are different from each other, in these measurement results, a result with a smaller measuremen value- will be closer to an actual measurement value. Therefore, the smaller measurement value ma be used as a. result of latency .measurement, m a preferred embodiment, -a smallest measurement value Is selected from -the second set of measurement -values as the latency between the first signal and the second signal The smallest measurement value is a measurement result closest to an actual standard value.

151} According to the signal processing method of the present Invention, after obtaining a measurement result of the latency between the first signal and the second signal, the signal processin method according to the present invention further comprises: compensating to a to-be-compensated signal according to the determined latency, to obtain a compensated signal. This step comprises;

[52} - compensatin the to-be-compensated signal with Integer clock periods included in the latency, to obtain an integer-clock-periods compensated signal-

[53] - compensating the Integer-dock-periods compensated signal with a non-integer clock period included In the latency, to obtain the compensated signal, wherein the com ensation with the non-integer clock .period uses a clock signal, in the multiple clock signals, which has a non-integer clock period phase difference with th ock signal used for compensating the signal.

[54J The to-be-compehsated signal refers to a signal that needs latency compensation; the Value of the to-be-com ensated latency is the latency between the first signal and the -second signal. The to-he-compensated signal may be a first signs? or any one of the signals that need latency comp«Rsat-idfj in the - electronic device. In t e present invention, the latency compensation refers to -advancing a certain specified time point in the signal by the time of the latency: With the method of the present I ven ion, a. certain specified time point in the signal may also fee delayed to the time of the latenc in implementation,. Those skilled in the art may easily know a method for performing latency compensation to the to-be-compensated signal according to the depiction of the latency compensation herein, which thus- will not he detailed,

[55] Specifically, after measuring the latency between the first signal and the second signal, the latency Is divided Into two portions: one portion is a iatenjcy -inclyding a number .of integer clock periods, and the other portio is a latency Including non-lnteger-clock-period. For example, suppose the frequency of the clock signal is IGO Hz, i.e., the dock period is 10ns, if the measured latency between the first signal and the; second signal Is 53 ns, then 53ns = 5*.lQhs +3 , i.e., the 53ns latency -compensation includes latency compensation of 5 integer clock periods and 3 latency compensation of a 3ns non-inleger-clock-period . Or 53ns - 6*iGns-7 ' i¾s, i.e., . the S3ns ia-tency . compensation includes latency compensation of 8 Integei-clock-periods and a latency compensation of 7ns cran-integer-clock-per od,

[56] The ste of performing latenc compensation to the to-be-compensated signal is divided into, two portions: the first step is performing, integer-clock-p riods, latency compensation, while the second step is performing non-lnteger-dock-period latency compensation. The clock signal to b subjected to intege ^ ciock- eriods latency compensation may he any dock signal with a same frequency but a different p ase, and the method for latency compensation may use- any manner; comprising: usi g - . a clock signal to delay the to-be-cornpensated signal, so the:deiayed signal just starts at the position for latency compensation from the next: period. The dock signal employed in the first step for integer dock periods latency delay may foe any one of the clock signals in multiple clock signals. Preferably, a dock signal synchronized with the to-he-compensaied signs! ma be employed, i.e., the phase relationship between the clock signal and the to-be-compensated signal Is fixed, and a samplsng edge of the clock signal is nearest to start: point of the to-be -compensated signal and can capture the to-be-compensaie signs?. When performing the non-integer-ciock-period latency compensation In the second step, because the latency is of a non-lnteger-ciock-period and the beginning time of the s1gr»ai"wjH be advanced to the position of the rion-lnteger-dock-period, the phase of the dock signs! employed In the step Is prior to the phase of the dock signal used in the inte er Sock-perlods compensation in the first step; the phase differenc between the two docks is he: non-integer-clock-period, thereby implementing a non-lnteger-cldck-periad latency compensation.

[5-73 t should be noted: that the above two steps of latency compensation are added for the sake of clear depiction. There is no strict sequential order for th two steps. The electronic device may perform" a rton-jntegen-clock-period latency compensation while performing a integer-clock -periods latency compensation, or perform the non-integer-clock-period latency compensation and then perform Integer-ciock-perlads latency compensation,

fSS] Fig. 4; illustrates a schematic signal . diagram .of performing latency compensation to a to-be-compensated signal according to an embodiment of the present Invention, In the. figure, cik4Q„,., cik43 are clock signals of the same frequency but different phases, while the to-be-eompensated signal Is s¾4 that is synchronized with th cik40; the period of the sig4 signal is- 240ns, the latency tha needs compensation 2-2ns, the clock period Is Sns; the phase difference between each clock signai in ' respective clock signals and- a preceding clock signal is 2ns. Because- 22ns=2*8÷6ns, cik40 is. first used, to perform 2-clock-penods latency compensation to sig4, i,e. t fi st using dk 0 to delay the: sig4 signal by: 24Dns--3,Sns"224ns to ob ain the sig4. jLl signal; then,. c\k41 is used to perform a 6 ns latency compensation to the ssg __tl ts obtain the final compensated signai sig4_el, i.e., using clk41 to deiay sig4_tl by- ( 2 0-85 /8=29 clock periods to obtain sig4. el. Another man-net of performing 22ns latency compensation comprises; first using dk4Q to perform 3-i.iock-penods latency compensation to the slg4, i.e., using clk40 to delay the ssgA signal by 240ns- 24ns=21Sns to obtain sign_t:2 signai; then, eik41 is used to delay sig4 tl by 2ns to obtain the final compensated signal Sig4_„e2, Sig4_el and slg4„e2 obtained using the abo e two manners may foe used as ' the compensated .signal derived from performing a 22ns latency compensation to the slg4 signai.

[59] Fig, S- illustrates a schematic diagram of a time sequence relationship among s als according to- an embodiment of the present invention, in th present emljddirrieni, suppose there are 4 eiod? signals cikSi,„„ dkS4-of the .same frequency. but different phases, where the frequency of the ciock signals is " 125MHz,. i.e., the ' clock period is 8 ns. Sig5 . ..firsi is the first sign at while S!gS__secorid is : the second signal; the latency between the first signai and the second signal may denote a beginning t me and an ' end time using rising edges of the -two . si nal , respectively. The actual value of the to-be-measured latency is 2?ns, SigS ^ first is synchronized with the clkSO, and the c!kSO is a : serd-phasS'-differersee clock. Counters!,..., counter54 are counters for obtaining the first set of measurement values. The clocks of the counters correspond to cikSl,. cik54, respectively.. Accordin - ' to step Si, the counters start counting upon arrival of the rising edg of the sig5...first, while stop counting upon arrival of the: rising edge of the -sigS- second. The ' values ' of counters after stopping counting are respective measurement values of the first set of measurement values, e,g.> the values circled in the figure. According to step 32, the values' of mea2_51, mes2__.52, .meaS ^ SS and mea ' 2J54 are derived by summing the first set of measurement values and the phase differences between corresponding clocks: and the zero-phase-dlfference clock. The values of mea2Jsl, mea?,.52, maa2JS3 and mes2_54 are the measured values of- he second set of measurement values. According to step S3, the minimum ' measurement value is the value of mea2_5-2: 28s,, i.e., the measured latency value is 2Sns,

[60] Fig. 6 Illustrates a structural schematic diagram of a signal processing apparatus. 600 according to an embodiment in another aspect of the present Invention.

[6%] Wherein, the signal processing apparatus 600 In the present embodiment is mainly implemented through an electronic device. The electroni device includes, but not limited to, a communication device, a- terminal device, a network device, a medical device,: or a measurement instrument, among other electronic devices, he communication device includes, hut not limited to, a router, a; switch, a base station, s core network, a wireless .local area network controller or etc. The temiinai device Includes, but not limited to, a smart mobile phone, a tablet computer, a PDA,, a PC or etc. The network device includes, but not limited to, a single network server, a serve group comprised of multiple network servers, or a cloud computing-based cloud comprises of a considerable number of computers or network servers. In the present embodiment, the signai processing apparatus 600 may process a digital signal, or an analog signal, If a to-be-processed signai. is an analog signai, it Is preferred to be first subjected to an analog-digital conversion, and the obtained digital signai, it is- processed according to the apparatus illustrated In Fig. 8.

{62} The signal processing apparatus 600 according to the present embodiment comprises a first unit SGI, a second unit 602, and a third unit 603, The first unit SOl is conf ured to get a first set of measurement values. The second unit 602 is configured to get a second set of measurement values. The third unit 603 is configured to get the latertcy between the first signal and the second signal

> 63] The first unit 601 is configured to measure a latency between a first signal and a second signal using multiple clock signals of the same frequency but different phases, to obtain a first set of measu rement values.

6 1 Before further introducing: the first unit 601,, in order to facilitate understanding, multiple clock signals involved therein and the concept of latency between the first signal and the second signal will be illustrated first

[6S] In the present embodiment, multiple dock signals ar used. The multiple clock signals have the same frequency, but different phases. The number of clock signals might not be restricted. Phase differences among clock signals may be equal, i.e.,, the phase differences between each clock signal and a preceding dock signal Is equal. When performing latency measurement between signals according to the method of the present invention, an accuracy of the measurement result can be determined relatively easily using such multiple clock signals, for example, suppose there are 10 clock signals each clock frequency is QOM ' Hz; the phase difference ' between the each dock signal In the 10 clock signals and the preceding clock signal is i ns; in this way, .an error of the measurement result may be ins. The phase differences among clock signals may also be unequal, for example, suppose there are 8 clock signals with a frequency o lOOMHz; the phase difference between the dock signal 1 and the clock signal 2 is 3ns; the phase difference between each clock signal in the seven signals from clock signal 2 to clock signal 8 and the preceding dock signal is Ins. Figs. 2a arid 2b illustrate schematic diagrams of multiple clock signals of the same frequency but different phases according to an embodiment of the present invention. Fig, 2a shows 4 clock signals with s frequency of 125MH¾, i.e., the clock period is 8ns; the phase difference between each clock signal in the clock -signals and a preceding dock signal is 2ns. Fig; 2b shows 5 dock signals with a frequency pf 125MHz, I.e., the dock period is 8ns; the phase difference between the dock signal dkXbl and the dock signal c!k2bZ is 3ns; the phase difference between the dock signal dk2b2 and the dock signal dk2b3 is 2ns the phase difference between the clock signal clk2b3 and the clock signal clk2h4 is Ins; the phase difference between the deck signal eikS and the. dock signal dk2b¾ is: Ins; the phase difference between the dock signal clklbS and- the dock signal cik2bi is ins.

IS6] The first signal is a signal without latency,, while the second signal Is a signal with a latency after the first signal is transmitted via a circuit. The first signal and the second signal are ot limited to the digital signals, which may also be analog signals. The latency between the first signal and the second signal may also be represented through other manners, e.g... a pulse of a digital signal may be used to ' indicate a beginning or end time point of the latency; or a digital level signal may be used to indicate a beginning or end time point; or a certain fixed high-low level variation manner may be used to Indicate a beginning or end: time point. In addition, a to-be-measured latency between the first: signal and the /second signal may also be alternatively represented by one signal,. e.g., a rising edge of the signal indicates a beginning time point of " the latency, while a failing edge of the signal indicates an end point of the latency Multiple signals the phase difference latency with respect to the zero-phase-difference clock signal,

£713 . in one preferred embodiment according to the apparatus, of the present invention, the first signal is synchronized with the zero-phase difference clock signal, to the present invention, sy ch onisation between the first si nal and the zero-phase difference clock signal refers to an inherersi time sequence relationship bet een the first signal and he zera-p sse-dsfference clock signal, while the : sero-phase-differenefi clock signal refers to a clock signal that ss nearest to: a beginning time : indicated by the first signal and that can capture toe first signal. Fig.3 Illustrates a schematic diagram of s zero-^hase-dirferenee clock signal according to an embodiment of the present nvention. The clock signals clfc3I,.,.,dk35 refer to multiple clock ssgstsis of the same frequency but different phases, wherein clkSl refers to the zerorpha-se-differercce clock signal, and sig3„first refers to the first signal. The s¾3- first signal is synchronized with dock signal ' c!fcSl. {?2} Respective measurement values in the first set of measurement values are results of measuring , the latency .using differen clock signal in th first unit 601. Because a phase difference exists ¾et¾eeen respective dock sigrsal and the zero-phase-difference dock signal , , phase-difference modification should be performed to the results of the first set of measurement values. In the second unit 602, there are a plurality, of manners of determining a second set of measurement alues from the first set of measurement values and . phssa differences between corresponding clock signals and th zero-phase-dif!erene clock signal. In a preferred embodiment, the second unit 68 is configured to, for each measurement valu in the firs set of measurement values, add .a phase difference between a clock signal corresponding to the measurement- value in the multiple dock signals and the <tero-phase-dlfference dock signal to the .measurement value, to obtain a measurement value, in the second set of measurement values. In the first unit 601, each measurement value of. the first set of measuremen plus ' s has its own corresponding clock signal, which has one phase difference from the zsro-ohase-difTerence lock, signal; therefore, by adding the measurement value to the phase difference: between its clock , signal and the zeK pha e-differsnce clock signal, the sum is used as a measurement result- I the second set of measurement values, in another embodiment;, when the first signal is no synchronised with the i d-phase-difference clock signal, for each measurement value in the first set of measurement values, the modification using the phase difference between the clock signal corresponding to the each measurement value and the zero-phase-difference clock signal should also consider performing add or subtract operation with the phase difference between the first signal and the zero-phase-difference clock signal finally to obtain a measurement result, of the second set o measurement values..

[73] the third unit 693 Is configured to select a smaller measurement value from the second set of measurement values as the latency between the first signal and the second signal. The second set of measurement values refer to the : measurement values that result from, measuring latency according to respective dock signals of different phases and are adjusted with respect to clock phase differences. Because the latency relationships of respective clock signals with the first signal and the : second signal are different fro each other, respectiv measurement results in the second set of measurement values are different from each other. In these measurement results,; a result with a. smaller measurement valu will be closer to ah actual . measurement value. Therefore, the smaller- measurement value may be used ' as a result of latency measurement, i a preferred embodiment, th : thir unit 603 is configured to .select a smallest measurement value from the second set of measurement values as the : latency between the first signal ' and- the second signal. The smallest .measurement alue is a measurement result closest to an actual standard value.

i?4j According to the signal processing apparatus of the present Invention,., after obtaining- a measurement result of the latency between the first signal and the second -Signal, the signal processing apparatus - according to the present Invention further comp ises: a fourt unit 604 configured to perform latency compensation to a to-be-compensated signal according to the determined latency, to- obtain -a compensated signal. The f compensation operation: comprises:

[75] - compensating the to-be-compensated signal with Integer dock periods Included in the latency, to obtain an integer-dack-senods compensated signal;

1761 - com ensate the integer-clock-periods compensated signal wit 3 non-integer clock period included in the latency, to obtain the compensated signa wherein the compensation with the non-integer dock period uses a clock signal, in the multiple dock signals, which has a non-integer, clock period, phase difference with the dock signal used for compensating the- signal.

[77] The to-he-compensated signal refers to a signal that needs latency compensation; the value of- the to-be-compensated latency is the latency betwee the first signal and the second signal. The to-be-compensated signal may be a first signal or any one of the signals that need .latency compensation in the electroni device, in the present .invention, the latency com nsation refers to advancing a certain specified .time point in the signal by the time of the latency. With, the method of the presen invention,, a certain specified time point in the signal may also b delayed to the time of the- latency in implementation:. Those skilled in the art may .easily know a method for performing: latency compensation to the to-be-compensated signal according to the depiction f the latency- compensation herein, which t hus will not be detailed.

p j For the fourth unit 604, . specifically, after measuring the latency between the first-signal and the second; signal, the latency is . divided into two portions: one portion i a latency including a number of integer clock periods, and the other portion is a latency including: non-integer-ciock-penod. For example, suppose the frequency of the dock signal is 2QQMB¾ i.e., the clock, period Is-iGfts-; If the measured latency between the first signal and the second signal is 53ns, then 53ns = 5*iOas +3ns, i.e., the 53ns latency compensatio includes latency compensation of 5 Integer clock periods and a . latency compensation of a 3ns non-integer-doek-penod. Or 53n * S*iGns-?ns, i.e., the 53ns latency compensation includes latency- compensation, of 6 integer-elock-periods and a latency compensation of 7 ns non-integfif-dock-perlod.

(791 The step of .performing latency compensatio to the to-be-compensated signal is divided into two portions-, the first step is performing integer-clock-periods latency compensation, while the second step is performing non-integer-tiock-perk>d latency compensation. The clock -signal to be subjected to integer-clock-periods latency compensation may be any c ck.slgnai with a same frequency but a different, phase, and the method for latency compensation may use any manner; comprising; .using -3 clock signal to delay the to-be-compensated sjgna -so the delayed, signal just Starts at the position for latency compensation from the next period. The clock signal employed In the first step for Integer dock periods latency delay may be any- one f the clock signals in -multiple clock signals. Preferably, a clock signal synchronized with the ' to-be-compensated signal may be employed, i.e., the phase relationship- between the clock signal and th to-be-compensated signal is fixed, and a sampling: edge of the dock signal Is nearest to start point of the to> Decompe sate signal and can capture the to-be-compensated signal. When performing ' the. nOnHn egerelosk-per ' i d latency compensation in the second-step,, because the latency is of s non-integef tock-penQci and the beg inning time of the signal will be advanced to the position of the i non-lnteger-dock-period, the phase of the clock signal employed h the ste Is prior to the phase of the clock signal used in ..the integer-clock-perlods compensation in ' the first step; the phase difference between the two clocks is the nomlnteger-cioek-perscd, thereby implementing a non-integer-clock-period atency compensation,

.180]. rt should e note that the above two steps of late cy com ensation are added for the sake of clear depletion, there is no strict sequential order for the two steps. The electronic device may perform: a non-integer-elodc-penod latency -compensation -while performing a Integer-dock-perlods latency compensation., or perform the nondnteger-dock-period latency compensatio and then perform .integer-efeck-perlods latency ■■ compensation.

■[81] Fig- . Illustrates a schematic signal diagram of performing latency compensation to a io-be-compensated signal according to an embodiment of the present invention, hi the figure,. c,%40,,.,, k: 43 are clock signals of the same frequency but different phases, while the to- be+compensated signal is sig4 that is Synchronized with the clk40; the perlod of the sig4 : signal is 240ns, the latency that needs compensation Is 22ns, the clock period Is 8ns; the phase difference between each dock signal in respective clock signals and a preceding dock signal Is 2ns. Because 22ns=2*8+6ns, ci¾40 is first used to perform 2"C.lotk-periads latency compensation to sig4, Ce., first using rJk40 to delay the sig4 signal by 2 0ns-a8hs=2Z4sns to obtain the slg4 ti Sigi-!isi then, c l is used to perform a 6ns latency compensation to the sig4j.l to obtain the final compensated signal ssg4_ el. I.e., using: cl i to delay slg4Ji by |24S-S}/8~-29 clock periods to obtain sig4 jel.. Another manner of performing 22ns latency compensation comprises; first using cl 40 to perform 3-riock-periods :■ .latency compensation to -the sig4, Is,, using cik40 to delay the sig4 .signal by 240ns-24ns=216ns to obtain $igrs_t2 signal; then, cik4i Is used , to delay sig4 ti by 2ns to obtain the final compensated signal stg4„e2, Ssg el and slg4 e2 obtained using the above two manners may be use as th compensated signal derived from .performing a 22m latency compensation to the :: sig4 signal.

[82] Fig. S illustrates a schematic diagram of a . time sequence relationship among signals according to an embodiment of the present invention, in the present embodiment,, suppose there are 4 clock signals cfkSX, dicS4 of the same frequency but different phases, where the frequency , of the- dock signals Is 125MHz, I.e., the- Clock period is 8ns. SigSJkst is the first signal, while sigS_second Is the second signal; the latenc between the first signal and the second signal may denote a beginning time and an end time ysing rising edges of the two signals, respectively The actual yalue of the . to-be-measured latency is 2.7ns, SlgS . first is synchronized ' with. the cikSO, and the cikSO is a Kero-phase-dSr erence clock. Countes-51, ..., counter$4 are coimters for obtaining ' the first set of measurement values. The clocks, of the counters correspond to cikS ' l, ...» e|k54, respectively. According to the first unit ' 601, the counters start counting upon arrival of the risin edge of the sigSJirst, while sto counting upon arrival of the rising edge of the sigSjsecortd. The values of counters after stopping counting are respective measurement- values of the first set of measurement vaiues,, : e.g., the values circled in the figure. According to the second unit. 602, the values of mea2 51, es2_ S2, mea2 S3 and mea2_S4 are derived by summing the first set of measurement .values- and the phase differences between correspondin clocks and the zerd-phase-difference clock. The values- of mea2,. Sl, mea2_.52, mea2 53 and mea2_ 54 are measured values of the second set of measurement values. According to the third unit 603, the minimum measurement value is the value i mea2 _S2;: 28s, i.e.,. the measured latency value is 28ns,

{ 833 Sft an embodiment of a further aspect of the -present invention, there s provided art electronic device, including signal processing apparatus 630 as ' illustrated in fig. 6. The electronic device includes, but not limited to, a communication device, a terminal device, a network device, a medical device, or a measurement. instrume ' rit, among other electronic .devices. The communication device Includes, but not limited to, s router, a switch, a base station, is core network, a wireless local area network controller or etc The. terminal device includes, but not limited te a smart mobile phone, a tablet computer, a PDA, a PC or etc. The network devicencludes, but not limited to, a single network .server, , a server- group comprised of multiple network servers, or a cloud computing-based doud comprises of a considerable numbe of computers or network servers. In the present embodiment, a met od for signal processing may perform processing to a digital signal, .or may perform processing te ars analog signal.

ISA] St should be noted that the present Invention may be implemented in software and/or 3 combination of software and hardware. For example, various modules of the present invention may be- implemented using an application-specific integrated circuit (ASIC) or any other similar hardware devices. In one embodiment th¾ software program of the present invention may be executed -by the processor to- implement the steps or functions, above. Likewise, the software- program ' (including a relevant data, structure) of the present invention may be stored in a computer-readable recordin medi m, e.g., a RA. memory, a magnetic or optical driver or 3 floppy disk and a similar device, in addition, some steps or functions of the present invention may be implemented by hardware, e.g., as a circuit cooperating with th processor so as to execut respective steps or functions.

|853 To those skilled in the art, it is apparent that the present Invention is not limited to the details of the illustrative embodiments, and without departing from the; spirit or basic feature of the present invention. The present invention can be implemented in other specific, form. Therefore, In any perspective, the embodiments should be regarded as illustrative, not limitative. Th scope of the present- Invention is limited by the appended claims, rather than the depiction above. Therefore, all variations, within the meanings and scopes of equivalent elements of the claims are covered within the present invention. No reference numerals in the claims should be regarded as limiting the involved claims. Besides, it is apparent tha the word "comprise" or ' ""include" does not. exclude other units or steps, and a singular form does not exclude plurality. A plurality of units or modules stated in a syste claim may also be Implemented by one unit or module through software o hardware. Words like the first and second are used to indicate names, not indicating any specific sequen e.