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Patent Searching and Data


Title:
SIGNAL PROCESSING DEVICE AND METHOD, AND SIGNAL DECODING DEVICE AND METHOD
Document Type and Number:
WIPO Patent Application WO/2005/099092
Kind Code:
A1
Abstract:
A signal processor (10) realizing the second order term of a second order Voltera filter comprising multipliers for multiplying first and second input signals wherein each multiplier comprises one or more delay circuits connected in series and delaying the out signal from the multiplier by a unit time and a coefficient multiplier for multiplying the output signal from the multiplier and the output signal from each delay circuit by specified coefficients. Such multipliers the number of which is n (n is an integer of 1 or more) are connected in parallel, and the k-th multiplier (k is an integer satisfying the relation 1≤k≤n) employs a signal obtained by delaying the first signal by (k-1) times of the unit time as a second signal.

Inventors:
KAJIWARA YOSHIYUKI (JP)
Application Number:
PCT/JP2005/005371
Publication Date:
October 20, 2005
Filing Date:
March 24, 2005
Export Citation:
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Assignee:
SONY CORP (JP)
KAJIWARA YOSHIYUKI (JP)
International Classes:
G11B20/10; G11B20/18; H03H17/00; H03H17/02; H03H17/06; H03H21/00; (IPC1-7): H03H17/00; G11B20/10; G11B20/18; H03H17/02
Foreign References:
JP2001525101A2001-12-04
Other References:
GLENTIS G.-O.A. ET AL: "Efficient algorithems for Volterra system identification", IEEE TRANSACTIONS ON SIGNAL PROCESSING, vol. 47, no. 11, November 1999 (1999-11-01), pages 3042 - 3057, XP002989600
MATHEWS V.J.: "Adaptive polynomial filters", SIGNAL PROCESSING MAGAZINE, vol. 8, no. 3, July 1991 (1991-07-01), pages 10 - 26, XP000436340
Attorney, Agent or Firm:
Koike, Akira (Yamato Seimei Bldg. 1-7, Uchisaiwai-cho 1-chom, Chiyoda-ku Tokyo, JP)
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