SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, DELTA-SIGMA MODULATION TYPE FRACTIONAL DIVISION PLL FREQUENCY SYNTHESIZER, RADIO COMMUNICATION DEVICE, DELTA-SIGMA MODULATION TYPE D/A CONVERTER

Title:

SIGNAL PROCESSING DEVICE, SIGNAL PROCESSING METHOD, DELTA-SIGMA MODULATION TYPE FRACTIONAL DIVISION PLL FREQUENCY SYNTHESIZER, RADIO COMMUNICATION DEVICE, DELTA-SIGMA MODULATION TYPE D/A CONVERTER

Document Type and Number:

WIPO Patent Application WO/2004/023661

Kind Code:

A1

Abstract:

A fractional divider (28) includes a latch (31) for holding division data, a &Dgr Σ modulator (33), a digital dither circuit (32) for receiving a digital input F representing the fractional portion of the division data from the latch (31) and supplying a digital output alternately changing between F+k and F-k (k is an integer) or the F value itself to the &Dgr Σ modulator (33), and circuit means (34 to 38) for executing fractional division operation according to the integer portion (M value) of the division data and the output of the &Dgr Σ modulator (33). The digital dither circuit (32) serves to suppress a spurious signal generated as a result of concentration of quantization noise at a particular frequency when the &Dgr Σ modulator (33) has received a particular F value (for example F = 2^n-1).

Inventors:

NAGASO YOICHI (JP)
SAEKI TAKAHARU (JP)

Application Number:

PCT/JP2003/010885

Publication Date:

March 18, 2004

Filing Date:

August 27, 2003

Export Citation:

Click for automatic bibliography generation Help

Assignee:

MATSUSHITA ELECTRIC IND CO LTD (JP)
NAGASO YOICHI (JP)
SAEKI TAKAHARU (JP)

International Classes:

H03M1/20; H03L7/183; H03L7/197; H03M1/08; H03M3/00; H03M3/02; H03M7/00; H03M7/36; H04B14/06; (IPC1-7): H03M3/02; H03L7/18

Foreign References:

JP2002152044A	2002-05-24
JPH05284033A	1993-10-29
JPH0225116A	1990-01-26
JP2001237709A	2001-08-31

Other References: