Title:
SIGNAL PROCESSING DEVICE AND METHOD
Document Type and Number:
WIPO Patent Application WO/2018/163840
Kind Code:
A1
Abstract:
The present technology relates to a signal processing device and method which enables the suppression of a reduction in reception sensitivity. The present technology compresses a reception signal to a prescribed signal level or lower, and decodes transmission data which is included in the reception signal compressed to the signal level or lower and has been transmitted from a transmission side. For example, the present technology generates a schematic replica signal in which a large amplitude change of the reception signal is reproduced, and compresses the reception signal to the signal level or lower by subtracting the schematic replica signal from the reception signal. The present disclosure can be applied, for example, to a signal processing device, a reception device, a transmitting and receiving device, a communication device, an information processing device, an electronic device, a computer, a program, a recording medium, a system, etc.
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Inventors:
KOBAYASHI SEIJI (JP)
Application Number:
PCT/JP2018/006417
Publication Date:
September 13, 2018
Filing Date:
February 22, 2018
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H04B1/7097; H04B1/10
Foreign References:
| JP2010252249A | 2010-11-04 | |||
| JPH09214397A | 1997-08-15 | |||
| JP2016046618A | 2016-04-04 | |||
| JP2016046618A | 2016-04-04 | |||
| JP4443991B2 | 2010-03-31 |
Other References:
TADA, YASUTAKA ET AL.: "High anti-interference performance of 802.15.4k DSSS systems to coexist with others in 920 MHz band", IEICE TECHNICAL REPORT, vol. 114, no. 84, 9 June 2014 (2014-06-09), pages 35 - 39, XP055605204
See also references of EP 3595182A4
See also references of EP 3595182A4
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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