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Patent Searching and Data


Title:
SIGNAL PROCESSING DEVICE
Document Type and Number:
WIPO Patent Application WO/2014/181573
Kind Code:
A1
Abstract:
A first clock generation circuit (21) generates a first clock that rises with a delay of αT (0.5<α<1.0) from the transition point of each data in a Manchester-coded received signal having a cycle of T. A second clock generation circuit (22) generates a second clock that rises with a delay of βT (0.5<β<1.0) that is different from αT. A data detection circuit (31) outputs first and second detection results of the received signal on the basis of the first clock and the second clock, and the received signal is determined at a determination circuit (41) on the basis of the first and second detection results.

Inventors:
KITSUKAWA YUSUKE (JP)
HIRAI AKIHITO (JP)
HIRAMINE MASANOBU (JP)
NAKAMIZO HIDEYUKI (JP)
KAWAKAMI KENJI (JP)
Application Number:
PCT/JP2014/055670
Publication Date:
November 13, 2014
Filing Date:
March 05, 2014
Export Citation:
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Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
H04L7/02; H04L7/00; H04L25/49
Foreign References:
JP2010130138A2010-06-10
JP2012039357A2012-02-23
Attorney, Agent or Firm:
TAZAWA, Hideaki et al. (JP)
Hideaki Tazawa (JP)
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