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Title:
SIGNAL TRANSMISSION CIRCUIT, SWITCH DRIVING DEVICE, AND POWER MODULE
Document Type and Number:
WIPO Patent Application WO/2019/167827
Kind Code:
A1
Abstract:
A filter circuit (80), having a first rise delay circuit (82a) for delaying the rise timing of a first shifted signal by a prescribed time and outputting the result, and a first fall delay circuit (82b) for delaying the fall timing of a second shifted signal by a prescribed time and outputting the result. The first rise delay circuit (82a) is configured so that a second rise delay signal does not follow a variation towards the side in which a first voltage decreases, and follows a variation towards the side in which the first voltage increases. The first fall delay circuit (82b) is configured so that a second fall delay signal does not follow a variation towards the side in which the first voltage decreases, and follows a variation towards the side in which the first voltage increases.

Inventors:
ISHIMATSU YUJI (JP)
Application Number:
PCT/JP2019/006733
Publication Date:
September 06, 2019
Filing Date:
February 22, 2019
Export Citation:
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Assignee:
ROHM CO LTD (JP)
International Classes:
H03K17/16; H02M1/08; H03K17/687
Foreign References:
JP2012175437A2012-09-10
JP2015033248A2015-02-16
JP2009278406A2009-11-26
JP2013183422A2013-09-12
JP2008278729A2008-11-13
JP2007235245A2007-09-13
Attorney, Agent or Firm:
ONDA Makoto et al. (JP)
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