Description

SIGNAL TRANSMITTING APPARATUS AND SIGNAL TRANSMITTING METHOD

Technical Field

[1] The present invention relates to a signal transmitting apparatus and a signal transmitting method.

[2] In particular, the present invention relates to a signal transmitting apparatus and a signal transmitting method that transmit data through a plurality of signal lines constituting a data bus while interfacing. Background Art

[3] When data is transmitted in parallel through data transmission lines having a plurality of signal lines, signal delay is caused by parasitic resistance of each transmission line.

[4] FIG. 1 is a waveform diagram illustrating signal delay according to a plurality of transmission lines.

[5] Referring to FIG. 1, data transmitted according to a clock signal Clock are transmitted through respective transmission lines BUSl, BUS2, BUS3, and BUS4 with predetermined signal delays.

[6] Such signal delays have different values depending on parasitic resistance of the respective transmission lines BUSl, BUS2, BUS3, and BUS4.

[7] When data that are transmitted through the transmission lines BUSl, BUS2, BUS3, and BUS4 are digital signals, since the digital signals are transmitted at a higher speed than, for example, analog signals, the signal delay may cause a data error. As shown in FIG. 1, when data are exchanged in parallel, a time required for loading the data on the transmission lines BUSl, BUS2, BUS3, and BUS4 stably varies according to the transmission lines BUSl, BUS2, BUS3, and BUS4. For this reason, after the data loaded on all of the transmission lines BUSl, BUS2, BUS3, and BUS4 stabilized, logic values are determined based on a synchronizing clock.

[8] Accordingly, when interfacing to a memory is carried out through a programmable logic device (PLD), even if the clock signal for the data transmission lines BUSl, BUS2, BUS3, and BUS4 does not conform to the memory specification, a clock signal having a plurality of cycles must be used to make data stable. This may cause a decrease in memory access speed.

[9] The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art that is already known in this country to a person of ordinary skill in the art.

Disclosure of Invention

Technical Problem

[10] The present invention has been made in an effort to provide a signal transmitting apparatus, having an advantage of transmitting signals uniformly through a data bus having a plurality of signal lines when a user carries out interfacing to a memory by hardware. Technical Solution

[11] An exemplary embodiment of the present invention provides a signal transmitting apparatus including: a plurality of data transmission lines that transmit output data to a memory; a plurality of delay units that are correspondingly connected to the plurality of data transmission lines, that delay test data according to a delay signal for a predetermined time, and that output the delayed test data to each of the data transmission lines; and a transmitting/receiving controller that compares the stored data in the memory with the test data to adjust the delay signal, and outputs the adjusted delay signal to each of the plurality of delay units.

[12] The transmitting/receiving controller may set a delay signal as a final delay signal when a difference between the stored data and the test data has a minimum value, for the plurality of delay units, and may output the final delay signal to each of the plurality of delay units.

[13] A delay time of each of the delay units according to the final delay signal may be smaller than the cycle of a clock signal for data transmission of the test data.

[14] The signal transmitting apparatus may further include a plurality of selection units that receive input data from the outside and the test data from the transmitting/ receiving controller, and that selectively output one of the input data and the test data to each of the delay units.

[15] The test data to be input to the plurality of selection units may be the same.

[16] Each of the delay unit may include a plurality of buffers, and the number of buffers through which the test data passes may be determined according to the delay signal.

[17] Another embodiment of the present invention provides a signal transmitting method including: transmitting test data to which an initial delay value is applied to a memory through a data bus; reading data stored in the memory and comparing the stored data with the test data; changing a delay value according to the comparison result; and applying the changed delay value to the test data and transmitting the test data to the memory through the data bus.

[18] The comparing of the stored data and the test data may determine whether or not the stored data and the test data corresponding to a plurality of data buses have the same waveform.

[19] When a signal difference between the stored data and the test data corresponding to a plurality of data buses has a minimum value, the changed delay value may be determined as a final delay value.

[20] The signal transmitting method may further include applying the final delay value to input data and transmitting the input data to the memory.

[21] A delay time according to the final delay value may be smaller than the cycle of a clock signal for data transmission of the input data.

[22] The signal transmitting method may further include selecting one of the input data from the outside and the test data according to a selection signal and outputting the selected data.

[23] The same test data may be transmitted to the plurality of data buses.

[24] The delaying of the test data may cause the test data to pass through buffers, the number of buffers being determined according to the delay value.

Advantageous Effects

[25] Therefore, according to the present invention, when data is transmitted to a memory through a data bus, a delay value can be adjusted among a plurality of signal lines constituting a data bus, and thus signal transmission can be performed uniformly. Brief Description of the Drawings

[26] FIG. 1 is a waveform diagram illustrating signal delay according to a plurality of transmission lines.

[27] FIG. 2 is a block diagram illustrating a signal transmitting apparatus according to an exemplary embodiment of the present invention.

[28] FIG. 3 is a schematic diagram illustrating an example of a delay unit shown in FIG.

2.

[29] FIG. 4 is a flowchart illustrating the operation of the signal transmitting apparatus shown in FIG. 2. Mode for the Invention

[30] In the following detailed description, only certain exemplary embodiments of the present invention have been shown and described, simply by way of illustration. As those skilled in the art would realize, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature and not restrictive. Like reference numerals designate like elements throughout the specification.

[31] Throughout this specification and the claims that follow, when it is described that an element is "coupled" to another element, the element may be "directly coupled" to the other element or "electrically coupled" to the other element through a third element.

[32] Throughout this specification, unless explicitly described to the contrary, the word

"comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements. In addition, the terms "-er", "-or", "section", "unit", and "module" described in the specification mean units for processing at least one function and operation and can be implemented by hardware components or software components and combinations thereof.

[33] Hereinafter, a signal transmitting apparatus that can transmit signals with no signal delay will be described with reference to FIGS. 2 and 3.

[34] FIG. 2 is a block diagram illustrating a signal transmitting apparatus according to an exemplary embodiment of the present invention, and FIG. 3 is a schematic diagram illustrating an example of a delay unit shown in FIG. 2.

[35] Referring to FIG. 2, a signal transmitting apparatus 100 according to an exemplary embodiment of the present invention includes a transmitting/receiving controller 110, a selection unit 120, and a signal delay section 130.

[36] The transmitting/receiving controller 110 receives an initial signal IS from the outside, initializes the selection unit 120 and the signal delay section 130, and controls the selection unit 120 and the signal delay section 130.

[37] The selection unit 120 includes a plurality of multiplexers MUXl to MUXl. The multiplexers MUXl to MUXl are correspondingly connected to delay units DUl to DUl, select transmission signals DATl to DATl from the outside and initial test values TSl to TSl from the transmitting/receiving controller 110, and output the selected signals to the delay units DUl to DUl.

[38] The signal delay section 130 includes the plurality of delay units DUl to DUl. The delay units DUl to DUl are connected between the multiplexers MUXl to MUXl and data buses DBl to DBl, respectively. The delay unit DUl to DUl receive the output signals from the multiplexers MUXl to MUXl connected thereto and control signals CONl to CONl from the transmitting/receiving controller 110, and output the output signals while delaying the output signals according to the control signals CONl to CONl for a predetermined time, respectively.

[39] The plurality of data buses DB 1 to DBl include a plurality of data line groups, and are connected to different ports of a memory 200. A delayed signal is transmitted to the memory 200 through the data bus DBi through the delay unit Dui (where i = 1, 2, .., and 1).

[40] Referring to FIG. 3, the delay unit DUi includes a plurality of buffers B 1 to Bn and

Ba to Bn-I, and a multiplexer MUX.

[41] The plurality of buffers Bl to Bn and Ba to Bn-I include buffers Bl to Bn that are connected in series, and buffers Ba to Bn-I that receive signals on connection points between the buffers B 1 to Bn and output the signals to the multiplexer MUX.

[42] Each of the buffers Bl to Bn and Ba to Bn-I outputs input data Din while delaying the input data for a predetermined time. The delay time is determined according to the number of buffers B 1 to Bn and Ba to Bn-I through which the input data passes.

[43] Accordingly, a plurality of delayed signals input to the multiplexer MUX have different values. The multiplexer MUX selects one delayed signal according to the control signal CONi from the transmitting/receiving controller 110 and outputs the selected delayed signal as an output signal Dout.

[44] Hereinafter, a method of adjusting a delay value according to an exemplary embodiment of the present invention will be described with reference to FIG. 4.

[45] FIG. 4 is a flowchart illustrating the operation of the signal transmitting apparatus shown in FIG. 2.

[46] Referring to FIG. 4, if a signal transmission operation starts, the transmitting/ receiving controller 110 receives the initial signal IS from the outside (S201).

[47] The transmitting/receiving controller 110 sets the initial test values TSl, to TSl according to the initial signal IS, and correspondingly outputs the initial test values TSl to TSl to the multiplexers MUXl to MUXl (S203).

[48] The initial test values TSl to TSl are used when the user sets whether or not to use a timing trace mode, and inform of signal timing to be written and read with respect to the memory 200 at the beginning of interfacing. The initial set values are values before optimization, and may be the same as the initial test values TSl to TSl for the plurality of multiplexers MUXl to MUXl.

[49] The transmitting/receiving controller 110 also sets initial delay values for the plurality of delay units DUl to DUl and outputs the set initial delay values.

[50] The plurality of multiplexers MUXl to MUXl output the initial test values TS 1 to

TSl from the transmitting/receiving controller 110 to the delay units DUl to DUl, respectively. The delay units DUl to DUl delay the initial test values TSl to TSl according to the initial delay values, and transmit the delayed initial test values to the memory 200 through the data buses DB 1 to DBl, respectively.

[51] Next, the transmitting/receiving controller 110 reads, from the memory 200, the initial test values TSl to TSl stored in the memory 200, and compares the read initial test values TSl to TSl with the initial test values TSl to and TSl stored therein (S207).

[52] From the comparison result of the signal waveforms of the initial test values TS 1 to

TSl to be input to the memory 200 and the initial test values TS 1 to TSl, when it is determined that distortion according to signal delay occurs, the transmitting/receiving controller 110 outputs the control signals CONl to CONl in which the delay values for the delay units DUl to DUl are adjusted.

[53] The delay units DUl to DUl delay the initial test values TSl to and TSl according to the adjusted delay values and output the delayed initial test values TS 1 to TSl to the

memory 200 through the data buses DB 1 to DBl. Then, the transmitting/receiving controller 110 reads the initial test values TSl to and TSl stored in the memory 200 and compares the read initial test values TS 1 to TSl with the initial test values TS 1 to TSl stored therein.

[54] The transmitting/receiving controller 110 repeats this operation, and stores the delay value groups for the plurality of delay units DUl to and DUl and the comparison result. Then, the transmitting/receiving controller 110 determines, among the delay value groups, an optimum delay value group when the delay time between the initial test values TSl to TSl stored therein and the initial test values TSl to TSl stored in the memory 200 has a minimum value (S209).

[55] The transmitting/receiving controller 110 sets the delay values of the optimum delay value group as the final delay values and transmits the set final delay values to the delay units DUl to DUl, respectively.

[56] The final delay values may be set to be different according to the delay units DUl to

DUl. At this time, the operation of delay units having a large signal difference among the plurality of delay units DUl to DUl may be restricted.

[57] The delay values are much smaller than the cycle of a clock signal for data transmission, which is used to output data to the data buses DB 1 to DBl.

[58] Next, the plurality of delay units DUl to DUl set the final delay values, delay the transmission signals DATl to DATl from the multiplexers MUXl to MUXl for a predetermined time, and output the delayed transmission signals to the data buses DB 1 to DB1 (S211).

[59] In this way, by adjusting the delay values of the individual delay units DUl to DUl, it is possible to actively compensate the arrival time delay at the memory 200 due to the data buses DBl to DBl.

[60] In addition, the delay values for compensating the signal delay can be set for the delay units DUl to DUl, while various data bit patterns can be applied according to the transmission signals DATl to DATl.

[61] The embodiment of the present invention described above is not be implemented by only the method and apparatus, but it may be implemented by a program for executing the functions corresponding to the configuration of the exemplary embodiment of the present invention or a recording medium having recorded thereon the program. These implementations can be realized by the ordinarily skilled person in the art from the description of the above-described exemplary embodiment.

[62] While this invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit

and scope of the appended claims.