Title:
SIGNAL-UNDER-TEST ANALYZING DEVICE
Document Type and Number:
WIPO Patent Application WO/2007/114206
Kind Code:
A1
Abstract:
It is possible to provide a signal-under-test analyzing device capable of identifying a test pattern having a high error ratio or a test pattern causing a bit error easily as compared in the prior art. The signal-under-test analyzing device (4) for analyzing a signal under test and causing a display device (21) to display the analysis result includes a test signal generation device having: an analysis result statistical unit (34) for statistically processing the analysis result for each division obtained by dividing the analysis section set for the signal under test; and a display control unit (23) causing the display device (21) to display the statistical result obtained by the analysis result statistical unit (34) for each of divisions. When a division is specified as a new analysis section, the analysis result statistical unit (34) statistically processes an analysis result of the signal under test for each new division obtained by dividing the new analysis section and the display control unit (23) causes the display device (21) to display the statistical result obtained by the analysis result statistical unit (34) for each new division.
Inventors:
WADA TAKESHI
IMAZEKI HAJIME
MIYAMOTO TAKASHI
IMAZEKI HAJIME
MIYAMOTO TAKASHI
Application Number:
PCT/JP2007/056769
Publication Date:
October 11, 2007
Filing Date:
March 29, 2007
Export Citation:
Assignee:
ANRITSU CORP (JP)
WADA TAKESHI
IMAZEKI HAJIME
MIYAMOTO TAKASHI
WADA TAKESHI
IMAZEKI HAJIME
MIYAMOTO TAKASHI
International Classes:
G01R31/319; G06F11/22
Foreign References:
| JP2004128981A | 2004-04-22 | |||
| JPH07218603A | 1995-08-18 | |||
| JPH08279839A | 1996-10-22 | |||
| JP2001111531A | 2001-04-20 |
Attorney, Agent or Firm:
ARIGA, Gunichiro (2-4-9 Yoyogi, Shibuya-ku, Tokyo 53, JP)
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