CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of Provisional Application No. 60/684,290, filed May 25, 2005, herein incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention.

[0002] The invention relates generally to Micro-Electro-Mechanical Systems

(MEMS). More particularly, the invention relates to a method for parasitic capacitance reduction in bulk MEMS accelerometers and other MEMS devices.

2. Description of Related Art.

[0003] Micro-Electro-Mechanical Systems (MEMS) is the integration of mechanical elements, sensors, actuators, and electronics on a common silicon substrate through microfabrication technology. The electronics in a MEMS device are fabricated using Integrated Circuit (IC) technology (CMOS, Bipolar, or BICMOS processes), while the micromechanical components are fabricated using "micromachining" techniques that selectively etch away or add new layers to the silicon wafer to form mechanical and electromechanical devices.

[0004] MEMS devices are widely used in automotives, navigation systems, chemical and biological sensors, microoptics, accelerometers, pressure sensors and other devices. A common approach to fabrication of MEMS devices is the so-called bulk MEMS process. This process consists of processing two or three silicon wafers with patterns machined by Deep Reactive Ion Etching (DRIE) to form the structure used in

each layer, and then bonding these. layers together by a process called direct bonding to form the device.

[0005] An example of a particular MEMS structure is the Silicon Accelerometer

(SiAC™) sensor 100, shown in FIG. 1. This structure is fabricated from two silicon- on-insulator (SOI) wafers and one prime silicon wafer. The SOI wafers provide the covers, electrodes and guards, while the prime wafer provides the Proof Mass (PM) layer. The electrodes are positioned parallel to one another to form a capacitor in between. During operation, the capacitance is used to determine the gap between the paddle and each electrode. An electronic circuit supplies the proper voltage pulses to force the paddle to null, defined as the paddle position where both capacitances are equal.

[0006] The electronics defines the null as the position of the paddle where both capacitances are equal. If the sensor 100, with top and bottom capacitances equal, distorts in any way such that the paddle hinges bend, a bias error will occur. The magnitude of the error will depend on the amount of hinge bending and the hinge spring rate.

[0007] Since the sensor 100 has silicon and silicon dioxide elements with different thermal coefficient of expansion (CTE), the sensor 100 can distort when it is subjected to a change in temperature. This distortion is accentuated due to the asymmetric staircase design of the sensor 100. The distortion can also result from the prior art fabrication method, for example, the sensor 100 is mounted, during assembly, on a ceramic carrier with a different CTE than silicon.

[0008] With an increasing demand for improved MEMS devices, there remains a continuing need in the art for a silicon accelerometer chip design for size and thermal distortion reduction and process simplification.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The exact nature of this invention, as well as the objects and advantages thereof, will become readily apparent from consideration of the following specification in conjunction with the accompanying drawings in which like reference numerals designate like parts throughout the figures thereof and wherein:

[0010] FIG. 1 is a perspective view of a prior art silicon accelerometer sensor mounted to a carrier.

[0011] FIG. 2 is a perspective view of a silicon accelerometer sensor before assembly to the carrier.

[0012] FIG. 3 is an exploded view of the silicon accelerometer sensor of FIG. 2.

[0013] FIG. 4 is a top view of the silicon accelerometer sensor of FIG. 2.

[0014] FIG. 5 is a front view of the silicon accelerometer sensor of FIG. 2.

[0015] FIG. 6 is a side view of the silicon accelerometer sensor of FIG. 2.

[0016] FIG. 7 is a perspective view of a silicon accelerometer sensor, according to one embodiment of the invention.

[0017] FIG. 8 is an exploded view of a silicon accelerometer sensor of FIG. 7, according to one embodiment of the present invention.

[0018] FIG. 9 is a top view of the silicon accelerometer sensor of FIG. 7, according to one embodiment of the present invention.

[0019] FIG. 10 is a front view of the silicon accelerometer sensor of FIG. 7, according to one embodiment of the present invention. [0020] FIG. 11 is a side view of the silicon accelerometer sensor of FIG. 7, according to one embodiment of the present invention.

SUMMARY OF THE INVENTION

[0021] A silicon accelerometer sensor configured for thermal distortion reduction, having a first outside layer, a first guard layer, a proof mass layer, a second guard layer and a second outside layer. The first outside layer having a first cutout from one side of the first outside layer at substantially the center of the side, and the first guard layer is stacked underneath the first outside layer having a second cutout from one side of the first guard layer at substantially the center of the side and positioned below the first cutout, the second cutout being smaller than the first cutout. The proof mass layer is stacked underneath the first guard layer. The second guard layer stacked underneath the proof mass layer, the second guard layer having a third cutout from one side of the second guard layer at substantially the center of the side and positioned below the first cutout and the second cutout, and the a second outside layer below the second guard layer, the second outside layer having a fourth cutout from substantially the center of one side of the second outside layer and positioned vertically below the first cutout, the second cutout and the third cutout. The first and second cutouts have sloping edges for facilitating uninterrupted deposition of metal contacts.

[0022] In one embodiment, the silicon accelerometer sensor has a first metal contact extending from the top surface of the first outside layer through the first cutout to the

top surface of the first guard layer. A second metal contact extending from the bottom surface of the second outside layer through the fourth cutout to the bottom surface of the second guard layer. A third metal contact on the top surface of the proof mass layer below the second cutout of the first guard layer.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0023] FIG. 2 is a perspective view of a prior art silicon accelerometer sensor 200 before assembly mounted to a carrier. The sensor 200 has a first outside layer 210, a second outside layer 215, a first guard layer 220, a second guard layer 225, and a proof mass layer 230. The proof mass layer 230 is sandwiched between the first and second guard layers 220 and 225, which are sandwiched between the first and second outside layers 210 and 215. The sensor 200 also has a via 235 to facilitate a path or opening for circuit shorting. The sensor 200 is fabricated from two silicon-on- insulator (SOI) wafers and one prime silicon wafer. A first SOI wafer 212 contains the first outside layer 210 and the first guard layer 220, while the second SOI wafer 222 contains the second outside layer 215 and a second guard layer 225. The prime silicon wafer provides the proof mass layer 230.

[0024] On the surface of each wafer layer 210-230 is a layer of oxide, typically

1 micron thick. When the layers 220-230 are bonded together, a 2 micron layer of oxide is formed between the guard layers 220 and 225 and the proof mass layer 230. Similarly, a 2 micron layer of oxide is formed between the guard layers 220 and 225 and the outside layers 210 and 215, respectively.

[0025] One technique to bond the SOI wafers to the proof mass layer 230 is by a process called direct bonding. As shown in FIG. 5, a first SOI wafer 212 containing

the first outside layer 210 and the first guard layer 220 is bonded to one side of the proof mass layer 230 and a second SOI wafer 222 containing the second outside layer 215 and the first guard layer 225 is bonded to the other side of the proof mass layer 230. Before bonding, the SOI wafers 212 or 222 and the proof mass layer 230 are preferably cleaned and activated. Activation is done by either chemical or plasma surface activation. The SOI wafers 212 or 222 and the proof mass layer 230 are properly aligned and then each SOI wafer 212 or 222 is coupled to one side of the proof mass layer 230. Van Der Waals forces will cause the SOI wafers 212 or 222 and the proof mass layer 230 to bond to each other. Since the Van Der Waals forces are relatively weak, the SOI wafers 212 or 222 and the proof mass layer 230 may be annealed at an elevated temperature. This temperature depends on the activation process. Older processes used temperatures in excess of 1000°C. With newer plasma processes, 400-700°C may suffice. It can be envisioned that other methods or techniques can be used to bond the layers 210-230 together and achieve the same objective of the present invention. FIG. 3 is an exploded view of the silicon accelerometer sensor 200 of FIG. 2.

The assembly drawing shows the internal components of sensor 200. Contained within the proof mass layer 230 is a proof mass paddle 305 that is coupled to the proof mass layer 230 by silicon hinges 315. On opposite sides of the paddle 305 are electrodes. FIG. 3 shows electrode 310 contained within the guard layer 225. The first guard layer 220 also surrounds an electrode (not shown in the diagram) that is adjacent to the paddle 310 and is parallel to electrode 310. This configuration forms a capacitor between electrode 310 and the paddle 305.

[0027] FIGS. 4, 5 and 6 are the top, front and side views, respectively, of the silicon accelerometer sensor of FIG. 2. FIG. 6 shows electrode 310 contained within the second guard layer 225, while electrode 610 is contained within the first guard layer 220. Electrodes 310 and 610 are parallel to one another and are adjacent to the paddle 305.

[0028] In operation, the capacitance is used to determine the gap between the paddle 305 and each electrode 310 or 610. An electronic circuit supplies the proper voltage pulses to force the paddle 305 to null, defined as the paddle position where both capacitances are equal. If the sensor 200, with top and bottom capacitances equal, distorts in any way such that the paddle hinges 315 bend, a bias error will occur. The magnitude of the error will depend on the amount of hinge bending and the hinge spring rate.

[0029] Since the sensor 200 has silicon and silicon dioxide elements with different thermal coefficient of expansion (CTE), the sensor 200 can distort when it is subjected to a change in temperature. This distortion is accentuated due to the asymmetric staircase design of the sensor 200. The distortion can also result from the prior art fabrication method, for example, the sensor 200 is mounted, during assembly, on a ceramic carrier with a different CTE than silicon.

[0030] FIG. 7 is a perspective view of a silicon accelerometer sensor 700, according to one embodiment of the invention. The sensor 700 has a first outside layer 710, a second Outside layer 715, a first guard layer 720, a second guard layer 725, and a proof mass layer 730. The proof mass layer 730 is sandwiched between the first and second guard layers 720 and 725, which are sandwiched between the first and second

outside layers 710 and 715. The sensor 700 also has a via 735 to facilitate a path or opening for circuit contact to the electrodes. The sensor 700 is fabricated from two silicon-on-insulator (SOI) wafers and one prime silicon wafer. As shown in FIG. 10, a first SOI wafer 712 contains the first outside layer 710 and the first guard layer 720, while a second SOI wafer 722 contains the second outside layer 715 and the second guard layer 725. The prime silicon wafer provides the proof mass layer 730.

[0031] The sensor 700 has symmetric contact pads 740 for electrical contact between the outside layers 710 and 715 and the guard layers 720 and 725. The contact pads 740 can be formed by depositing metal on the first and second outside layers 710 and 715, and the first and second guard layers 720 and 725. The metal can be deposited by an electron beam that is highly directional. The first and second outside layers 710 and 715 have sloping edges 745 that allow the metal contact pads 740 to connect the first and second outside layers 710 and 715 to the first and second guard layers 720 and 725, respectively, without having a vertical wall that interrupts the metal deposition process.

[0032] FIG. 8 is an exploded view of the silicon accelerometer sensor 700 of FIG. 7, according to one embodiment of the present invention. The exploded view shows the internal components of sensor 700 after the entire assembly is completed. Contained within the proof mass layer 730 is a proof mass paddle 805 that is coupled to the proof mass layer 730 by silicon hinges 815. On opposite sides of the paddle 805 are electrodes. FIGS. 5 shows electrode 810 contained within the second guard layer 725. The first guard layer 720 also surrounds an electrode (not shown in the diagram)

that is adjacent to the paddle 710 and is parallel to electrode 810. This configuration forms a capacitor between electrode 810 and the paddle 805.

[0033] FIGS. 9, 10 and 11 are the top, front and side views, respectively, of the silicon accelerometer sensor 700 of FIG. 7, according to one embodiment of the present invention. FIG. 11 shows electrode 810 contained within the second guard layer 725, while electrode 830 is contained within the first guard layer 720. Electrodes 810 and 830 are parallel to one another and are adjacent to the paddle 805.

[0034] According to one embodiment of the invention, the dimensions of sensor 700 are reduced by decreasing the unused space of the prior art internal cavity 320 between the hinges 315 of FIG. 3. This provides additional contact between the outside layers 710 and 715 and the guard layers 720 and 725, as well as contact to the proof mass layer 730, while preserving an adequate bond area. The utilization of a smaller internal cavity 820 reduces the size of sensor 700 from 5x6 mm to 5x5 mm.

[0035] Only minor changes in processing are required for the manufacture of the invention. In one embodiment of the invention, the sensor 700 is manufactured by using the standard series of fabrication techniques. The first SOI wafer 712 and the second SOI wafer 722 can be identically processed. Therefore only the processing of the first SOI wafer 712 will be described. First, the first outside layer 710 is coated with a photoresist, and by photolithography, openings are defined for the via 735 and the cutout 750. In one embodiment, the first SOI wafer 712 is etched by a modified DRIE recipe that produces sloping sidewalls with approximately a 45 degree slope. The outside layer 710 is etched all the way through to the SOI oxide.

[0036] Next, the first SOI wafer 712 is oxidized to produce 1 micron of oxide on the surfaces of the first outside layer 710, the first guard layer 720 and the walls of the via 735 and the cutout 750, Both, the first outside layer 710 and the first guard layer 720 are coated with photoresist. Spray resist will facilitate the uniformity of resist on the previously etched first outside layer 710. By photolithography, an opening is made in the photoresist which defines the trench around the electrode 830 and cavity within the first guard layer 720. This region is etched out, down to the SOI oxide, by a standard DRIE etch that produces vertical walls. The second SOI wafer 722 is prepared in the same way as the first SOI wafer 712.

[0037] The fabrication technique used to prepare the proof mass layer 730 is similar to the methods used in the prior art; however, the proof mass layer 730 is patterned differently to have a smaller internal cavity 820 that contributes to the reduction of the sensor's size.

[0038] After the first SOI wafer 712 and the second SOI wafer 722 are bonded to the proof mass layer 730, openings are made in the oxide on the various layers in order to make the required electrical contacts. These oxide removal areas are: the SOI oxide in the bottom of the via 735, the oxide under the contacts 755 and 910 for the outside layers 710 and 715 respectively, and the oxide under the contact 740 between the outside layers 710 and 715 and the guard layers 720 and 725, and the oxide under the contact 765 to the proof mass layer. The oxide can be removed by photolithography and chemical etching or by plasma etching.

[0039] After the oxide has been removed, the metal contacts 740, 755, 765 and 910 and traces 760 between contact to the electrode 810 and 830 in the via 735 to the wire

bond pad on outside layers 710 and 715 are deposited by electron beam deposition through a shadow mask. This is done at the wafer level and from both sides of the wafer stack.

[0040] At the end of wafer processing, there will be pads at one end of the sensor 700 for all 5 connections that need to be made. The routing of the electrode wires 105 on top of silicone bumps 110, as shown in FIG. 1, are eliminated and replaced by batch processing at the wafer level. Connections are made by metallization between the outside layers 710 and 715 and their respective guard layers 720 and 715, thereby eliminating two wire bonds 115 and 120 used the prior art sensor 100 of FIG. 1. Three connections are made to the top of the sensor 700, and two connections to the bottom.

[0041] In one embodiment, the sensor 700 is assembled by mounting it to three silicone pads on a ceramic carrier using silicone adhesive. The leads from the top and bottom electrodes are routed across the cover on top of silicone bumps. This is a labor intensive operation. Also there is a flying lead, i.e., a lead that is not wire bonded normally but one end of the wire attached to the chip before it is attached to the ceramic carrier. The other end must then be bonded later.

[0042] One advantage of the present invention is that the manual routing of the two electrode leads 105 on top of silicon bumps 110 is eliminated as well as the two wire bonds 115 and 120 connecting the guards 220 and 225 to the outside layers 210 and 215, respectively. Yield and reliability will be improved because occasionally the long electrode leads 105 from the electrodes 310 short against the outside layers 210 or 215.

Another advantage of the present invention occurs in the DRIE etching of the outside layers 710 and 715. For fabrication of prior art sensor 10O ₅ a large window 1 mm in width, must be opened up in the outside layer 210 for access to the underlying staircase. This is done by etching from both sides down to the SOI oxide, which makes it thin, brittle and can shatter easily. During etching, the back side of the outside layer 210 is cooled by a low pressure of helium. Shattering of the SOI oxide introduces helium into the etching plasma and interferes with the final etching of any lagging areas on the wafer. In addition, the oxide particles, which are 2 microns thick and variable lateral dimension, contaminate the DRIE chamber. According to the present invention, there is a smaller cutout 750, preferably with a dimension of 0.9 mm wide x 1 mm long, versus the longer window of 1 mm wide x 3 mm long for the prior art sensor 100. Therefore, the probability of breaking the SOI oxide will be reduced.