Title:
SILICON-CARBIDE (SIC) METAL-OXIDE-SEMICONDUCTOR FIELD-EFFECT TRANSISTOR (MOSFET) WITH SHORT CIRCUIT PROTECTION
Document Type and Number:
WIPO Patent Application WO/2023/193288
Kind Code:
A1
Abstract:
An integrated MOSFET-JFET device made from a Silicon-Carbide (SiC) wafer has N+ source, P body diode, and upper N regions that form vertical MOSFETs on the sidewalls of polysilicon gates. An N substrate under the upper N region forms a drift region that is pinched by the JFET to limit saturation current. Trenches are formed between MOSFETs. JFETs are formed by doping the bottom and sidewalls of the trenches to form P+ taps to the N substrate. P islands within the N substrate are formed underneath the P+ taps. These P islands are wider near the surface but are successively narrower with increased vertical spacing deeper into the N substrate. This P-island tapering provides a tapered shape to the JFET depletion region that pinches the MOSFET drift region in the N substrate to limit saturation current and yet reduce linear-region ON resistance.
Inventors:
YAU SHU KIN (CN)
MA CHENYUE (CN)
WONG SIU WAI (CN)
MA CHENYUE (CN)
WONG SIU WAI (CN)
Application Number:
PCT/CN2022/086714
Publication Date:
October 12, 2023
Filing Date:
April 13, 2022
Export Citation:
Assignee:
HONG KONG APPLIED SCIENCE & TECH RESEARCH INST CO LTD (CN)
International Classes:
H01L27/02; H01L29/06; H01L27/07; H01L29/78; H01L29/808
Foreign References:
| US20120175699A1 | 2012-07-12 | |||
| CN102420251A | 2012-04-18 | |||
| US20120080748A1 | 2012-04-05 | |||
| CN108511527A | 2018-09-07 | |||
| US20080277695A1 | 2008-11-13 |
Attorney, Agent or Firm:
CHINA TRUER IP (CN)
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