an D ices iscioillBg the Same

BACKGROUND Ο0.Ϊ I Porous silicon, is a form of si l icon material thai has holes (pores 1» small, scales.

According to existing nomenclature, adopted by the international llnio ofPnre and Applied Chemistry (ilJPACk there cm he three categories of pores with regard to the pore dimensions: micropores, mesopores, and &CFopotes with, average pore diameters of less than 2 nm, 2-50 and greater than 50 «m respectively. The pores hi porous silicon can also display various morphologies, i-s. shape, orientation,, alignment, and interconnection of pores, among others. ff §02) Porous silicon is a dielectric material w th applications in a wide range of areas, Previous and ongoin research on the application of porou silieon cau he fouad k among: others, optoelectronics, micro-optics, energy coeversion, eimronmeniai monitoring,

microelectronics, wafer technology, micfomachiamg, and biotechnology,

SUMMARY f:§S§3] finbodlrrsems of the present hrvention include semiconductor systems containing porous silicon layers, methods of manufacturing the sernieondnetor systems, and devices including the semiconductor systems, in one exemplary embodiment, a semiconductor system, includes sil icon substrate nd a porous silicon regio disposed on the silicon substrate. The silicon substrate is doped with a do ant at a concentration rom about errr to about 10··* cm ^{' '} , The silicon sathstrate has a first band gap energy, and the porous silicon region has a second band gap energy greater than the first hand gap energy, lire semiconductor system is coirfigured to exhibit: an electric field o the interlace between the silicon sttbstrate and the poroos silicon region, The electricd1ele< is generated at least partiall by a difference between the first band gap energy and the .s cond, hand gap energy. The porous si Henri region is eouf g red to p&ssivnie a swri ee of the silicon substrate vi , at least ^: partially, an ekctrie f¾ree induced by the electric field on a. minority charge; carrier in the silicon substrate. The electri c force is configured te he at a. direction from the porous silicon region to the silieon substrate so as to sirppress transport of minority charge carriers from the silicon substrate to the porous silico region, thereby increasing a passivaied limtinle of the &of t charge carriers and passivaring the surface of the silicon substrate,

|10Θ4] I» another exemplary embodiment,, a solar cell includes a silicon sid>simie comprising m emitter region n .a front side of the silico substrate and a base regio on a hack side of the silicon substrate, A front side passivation layer is disposed on tbe easitter region. The front side passivation lay er comprises: a first, param silicon region p contact wit tile emitter region and an anlirettectlon and passivation coating disposed on the f ont side passi vation layer, Tbe front side passivation layer and the antirefleetion and passivation layer, respectively or in combination, are configured to rednee reflection loss on the front side of the silicon substrate and increase a minority carrier li fetime of minori ty ch ge carriers in the emitter region. Tire solar eel! also includes a back side passivation layer disposed on the base region. The back side passivation layer comprises a second, porous silicon region, and optionally a back surface field (BSF) laye disposed between the base region and the second porous silicon region.

f In yet another exemplary embodiment a method of facilitating ftthrieation. of a solar cell via a stain etching process using- a junction isola lori phosphosilicate lass (PSG) etch, processing tool starts from: l cing a first stain etching solution In a f rs reservoir coupled t a PSG etch tank in the junction isoIatfon/PSO etch. processing tool throisgh ¾ fes chemical dosing unit of the PSG etch processing tool The method then places at least a portion of a silicon substrate for the solar cell in the PSG etch, task and allows contact, m the PSG etch tank,, between the silico sabslraie and the .first stain etchin solution in the fet reservoir, Chcrnieal reactions between he silicon sohMrate and the first etching sointion _: rempves possible PSG n, a front side of the silicon substrate during: first t ne period, etches hack at least a portion of the fron t side of the silicon ubstrate during a second time period, and passivaies the front side of tbe silicon substrate and reduces a reflection, loss on the front side of the silicon substrate. The passi atio and antirefleetion is achieved, at least partially, by creating a f ont side porons silicon region on the front side of the silicon substrate during a third ime period, in one example, at least a portion of tbe second time period and the third time period is concurrent In another e ple, at least a portion of the first time period, tbe second time period, and the third time period is concurrent. §§MW] It sho ld be ap recia d that ail eombhtations of he foregoing concepts nd additionsl concepts discussed n greater detail below (provided such coiieepts are dot mutually inconsistent) are contemplated as being pari, of the ¼v¾j#ve subject Matter disclosed herein, in particular, all combinations of elaufte subject matter appearing at the end of this disclosure are contemplated as being part, of the inveritive subject matter disclosed herein. It should also be appreciated that terminology explicitl employed herein that also hmy ppear in any disclosure incorporated by reference should be accorded a meaning m i consistent with the particular concepts disclosed herein,

BRIEF DESCRIPTION OF THE DRAWINGS The skilled artisan: will understand that the drawings primarily are for illustrative purposes sad are not intended to limk the scope of the inven tive subject matter described herein. The drawmgs are n t necessarily to scale; i some instances, variou aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features {e.g.,. functionally similar and/or structurally similar elements}.. f 0¾ §j FIG. 1 is a schematic view of a. solar cell including poroos silicon layers on both the front side and the back side.

{008 1 FIGS. 2Λ Β show sinudaied energy band dia ams of semiconducto systems including an n-iype silicon substrate and. a porous silicon, region disposed, o the n~type silicon, substrate.

{ ^• 0010] PIGS ^' . 3 A-3B show simulated energy band diagrams of semiconductor systems including a p-type silicon substrate and a porous silicon region disposed on the p-type silicon substrate. f0011 FIG. 4A show simulated reflectance of a semiconductor system Including a smooth silicon substrate and a porous silleon region on the. sort¾ee.

f 0012} FIG. 48 show simulated reflectance f a semiconductor system including textured silicon substrate and a porous silicon region on the textured surfeee. fitBJ FIG. 5 illustrates a matching between si ulated and measured reflectance of a

11014] FIG, 6 illust ates a method of porous silicon layer f rmation: isskg exisMag ooIs of junction isolation and PSG/BSG eieh,

|00Ι·5| FIG, 7 is a flow chart of an exemplary solar ceil manufacturing proces using existing: tools of junction isolation and PSG/BSG etch.

flii iSj FIGS. &A-8B arc scamriag electron microscopy (SEM) images of two silicon substrates with porous silicon on the surface, ^' Ore two silicon substrates are processed by a first ammmt of etch-back.

WI7| FIGS. 9A-9B are SEM mages of another two silicon substrates with porous silicon on the surface, lire two. silicon substrates are processed by a second amount of etch-back.

108181 FIGS, 10A-1GB are SEM images of another two silicon substrates with porous silicon on the surface. Th two silicon substrates are processed by a. third amount of etch-back.

[m ] FIGS, 1 1 A-i IB are SEM images of another two silicon siibsttates with porous silicon on the surface. The two silicon substrates are processed by a. fourth amount of etch-back,

10020] FK1S, :!2A~12D are SEM images of two porous silicon sample fabricated by a stain etching solution Including a surfactant,

i i] FIG , L3A i a photo of a solar ceil without any etch-back on the iront side.

|0022| FIG. 13B is a photo of a solar cell with a posmrs silicon region created by a stain etching solution on the front surface,

|; 023| FIG. I3C is.a photo of a solar cell with an etch-back performed by a Η /θΜΜ

solution,

{102 ! FIGS. 14A and. I4B arc measured short circuit currents t _Si and fill factors (FF} _> respectively, of the three solar cells shown in FIGS, 13A~!3C.

{1025| FI G . 15: is measurement of contact resistance n the front side of the solar cells shown in FiGS, I3A- C. HO. .1 <5A is a measurenientof reverse saturation cunt i density of solar cells shown in FIGS:. I3A-13C.

110271 FIG. .16B ¾-¾ measurement of impl ed op circuit voltages of solar eelfe shown in FIGS. I3A-I3C.

\≠2%\ FIB, :16C is a measurement of iiferates oi t ceils shown la FIGS, 13A-130.-

|θ§59 j FK3S. Ϊ 7A-I7B show comparison of peribnsanees of solar ceils including pot&m silicon layers fabricated by a HF-Nitrie solution id by a BP-rlCI rotation.

im ] FIGS. 18A~1.SC are S ^' E image* of porous silfeon. created by a BP~ itrlo solut n. flM I I FIGS . 19A-I9B show open, circuit voltages of sola ceils that include porous silicon regions and ate processed at different firing conditions.

f IMKi&j FI S. 20A-20D show perfimnanees of solar cells that incksde porous silicon, layers and ate processed under different -firing temperatures.

f ^' 06331 FIG, 2.1 Is a table summarizing per btrnanees of solar cells with different nseiai pastes, processed under 4iffere$$i firing conditions, and with different antirefieeiion and passivation coatings.

iff §34] FIGS . 22A-22C show implied open circuit voltages of solar cells includin porous silicon .regions before M\d after tllernia! tiring t.reaP¾entS,

fW3 j FIG . 23 shows irnplted open circuit voltages of solar ceils with and withou a _; silicon nitride layer deposited, y plasma enhanced chetnieai vapor deposition (P1CVD) techniques. f ¾§36| FIGS. 24A -24 sho implied open circuit vol tages of solar cells includin porous silicon layer fabricated by etching solutions Including: dli%rent percentages of HP and snrf»et»nt,

§037] FIG.2$. shows averaged, implied: vol ages of solar cells including porous silicon layers fabricated by etching solutions including different percentages of BF and surfactant. DEX LED DESCRI PTION

[0638 Introduction fiMBf) Porous silicon, can. be a promising . ^' .materia ! due to ds mechanical, arid thermal properties, coninaiihility with silicon-based microeketonics, an low cost. For example, porous silicon can. have efficient leefeiumhvesceneo that: can find applications is LED li ht .sources. Porous silicon can also have tuna le .refractive index, whic is desirable in itibricating waveguides nd Fabry-Perot filter. The nearly periodic array of pores in porous silicon ears ¼lidaie fabrication of photonic barsdgap simetures, or photonic crystals, Porous silicon can also be utilised In optica! fxi a y- and all optical switching due to its: non-linear properties. Gas sensing and biosensors can also benefit from porons silicon since die micro-scale structures within porous silicon allows ambient sensitivity properties and enz me immobilization. Other applications of porous silicon include anti-reflection coating, micro-capacitors, insulator layer, low index material, SO! wafers, and thick sacrificial layers, atnong others, f 0040 j At least two methods can be employed to create pores in silico substrates or wafers and ^' fabricate porous silicon. One method of introducing pores in silicon can use an an te tion ceil, in which, a platinum cathode and a silicon wafer anode can be immersed in hydrogen fluoride (HF) electrolyte. Alternatively, inert diamond, can als be used as the cathode materia! to avoid. metallic impurities in the electrolyte md to forts a mp o ed electrical back plate contact to the silicon wafers. Porous silicon is this method can be produced through,

electrochemical reactions. On the piadnnrn. cathode, the chemical reaction can be 2H ¾ο ^" - · H _¾ , while on the silicon: anode (also referred: to as silicon workin electrode), the chemical reaction ears he S^ M ^{" ;} 21 Γ - 2h Si ^' : l b.

|0041| A. second method to- produce porous silicon: can he through siain-etching with, hydrofluoric acid (HI?), nitric acid (MNQj) and. wafer $¾0} _s -A- possible process that leads to the formation of porous silicon, can. be that oxidation of silicon atoms occurs by hole injection from, nitric acid an simultaneously the reduction of silicon atoms produces NO and water. Silicon oxide can react with HE. forming water-soluble complex, Metal ions can be added into the solution to produce poroos silicon of different properties. For example, when mixed with HF( _s¾j , Fe ^3' \ Co* ^' , and VCT ^":' can produce uniform layers of porous silicon with thicknesses up to 20 urn. PfM2] Application ₀ f Porous Silicon ife Sola Cells

|0§43| Silicon-based solar cells can be su ject: to a variety of losses, which can s turn reduce the conversion efficiency torn solar energy C electrical energy. Possible losses Ineltsde, among others, recombination losses, series resistance losses _* thermal losses, metai-setrheondnctor contact losses, and reflection losses.

{0844] itee Bibitmi if i losses cm occur m multiple regions of a solar cell, .including the cell, surface, the bulk of the cell, the depletion region., and the ineial/seniiconducior contact The Incomplete chemical . onds on die surface of semiconductor (or anywhere else) can trap the photo-excited carriers via reedmbiitatioii and therefore cause reduction oa photoeurreat Without being bound by any particular theory or mode of ope ation _s recombination losses can be characterized by the surface recombination velocity which can be expressed as;

where σ and y are capt re cross section and thermal velocity of carriers, respectively, and Λ Is the number of , surface traps (incomplete chemical bonds}..

|¾045] Reducing ^combin ti n losses cm the cell surface can be achieved by reducing the surface recombination velocity. One m t od to reduce sorfaee recombination veloeity is depositing a thin passivatio films on to the cell surface. For example, Sii¾ or SiN. films ea» be deposited, via chemical vapor deposition (CVD), plasma enhance chemical vapor deposition (PEGVD) or thermal oxidation tee mcjU% to reduce the surface recombination veloeity.

|0646| Impurities and crystalline defects, in _. bulk regio of semiconductor can also induce recombination losses , deduction of concentration of rest Impurities: in bulk of semiconductor, according to Sehoeke and Read model, may decrease the recombination veloeity. Using semieonductor material, wit lower eoncenfi-auon. of imparities and delects can. accordingly increase the diffusion length of minority carriers, thereby reducing the reeombmaiion losses In bulk; of solar cells,

1 41 \ Series resistance of a solar ceil can originate from several ditlereni regions in. the solar cell, such as the top grid* the busbar, the emitter, the hulk of the semiconductor,, and/or the contact betwee the metal electrode attd the semiconductor, Each region can contribute its own resistance to the total series resistance of the entire sola cell. Reducing the series esistance can foe achi v d by, for e ample, c ^' hoosiag materials of io T&^i vKy, or &4j« ag the doping eoiiceri ratioii in the emi ter tegiod, and the depth of the p-n junction,

{90 8 j Thenhal osses u . a solar cell can foe a si ^' ifead.less e anftel ih. photovoltaic solar ceils; Sunlight .incident o« a solar includes components with different wavelengths, or photos, energies. Some components have a photos energy greater t an the band gap energy of the semiconductor material. When the solar coil absorbs these photons, ik excess energy (he. energy difierefit bet een the photon »esf¾y and the hand gap energy) is »e«ftal!y converted into heat, Instead of electrical eaei¾y, thereby inducing losses, Moreover, the generated heat can also lead to an increase of intrinsic ..carrier concentration and diffus n lengt ef minority carriers,, both of which can increase the reverse saturation current - T e: le vel of reverse saturation current can he related the leakage of carriers across the p-n junction under reverse bias.

Therefore, increased reverse saturation current typically induces lower open circuit voltage, 00 ] Metaf-semieondue or contact losses normally occur on the frontal and back surfaces of solar cells, Screen-printed, technique is often used for depositing metall contacts to silicon solar cells. The front contact typically includes a fine grid and the back contact can he a metal, plate covering the entire back surt ee of the cell , Ag and Ag~A.I astes are used in conventional silicon solar cells. Reduction of metal~set»ioenduotor rcsistartce can address the losses at the metal-semieonduetor Interface. For exam le, introducing acceptor type impurity in m contact can result in decreas of the resistance of near-back eoutaef region, of p-iype silicon sufosirate due to -.d ffus on penetration of alwuiuum during thernuii treatment. In auothcr exaro ic, eavy doping can .form, a near-surface electdc field that can reduce the reco bination losses at the metal-semiconductor contact

fu S§] Reflection losses can he another significant source of losses in solar cells. Texturing and autlrefleetion coating (ARC) can he applied to decrease the reflectance on the ceil surface. The texturing technique, in general, intmdnees miemrneier-scale tilted pyramid structure to the silicon surface, which can facilitate trapping the incident sunlight b reducing: the amount of sunlight that is directly reflected by an otherwise smooth surface. The pytani .structure can be formed foy etching the surface with acid (ββ® ₄ , HNCh¾0 etc.) or with alkaline etch fNaOB, KOB etc.)- |ί§5ί 1 la antiteflectlon coating (ARC) ischtriqu s, -one or more frrin and transparent fi ^' hfts made of materials with refractive i eji in) between those of air and silicon -- 3 ,4) are deposited on the solar cell surface thai receives the s oii girt. ARC can reduce the Fresad reflection, hiebnotmally occurs when light propagates, ιφοη interface between materials of two different refractive indices (e.g. the air-semleondnetor surface),

f C!§S2| T e stratified Medium theory: and Brnggeman effective medium approximatkm an be e plo ed when taliricat dig ¾i≥ ARC. Without being b u d b any particularly theory or mode of operators, the zero-retlecnon. for normal Incidence of light on. AR /Si system, can. be given by; n _m < - _{i :} v«.v)½

where n _f> and n$< are the rsfractive indices of the antireflection coating, the am ient media (air) and silicon, respeetively.

| ftS | For a given wavelength λ, the thickness .(<:£» ) of the single-layer ARC ca be:

,·;<· ^■ (4n _<:y; ) (3)

According to e uation (2) and 0), for typical solar cells (a _» ~ 3 _s %* 3.4), one choice of the refractive kdex and thickness of the ARC can be (for A ^::;: 6$0 nm) n^ " 1.96 and 4m-tr%$ »m.

|#§54| Two or more layers of ARC can be deposited on. the solar cell surface to farther reduce the reflection loss. Take a two-layer ARC system for example, thc isero-retleetanee at normal Incident angle can be achieved by :

¾ ^» (?«¾ % and (d)

wbere and are refractive index of top and bottom layers, respectively, of the two-layer ARC. According to equation (4), one design of a two-layer ARC can be 1.57 and ~ 2.46. la practice; ARC can be deposited by oltemieal v or deposition (CV ^' D), plasnva- enhanced chemical deposition (RBC VD), o thermal . oxidatio processes, which are normally carried out at high temperatures. High temperatures may Induce high cost and potential damage to the solar cells.

f 0&S6j The above mentioned losses (recombinatio losses, series resistance loses, thermal losses, roetai-semicondnctor contact losses, and reflection losses) ca be addressed, at least pai ially, by nsing porous silicon in solar ceils.. First, the process of creating porous silicon through BF acid can have a getteririg (moving contaminants and/or defects in semiconductor

number of dangling s lic n bonds at the top surfa e) effect ou thesliicon material, thereby reducin surface recombination velocity of the resu ting solar cel l

|00S7j Second, porous s. ^' H ©/« cm have a tunahle band; ga energy, which can improve the cotnpatibllity with metal electrode on the fo t a»d back sorface of solar cells. On. the interface of metal and seffilcondoetor, there typically has a potential energy barrier, referred to s a Scbottky barrier, which, can. be ind uced by the mismatch between the work function of the metal •material and the electron affinity of the semicondiictor material, hi operation, Sehottky barriers can block charge flow across die metahsetnieondnctor interface, thereby imposing limitations en performance of the semiconductor devices a¾d device systems based on them. The tuaabk band gap energy of porous silicon may allow the reduction of the Schottk barrier height and accordingly the metai-scrmeondwetor contact losses.

fWSSj The tunable band gap energy of porous silicon can also reduce thermal losses. To be more specific^ the porous silicon can be fabricated to Imve a larger energy gap than, conventional silicon. The enlarged band gap can raise the threshold of heat generation hecaitse photons In the sunlight now need a: higher energy I orde to overcome the enlarged nd ga and generate heat based on the excess energy {difference between the photon energy and the band gap energy), in other ds, porous silicon, can. facilitate more effective absorption of photons _s particularly &e shorter wavelength components (higher frequency components and higher photon, energy part) of the sursilg with reduced heat generation..

f 005? j Third, porous silicon can be ased as the an iireil action coating to rednee reflection losses, Compared tO; conventional silicon, (i.e., substrate silicon), poroos silicon can have a lower refractive index. Without being bound by any- theory or modeof operation, poroos silicon ean be viewed as a mixture of silicon, and air (or any other material filled in. the poffis). Therefore, retractive index of porons silicon is typically between nnity (refractive index of ah) and 3.4 (refractive index of silicon substrate) - potentially useful as ARC: material,

08 1 Moreover, the refractive index of porous silicon can e dependent on the porosity. In general, higher porosity can lead to lower ret active index. And porosity of a porons silicon laye can be dependent on, for ex mple, the etching time. Therefore, a porous silicon, film created by etching a silicon surface can have- a gradient of reifaeiive Iftdex along the depth. Deeper regions can have a larger refractive index because d e etching p oc ss norm lly starts fm . tire top surface and reaches the deeper e n afte etching ibe shallower regions, in other wo ds deeper regions cm be exposed to the etching process for a shorter ii¾c, resulttag in lower ponasity and. accordingly higher refractive index. The gradient of refractive index can be approximately regarded as a multi-layer aniireBection costing, allowing: reduction of reflection losses in solar cells,

s&tj la- addition, porous silicon films ears fhtiher reduce refleci n losses due to tire porons structure. Com a ed to a smooth silicon substrate that can. directly reflect back incident lights, porous silicon films cm more effectively trap the incident lights hy inteluefng longer optical path tor incident lights. More specifically, the porous or uneven surface can deflect the aieideat light on various directions, and some of the deflected light can reach another portion of the porous surface and have second chance to be absorbed,

f §062] Fourth, porous silicon can be created fr m conventional silicon substrates. Therefore, the preparation of porous silicon films can take advantage of existing fabrication technologies i semicon uctor- industry , thereby reducing: costs associated with, tor example, deposition of antiref!ectiou coating and passivation coating, among others,

f «63 j Exemplary Structures of Solar Cells iaetat!teg Porous ilic n

|0O | FKi I shows a schematic view of a s&lar ceil including a parou silicon layer according to one exemplary embodiment. The solar cell HID includes an- u-type phosphorous emitter region 130 on the feat side (or top side),. a p-type base region 140 m the back side (bottom side), in peration, the front side of the solar cell 1(1) is toward. Incident radiation, whic can. be direct solar radiation, reemlitetl radiation from, a selective emitter as in a solar thermophotovoliale (STPV) system, thermal, radishou ¾ a heating source, or any other radiation, that can e absorbed and converted kto _: electricity by fe _: solar cell 100, In one example, both the front side and tire back side cm be doped so as o construct bifacial or hetetosiructure solar cells. Doping material may include phosphorous, aluminum, boron or gallium, and the doping corscentration can he about |0 ^> em ^" to about 10 ^Ai c "\

(0865 On the surface of the emitter region 130 disposes a front side porous silicon layer 120. Since porous silicon can he created directly from, silicon substrates vis stain etching of

it eleetroehemieai reactions, t¾e boundary or interface between the emitter region .130 and the front side porous silico layer 120 eaa be blurred. In oiher words, the transition ^' from the emitter region 130 to the from side porous silicon layer 120 region can be gradual An an irerleetion and passivation layer 1 10 is disposed on the surface of t e front side porous silicon layer 120 to improve the anti-reflection property of ih& emitter surfece aftd fttrtbef rednce refiectlon: losses. The ainrireftectioa nd. pass va ion layer oan also increase the lifetime of minority charge carriers in the emitter region 130 by reducing the number of defects states near the surface of the emitter region 1.30.

f The antirefeetioo and passivation layer 1 10 normally comprises dielectric materials, in one example, the amirefection and passivation layer 110 comprises silicon oxide (eg,, Sit¾, whieli can be grown by a thermal oxidation process or a room temperatnrc wet chemical growth (RTWCG) method, among others, in another example, the ^reflec ion and passivation layer comprises aluminem oxide (eg. _s A½0.?) _> which, can. be deposited via,†¾r example, atomic layer deposition (ALO) techniques. In yet another example, the autiref!eeiion and passivation layer comprises silicon, nitride (SiNxj, which can he deposited via, for example, plasma enhanced chem cal vapor deposition (PECVD) technique or other techniques known in the art. A. plurality of froni side metal contacts or fingers (not shown) can be printed over the antirefleetion and passivation layer 1.1.0 but penciraie ihrough both the anrireflection and passivation layer 11.0 and the front: side porous silicon layer 120 to reaeh tip emitter region 130 so as to conduct the electricit ou t of the solar eel! for utilities.

The front surface of the solar cell 100 can be either smooth or textured (not shown here). In operation, textured surface with., for example, ndom pyramid can. increase absorption due to the increased surface area and decreased chance of light being directly reflected away from the surface. The textures ears be erealed either on the surfaee of the semiconductor snbstrate (e.g., the emitter region) via KOH etching, or o the surface of the antirefleetion and passivation layer 1 Hi, In operation, the latter c s result in a smaller sheet resistance and therefore increase the efficiency of the solar ceil.

W>8j The fron surface of the solar cell 100 can also be treated by an etch-back process. Emitter etch-back is typicall a process that partially removes tile emitter layer on the silicon wafer so as to optimize dopant surface concentration (e.g., removing heavily doped surface layers, known as "surface; dead layers", or d pant depleted or tick regions that occur in. boron dif1¾sion>, Etch-baefe also allows the formation of high h§^^i^c#^i» f mm a tow sheet: res stance precursor emitter in, for example, the formation of either ^' homogenous or selective emitters. i¾ the ease of selective emitters, the e eh-back is typically .m sked to produce selective etching 10 result M patterning of the sheet resistance of the emitter. Emitter etch-baek can be achieved; using solutions such -as hydrofluoric 'nitric acid (BF-H ^' N<¾)>

|«069| OH the back side of the solar mil disposes an optional back surface field (BSF) layer 1.50, o which a back side porous silicon layer 160 is disposed. A back contact 170 is electricall coupled to the optional BSF layer 150, In situations where the BSF layer 150; is not included in the solar cell 1 ^' 0O, the back contact 170 can ^" be configured to be in direc electrical eoatset with the base region 140. M operation, the BSF layer 150 can reduce t he Impact of rear sur ace (back surface) recombination velocity on voltage and current if the rear surface is closer than a diffusion length to the junction.. The BSF layer I SO can include a higher doped region at the rear surface of the base region 140. The interface between the BSF layer 150 and the base region. 1 0 m behave like a p~n junction, creating an electric field at the interface, The electric field can introduce a barrier to minority carrier flow to the rear surface, thereby maintaining, the minority carrier concentration at higher levels in the bulk of the device. Therefore, the BSF layer 150 can. realize- a net effect of psssivatmg the rear surface,

£0878] The back side of the solar eel! i AO can further include a back side passivaiimi la er (not sbowrf) disposed;, for example, between the hack side porous silicon layer !dO an the back contact 170, the back, side passivadoo, layer can . e m ade of silico oxide and can. be patterned to have at least one aperture so as to allow the back e niaet 170 to reach the BSF layer iSO or the base region 340. The pattern can be created ei her during the growth of the hack side; passivation layer or after. Fo example, a patterned mask that i resistive foot reactive) to the means of growing the passivation layer can be placed ove BSF laye 150, such that the back side passivatio layer Is created onl in selected locations. Alternati vely, a uniform passivation layer can be created first. Then ode or more apertures can be opened by, for example, lasers* etching chemicals, mechanics! drills, or other means known in the art,

10871] The passivation effect of the back side passi vation laye can be replaced or reinforced by the back side porous silicon layer io0. If there is ue back side passivation layer, the back side

B porous silicon layer 160 can fee disposed between the BSF layer 150 and the: back contact 170. If there is aback side paas vai on layer, the back side porous silicon, layer can be disposed between .the. BSF layer 150 and the optional back side passivation layer.

10072] In operation, the front side porous silicon .layer ^' 120: can fulfill sevens I purposes, In one esample, the front sid porous silicon, layer 120 c n passivate the surface of the: emitter region 130 via a field effect induced by enlarged: band gap energy iiee, e.g. FIGS. 2Λ-2Β). Without being bound by particular theory or mode of operation, the baud ga energy of porous silicon ears be dependen on the porosity of the porous silicon. Porosity of the front side porous silicon layer can be about 25% o about 95%, or about 25% to about 65 , or about 35% to about 55%.

|0β73| The passivation effect may also be influenced by the thickness of the front side porous silicon layer 120, Practical ranges of thickness of the trout side porons silicon layer 120 can he, tor example, -from about 8 am to about 30 nm, or about 5 ora to about 20 am, or about 7 am to about 15 fiffi. A fter passivation, the lifetime of minority charge carriers in the emitter region 130 can be about 10 rnieroseconds to abou 1 00 mierosecotuis:, about 50 microseconds to about 500 microseconds, or about 100 icroseconds to about 300 microseconds.

10074 ^' } The size of pores in the front side andtot back side porous si licon l ay er can be, tor example, about 2 nra to about 5 nm, lu one example, the front side and/or back side porous layer can have a substantially unlformsfee :fer nearly ail the pores i the layer, hi another examp , the: ias of om in the porous silicon layers can be different at difterenf locations within the porous silicon layers e.g. _s larger pores closer to. the surface and smaller pores deeper inside the layer),

f;0.075} to the porosity, the surface of the porous silicon layers Is not ideally smooth, at leas front a rnkto-sieale perspecti ve. Therefore, the porosity may replaee or supplement the sur&ce textures for liglrt trapping,

10876] Alternatively or inadduion, the front side porous siilerm layer .1 0 can he configured for antimfleetfon, in. which the refractive index of the front side porous silicon, iayer 120 can be: less than the tetraetlve.mdex of the emitter region .130, Exemplary ranges of the refraedve index of the front side porons silicon region 1 0 can be about 1.2 to about 3,4, The ftarrt side porous silicon iayer 120 can also be eombined with the andrefieetlon and passivation layer i 10 to form a double-layer antirefseetlon coating, in bieh case the refraedve index of the front si.de porous silicon region can be : ^' between thai of the antlfefiection nd pass ation layer 110 and that of the emitter egion 130, Exemplary ranges of xeft¾e e Index of tlie front side os^us lm region 120 can be about 1, to about 2, 1, Thickness of the front side orous sil icon layer 1 ^: eari ¼, for example, greater than the wavelength, of -raeidant Sight ^' Irs addition, along the thickness of the front side porous silicon layer 120, the refractive index can have a gradient, or a gradual change. More specifically, the front side p «x us silicon layer 120 can have a smaller refractive Index at the surface and a greater refractive index at the interface with, the emitter region 130 so as to resemble a multi-layer antlreflect u coating and improve the sntlrefleetlon property.

|007Y| Moreover, the teat side porous silicon layer 120 can be configured to have an uitra o refractive index (e,g , ·- ^■ f.0). I this ease, the refractive index of the front side porous silicon layer 120 is close to the reff active index of air, where incident light fo solar energy con version typically come from. Therefore, hen light propagates from air into the front side porous silicon layer 120 and foriher into d e eohlter region 130 .for energy conversion, reflection loss induced by change of retractive index across different media (Eresne! reflection) can he very little or negligible.

{3078] Simulated Performance of Solar Cells iael« i»g Porous B n

|C 0?9| Table 1 sho ws a. com arison of sitmdaied solar cell erformances in ter as of the open circuit voltage and short circuit current ^' (I _sc ). The simulatio is carried out using a com bination of commercial software programs^ including TFProbe for data fitting and optica! modeling, PC1D for electrical simulation (e.g. , uantum efficiency, 1-V curves, etc.), nd AFORS~Hst for electrical sltnukti n and some optical modeling.

respect to a baseline solar cell by ¾φ¾¾ιΙ ¾ one. arameter at a time so as to identify, investigate, and/or quantify the Influence of the adj usted p ameter

|00S§] The baseline solar cell lias basically the same structure as shown in FIG. I, but without the fr nt side and back side porous silicon layers 120 and 160. The antirefiecifon and passivation layer 1 10 comprises Sil% arid has a thickness of 75 nn , with inverse pyramid textures for Internal light trapping and reflection loss reduction. The n-iype emitter region .1.30 has a thickness of 300 tixti with a peak doping concentration of 1 ^x 10 ^i!> cst , The surface reeombiruition vel cit of minority charge carriers in the emitter region (also the majority charge carriers ¾ he base region) on the surface of the eniiiler region 130 is set at 50, 90 com, and the Steckley--Re&d-rial:l SRH) ^c mbination tune ir, _„ SRMl in the ^' bulk of the emitter region 130 is set at 2,2 10 ^'y s. The $"typs base region 14© has a thickness of 180 um and a peak doping concentration of 1 ,5 10 ^U< coir, A 300 rim thick heavily doped p-type seraicoodueior .material, with a peak doping coswenimtloft at 1 xl ^: m is used the BSF layer 150. The SRY recombination time ^' in the bulk o the ^' BSF layer is set ai 7* If* and the surface recombination velocity at the interface between the BSF layer 150 and the back contact ! 60 is set at 1 1 Q ⁷ cm/s. The baseline solar cell has a Y _iK of 0.618 V and l _si; of 8.87 A.

a e - mu ate : er rmance o o ar e s

I 0081 ] In the first experimental group, the surface lecombioation velocity on the stvrt¾ce of the emitter region 130 is reduced by ^■■' ¾*0% to 5,000 em/s. Lowering†he _: surface rceomkioaiiost velocity can mean, that charge carriers generated by the incident light jm a highe chance to

charge carriers out of the solar ceil, fo utilities, .¾ other words, reduced ¾r &ce recombination velocity is beneficial to achieve a higher short circuit current l _sc , $ shown in the second row of Table t in which the I^. increases fr m ;8,87 A, to 1.9 A in response to the reduction of surface: recombination velocity. A practical way to reduce t e Surface reeomb nation velocity can be pass! ating: the front surface of the ernitter region via, for example, a dleleetric passivation layer, or a porous silicon layer, or their combination.

[0882 j in the second experimental group, the SRH recombination time in the bulk of the emitter region 130 is increased, from 2.2* 10 ^' s to 4.4x 10* 8, increas of recombination time msansa longer lifetime r elms-go carriers, i.e. a longer tirne span between the generati n of charge carriers and ss of charge carriers via recombinatlort or other channels. Therefore, increasing the ti me of SRJi recombination, a, major sonteg of charge carrier losses Irs ibe huifc of the semkondueior, results In the boost of bothopetvcit ht voltage ^: V _tw and short eirenit enrrem l _sc , as shown in the fed row of Table I, n hic the i creases from.0:618 V to 0.626 V and the l _¾ : increase fera S ? A to 8.91 A in response to the increase of SRH recombination tlme>

£0883 j in a third exjrsrimentsl group, a front side porous silicon layer 120 is added to the- baseline solar cell and disposed between the antireileetion and passivation layer 1 10 (SiNx In this particular example) and the n4ype emitter region 130, The font side porous: silicon layer has a thickness of 1 1 rmi md a porosity of 60% (i.e. t he percentage of void spaces within th total space encompassed by the materia!). Moreover, the antirefieetion and passivation layer 110 is slightly thinned to 70 am. As described, above, porous silicon can hav an anti-reflection effect due to the proper refractive index. The front side porous silicon layer 120 nd the this e ample ears form a - layer (also refer ed to as douhie-!ayer) anti -reflection coating, thereby ftuiher reducing the reflection losses compared to the baseline solar cell in which only a single layer of SINx Is used for antirefieetion. Including a. front side porous silicon layer 120 in this example increases the open circuit voltage f rn 0.6 :· V to 0.620 V,

f In. a fourth, experimental group, a different front. side porous silicon layer .120 is introduced. The ront side porous silicon layer 120 in. this: group has a thiekuess of about 30 nm sod a porosity of about 30%. Moreover,, the awi:refiect:ion artd passivation layer 110 (he , SINx layer In thi - oup) is t hinned to 31 nm sneh that the same total thickness of the antirefieetion and passivation layer 1.10 and the front side porous silicon layer .1.20 is maintained with respect to the third experimental group. In general, lowe porosity can result In a higher refractive Index. For example, when the porosity of porous silicon approaches ¾ero {/.e., almost no pores i the silicon materia!), the refractive index Of the porous silicon approaches the: refractive index of a silicon substrate {:-3.4}, In another example _* when the porosity of porous silicon approaches 100% (Le,, almost no solid silicon material), the wfractrve index of the pprons silicon approaches the reftactive index of air f~ 1) that fills up the pores of the porous silicon. §mS] I this i< ≠h group, Both me open circuit voltage (from 0.616 V id 0,h26 V) and th short circuit current (from .8? A to 9.03A) are improved. The reason may foe attributed t better matching of refrasiive indices between the aotireileetlon and passivation laye 110 aud the porous silicon layer 320. More specifically, 30% porosity may create « refractive index between that of the antirefieciion and p assivation layer 110 nd. that of the emitter region 130, thereby aliowmg t he atdirefieefion and passivation layer 1 10 &h4 the Trout side porous silicon layer H O to form a bi~!aj¾r autteilectioo coating,, which typically has a lower reflection loss compared to a slngle laye amireikction coating,

086] It is also possible thai the passivation effect from this porous silicon layer 1:20 with lower porosity is stronger, thereby rcd t¾cing the surface rccomfhnati n velocity of the solar celt As shown in the first experimental group, reducing surface recombination velocity can ave: a more noticeabl effect In boosting the short circuit current than in boosting the open circuit voIt¾ge, _:

f §087] A fifth experimental group (not shown in Table 1 ) is constructed by including a. back side porou silicon layer 161) on the back side of th e basel ine solar ceil The back side porous silicon layer is disposed between ihe SSF layer 150 and the back, contact 170 shown in FIG. I . This bach side porous silicon layer 160 has 60% porosity and 20 nm thickness, including a back side porous silicon layer 160 tend to induce a greater effect on the performance of the resulting solar cells, in. this example, dur ope circuit voltage Increases from 0.618 V to 0.633 ^' V an.d the short circuit current increases fxnoi S1 A to 9.15 A. The increase of both the open, circuit voltage and. short circuit current is: larger tha an of me previous; group.

1 88] FIGS. 2A-2B show simulated energy hand diagrams of a semiconductor system including a silicon substrate with, nn mtvpe em tter re io , on which a porous silicon region (or layer) is disposed.. This semiconductor sy tem can be, tor example, on the front side of solar cells, FIG. 2A shows the energy hand diagram on and near the interface between the substrate silicon region and inn porous si h cos .region, more specifically, the flrst 1,25 tun e i n fro the top surface of the seoheondueior system . In FIG, 2A, the porous silicon laye has a thickness of 20 nro and a porosity of 60%. These parameters are for illustrative purposes onl , in. practice, these two parameters can have different values for different applications. For example, the

I S

poro s silicon layer ean be anywhere betwee about 25% to about 95%.

It W] In FIG, 2A, both the valence band (greets line) d the eonduetloft band (bine line) are smooth i« general, except ors the isiterface between the porous silicon layer and the n-type emitter region, w here the energy potentials have an abrupt jump; FIG, 2B sh ws a zoonvin image of the energ band diagram of the first 60 m from the to surface.. It can Be readily seen that the c nduction eaa has a sharp decrease of energy potential from the emitter region to the porous silicon. region. and the valence baud has a sharp increase of energy potential from the emitter region to the porous silicon region, Note that y-axis in FIGS, 2A-2B has: negative: values m the region where the energy Band arc plotted. Therefore, a "visual i crease" ^' in the plotted lines corresponds to a decrease of energy: potentials, and vice versa,

ff i §j I s operation, o the conduction band, the sharp decrease of energy potential from, the emitter region to the porous silicon region creates art electric field pointing toward the porous silicon region. Charge carriers . n the conduction band are mostly electrons carrying negative charges. Therefore, these negative charge carriers are expected to experience a resistance when transporting from the emitter region to the porous silicon region and. reaching the front metal contact. This can be iradesirable to the performance of the solar ceil However, the magnitude of this change is wry small (<!QQ m.V), s the Influence on electron transport through this mterfece can. be neghgi ble.

{0093 j On the other hand, the magnitude of ene gy potential increase from the emitter region to the porous silicon, region, on the valence band is much larger >550 mV), thereby inducing a stronger field (compared to the electric field on. the condnetiors band) pointing toward the emitter region. Since charge carriers on the valence band are mostly boles carrying positive charges, these: positive charge carriers, are expected to encounter stronger resistance when traveling:

toward the porous silicon region. This resistance can. reduce the transport of the hole from the emitter region to the front surface for recombination, thereby increasing the lifetime of the charge earners, i,e, passivating the emitter region.

1 0921 FIGS, 2A-2B show that porous silico layers can. have a larger band gap than that of the silicon, in the emitter region ( ⁴ ¾ubstrste sillc Tt ^>' i Moreover, the energy band diagram of porous silicon layer disposed on substrate silicon. In general, tends to block the transport of charge c rrie s i on. both conduction band and valence band) from the substrate silicon tp the porous silicon w electric fields. But since the electric field on the conduction ban is much .weaker h n the electric field on the valence band, the net effect is reduced or suppressed transport of holes rom the emitter region to the porous silicon region, thereby inducing ¾: passivation effect that is "beneficial to the pertbrmanec of the resulting solar cells,

|0003·| In. practice, the dift¾rerice of band gap energies (a«d or the energies potentials on. the conductiort/vaieftee bands between that in die .emitter region and that In the porous silicon region can. be tuned via, for example, the porosity of the porous silicon region. Exemplary range of band gap energy difference can be greater 550 roeV, between 150 meV m&.550 meV, between 250 meV and 450 nieVi or etween 300 meV and 350 meV.

|i§94) FIGS . 3Ά-3Β show sirntrlaied energy band diagrams of a. semiconductor system including a silicon sutefraie with a p-type ba.se region, on which a porous silicon region (or layer) is disposed. This system can be, for example, on the back side of solar ceils including a porous silicon layer. FIG, 3 A shows the energy band diagram of the first 500 nm. region, from the back surface, and. FIG. 38 shows a zoon-hi image of the band diagram, of the first.30 nm so as to illustrate more clearly the change of energy potentials across the Interface between the porous silicon region and the p- vpe semiconductor substrate region, in this example, the porous silicon Is disposed on a BSF layer, in anothe example, the orous silicon can be disposed directly on the p-type base region.

[009SJ Across the Interface between the p-type BSF layer and porous silicon region, the energy potential o the conduction, band decrease from the BSF layer to the porous silicon region, thereby generating an electric field pointing toward the porous silicon region. Since charge carriers ou the conduction band are mostly electrons carrying negative charges, this electric field tends to block the transport of electrons fern the BSF lay er to the porous silicon region, fM ] On the vakoce band, however, the. energy potential increases front the BSF layer to the porous silicon region, thereby creating an electric field pointin toward the BSF layer. This electric field then can suppress the transport of holes (major charge carriers on valence b nd) from, the BSF layer to the porous silicon. Notice that the increased energy potential outside the BSF layer returns, substantially to the original level (the level in the BSF layer) alter a short distance. So the transport resistance of holes acros the interlace between the BS F layer and the porons silicon layer im be small. Taking into aeeoont toe resistance to charge carrier transport on both the conduction hand and the valenc band, it can be seen that the set effect Is still positive, i.e. mote electrons: are expected to be blocked than holes, thereby passivaikg the back si«1¾ee of the solar ceil,

| 097| Other than th pass atio effect, the enlarged band gap of the porous silicon layer compa ed to the substrate silicon region, (partlcidajiy the emitter region) may also improve the performance of solar cells by irnnroviBg the bine response, i.e. effective absorption of light at shorter wavelengths. This can be attributed to the niatehfeg condition (also referred to as resonant condition) between the incident photon energy and the band gap energy, in other words, larger band gap energy can result in better absorption at shorter wavelengths which carry higher photon, energies.

ff if 8| Potential benefit of enlarged band gaps in porous silicon can also reiate to reduction of thermal, losses. As introduced before, the enlarged, band gap can raise the threshold of heat generation because photons in the simlight no need a higher ener in order to overcome the enlarged band, gap and generate heat based on. the excess energy (diftererii between photon .energy and band gap energy^ hi other words, porons silico can facilitate more eflcctiye absorpdoa of photons, part cularly the shorter wavelength com onents (hi gher fre¾ue∞y components and higher photon energy part) Of the sunlight, without generatin thermal heat. f¾£H»9J FIGS. 4 A~4B show simulated reflectance of surfaces incit n a porous silicon, layer, in each figure of FIGS. AA. and,4B,

.silicon with a single layer of SilNk are also . ^' included,

fflfM J Reflectance, corves shown, in FIG.4 A. are taken on samples based on polished (smooth) Silicon substrates. The bare polished silicon has a high reflectance across the entire spectral region between 300 am and 1.2 uo . In particularly, on the two spectra ends (below 5Θ0 «.m and above 1 μηι), the reflectance on bare silicon can be as high as ore than.30%, thereby Inducing high reflection losses. Depos og s SiNx layer on bare silicon can noticeably reduce the reflectance in the visible and near infrared region ( .g,, _: 400-1000 nMX _: bu the reflectance in the shorter wavelength region can remain, at high levels. Further decrease of reflectance is then achieved by himtdaelng a combination of 55 am SiNx layer with a 30 tint poroits silicon layer (30% porosity). Th te ting surface has Sig iicantl lo r refiecfcaPee ¾ the wavelengths shorter tbatt 500 nrn.

I 011 FIG, 4B shows reileeiaiiee of sainple Mi i e s based on textured silicon surface prepared y, f& ¾jEam ie, KOB etching.. The texture alone already shows reduction of reflectance comp ed to sifteoth surfaces shown, in FIG, 4A. Qualitatively ^' »i ^' mik£- to the trends: in IIO , 4A ₅ depositing a SiNx layer on, the bare sflleoo ί substrate reduces he reflectance in visible and near mfrsred region, and Including a combination of a. SI layer and a porous silicon laye farther rec es reflectance in the short wavelength region, hi the last ease, when both Si x layer and porous silicon are deposited, on a textured silicon so hstrate, the reflectance can be as low m nearly zero (e ., <S%) withi a wide spectral window between. 350 am and 800 am. Outside this windo w, the reflectance is still below 10% for wavelengths shorter tha 1050 am and below 20% for wavelengths between 1050 am and 1.200 nnx. Therefore, negligible reflection loss can be expected from solar cells with an antfeftection coating (ARC) comprising a combination of a SiNx layer and a porous silicon layer.

Simulation of reflectance can also be employed to derive porous silicon, parameters that are .not readily measurable m experiment {e.g., pomsity) as demonstrated in FIG, 5, This method includes the simidation of reflectance of a series of samples (simulation samples) Each, sample may include a porous silicon, layer having a different parameter. Then the reflectance of a particular experimental sample ca be measured and the acquired experimental reflectance can be _: compared against the series of simulation samples to identi fy a besPmatehed simul ation sampl e. Since parameters of the simulation samples are all known, the parameters of the maiebed experimental sartrpfe can be derived ® be similar to the simulation parameters with reasonable eonfidenee,

|i183) FIG. 5 shows that the experimental reflectance curve best matches a simulation sample including a porous silicon layer having . a thickness of 10 iw and a porosity of 60%. Therefore, the experimental sample is believed to have a silicon layer having approximately a 10 Am thickness and 60% porosity as well This method can provide a rough es itoatlon of porotrs silicon parameters. More accurate estimation require more thorough knowledge about the effects of other parameters of porous silicon on the reflectance property, sneh as morphology, doping concentration, refractive index, and refractive index distribution, amo&g others. [OMM-I Advanced And efleeflfMi atod Passivation Platforms Caitvetted from FSG ESG Etch and Junction Isolation Tools far Sola Ce l Fab ication

I 05] Conventional .solar cell manufacturing typically invokes wet chemical efc¾n

rocesses. In particular, wet chemical etching processes, represierit a sutaxiani procedure in batch or inline ased production lines for crystalline silicon solar cells. For example, before doping •silicon su st ates, SCI or€ tan be used for removing organies, while HCi HF, 0¾ or H ₃ O ₂ nan be osed to rem ve metal impurities.

f §1 j After doping, doped n ype silicon bstrates normall have a laye of pbosp osi!ieate glass (PS ^' G on the surface of the substrates created during the diffu ion (doping); la practice, the PSG layer may act as a constant source of dopants for subsequent diffusion steps, thereby fixing the surface concentration of the phosphorus doped areas to the solid solubility limit Accordingly, it is in general, desirable to remove the -PEG layers (PSG etch) m fabricating high efficiency solar cells. PSG etch can be achieved by, for example, HP or Ν¾Ρ etching.

|§!#7j Similarly, p-type doped sili substrates can. als have a layer of bomsilieate gl ss (BSG) created during the diffusion process. The BSG layer may lock, the surface concentration of the boron doped areas to the solid solubility limit, preventing further doping, BSG layers can. be similarly m ed vis etching processes using BP or Ml-L ₅ F,

lilSSJ Pirrtheraxtre, daring the dif&siou process, phosphoru not onl diffuses Into the desired front surface but also on. the edges .and the rear surface, creating a shunting path between the solar cell, front rear. For this reason, various edge isolation: techniques imve been devised, including,: among others, plasma etching and laser cutting. As a conventional praotiee, edge junction Isolation, Or the removal of the path around the wafer edge, is coniffioniy achieved by "mm stacking" the cells. The stacked cells are then placed ms&fe apJ^ a eichln :»ha$¾te t« remove the: exposed edges, fiowevep slacking and on-stacking in theso Isolation techniques may lead to a strong disruption in the process flow, thereby i creas ng anoi eturing cost.

Alternatively, inline process of junction isolation, without the steps of stacking and un~staekmg, can be achieved, via..& we ehernical etching step, in which mixtures of PIP, HNf¾ and ffcO are utilized to etch away diffused layer.

Iflfi j n conventional solar cell manufacturing, the junc tion isolation process may create poroos silicon. However, this porous silicon is generally an ondeskable byproduct because, at least partially, the creation of th poroos silicon is uncontrolled. Therefore, conventional solar ceil maaafaeturieg normally itnjludcs a step f porous silicon etch to remove undesirable porous silicon,

I .10} E^sting too!s to implement wet chemical etehmg |¾r solar cell fa eahon, more specifically for junction isolation, PSG etch and or porous siiico« eielr normally comprise: a junction isolation process a k, a first rinse s ation, a porous silicon etch process tank, second rinse station, a PSO etch process tahk, _. a third rim s a ion and a dry Station, Bach process tank: cars be coupled to one or me e chemical reserwlrs. For instance, the j nction isolation process tank can e coupled to a IIP neservair, a rJNC¾ reservoir and a ¾S(> reservoir. Additional reservoirs to contain water may also be included. The porous silicon etch process tank can be coopled to three chemical reservoirs for HP, H 0 ₃ and HjO. or KOH, laopropy I alcohol (ΪΡΑ) and 1¾0. The FSG etch task can he coupled to a BF reservoir,

f 011 i One or more chemical dosing u its ca be coupled between the process t nks and the chemical reservoirs to control and monitor the amoun , pressure ancVor fl.o speed of the chemicals so as to optim ze the etching process. Rinse stations in the above tools can. use do- ionised (Oi) water or nitrapure water to clean silicon substrates alter each etching, step, fiii 1.2} The dry station can use hoi air or nitrogen to dry silico substrates alter rinsing.

Alterna ively, more advanced surface tension gradient drying technique can also be used. The snrinee tension gradient drying,: or nraugoni d-ryiug, can utilize a volatile ^' o¾aa¾ eoif&fjouud (e.g. alcohol or ΪΡΑ) with a lower surface tensio than, water that is introduced in the vicinity of the snhsirate as it is slowly withdrawn fern the water. As the small quantity of the volatile ^• compo nd vapor comes into contact with, the refreshed water meniscus, it dissolves into t e water and creates a surface tension gradient which, causes the meniscus to partially eonfniet and assume an apparent finite angle. Tilts causes the thi water ^■ film to flow off the substrate, thereby drying the substrate. Moreover, the yarangoni drying can also emove contaminants and particles during the drying process.

i #11.3} in operation., a conventional junction isolation and PSO etch process 410. for sola cells, as shown in FiG. 6, comprises the following steps. Is step hi L a silicon substrate {after doping) or solar cell fi rieaiion can be exposed; to. a chemical solution tor junction isolation. The chemical solution can: be delivered from eheniieal reservoirs h i la - 61 l.e that contain HF, H O¾ and h SOii, respectively. Step b 12 rinses he junction isolated substrate by removing excessive chemicals o the substrate, preparing the substrate for step 613, in which a porou silicon etch ste is carried out A seeo«4 r ase thes cleans th etched sute&ie in step 61 , followed by a PSCi etch tep 615 to remove any PSG on the surfaces of file substrate via us of BF from the e¾ernical reservoir 15% Another rinse and dry step 616 then cleans the substrate: and dries the substrate for further processing, suc as metaiikatlon,

f ll 1.4) The shove tool for solar cell processing Can be retrofitted and utilized, as shown m the Ixittora half of HO. 6, to implement stain etching roce s s to produce the conventionally undesirable porous silicon layers in a couteliable manner, while a the same time realizing junctio isol tion, PSG etch, etch-hack, passivation, and anti-refleeiion coating, srootjg-ot ers. This modified, method 620 ears simplify fabrication steps for solar ells and accordingly reduce mann&eturing costs.

flfi 15) More specifically, the junction isolation unit, which generally comprise a junction

can be configured to passivate the back side of silicon substrates, in addition to junction, isolation. A stain etching solution can be placed in one of the plurality o f chemical reservoirs to grow a porous silicon layer on the back side of: silicon . subs rates for passivation, Since the stain etching solution can also react with, the edge of the .silicon substrate, a layer of diffused silicon c be etched away, thereby achieving efficient edge Isolation.

[01 I 6j The PSG etch unit, which generally comprise a PSG etch process tank and a reservoi for OF, can be eottftgured to pa srvate the front side of silicon snbsirates, in addition to PSG etch, anti-reflection layer coating and. porous. ilicon, etch. 1 be HF in the ehephcal reservoir can be replaced fey a stain etching solution to . grow the porous silicon: layer on. the trout side of silicon substrates for passivation. Since the growth: of porous silicon layer normally starts: when the stain etching solution comes in contact with a clean silicon surface, the solution can also he utilized for PSG etch.

it?] Moreover, the stain etching solution can also create textured front surface for solar ceils during the sanie step of passivating the front side, thereby replacing :or supplementing the f ont, side texturing i * for example, K.QM etching. In troe example, the surface texturing is solely achieved hy the stain etching solution via porous silicon creation. In another example, a ROB etc is employed to create surface texturing with a large feature size (e.g., on mtcratnete scale, on hundreds of nanometers scale, etc.). Then the stain etching sol ution is used to create additional texturing i h finer st uctures, ch as I» the nanometer scale, to mrther improve it light trapping properties,

I I S) In - :e.t another ^: example, t e stairs etching solut n can ubricate solar cells wi h smooth surfaces m the emitter region _* while the antiretleetion cedin disposed 0 . the emitter region is textured clue to the porosit of the porous silicon layer. Solar cells with smooth surfaces i the emitter and/or base regions but textured antireileetion coatings can ve several ad antage _* sue as reduced foot sur&ce reeonibination -velocity and a higher level of front surface passivation due to a less damaged silicon surface and reduced silico surface area. Furthermore, these solar ceils can also have a higher efficiency because of a decrease in the emitter sheet resistivity loss, lower contact resistance, higher .shunt res stance, and. a lower diode ideality factor,

f 0119) The resulting porou silicon layer can also ^■ ■function, at least in part, as an anti-refiectioi coating (ARC) to help solar cells retain the incident solar energy , in one example, the porous silicon layer alone may form a single-layer autireflection. coating, in another example, the porous silicon layer may be part of a niulti-layer ARC, whic can also include a silicon nitride (SiNx) layer, a silicon oxide (SiOx) layer, or m aluminum oxide -.{AbO*} layer, with a. larger refracti ve index thm that of the porous sil icon layer.

101201 In o eration* a method 620 ©f 1 acihtating rlbrication of a passivated emitter and rear solar ceil, via a Main etchin process using existing solar cell processing tools can start from diffused silicon substrate. In. step 62 ! , at feast a portion of the silicon substrate lo the solar ceil, can be placed i the .junction, isolation process tank to allow contact between the portion of the silico substrate and a stain etching solution deli vered from a chemical, reservoir 62 la. The chemical reserwir 62.1a can he selected from any one of the chemical reservoirs: 61 la - 61 le. Chemical reaction b t een silicon substrate and the slain.: etching solution can create a hack side passivation layer comprising porous silicon. At the same: time:, chemical reactions between the su strate edge and the stain etching solution can also remove a difftrsed layer, thereby achieving junction isolation.

C0I21I Following the stain etching processing on the: hack side in step 621 , the silicon suhstrai can he rinsed in the first rinse station during step 622 before being sent to the PSO etch tank, in which the front surface of the silicon substrate can be processed via a second stain etching step: 625. The seeond stain etching step 625 ean produce a front side porous silicon layer and fulfill one or more of the folio wing purposes: cleanin the silicon substrate hy removing any FSG layer, etching back the ^' -silicon, substrate, passivatmg the fttM side, aad -femlmg.at l ast a portion of .an. anti-reflection coating,

fill 22} The second stain ^' -etching solution, ^' which, can be delivered from a chemical reservoir 62:5a. converted horn the chemical reservoir 13a in the solar cell processing tool, can be further configured, to create a textured, surface on the front, side of the so lar ceil ^' by,-i f exampl e, creating a porous silicon layer with pores, of large sizes. In step 626, a third rinse station can ihm clean the silicon substrate by removing excess stain etching solutions, followed b a dry station to remove excessive water introduced by the previous rinse step.

$123) in each of the two stain etc hing steps, on the from side and back side of the silicon substrate,, respectively-, more than one etching solution can be used so m to further increase the controllability of the porous silicon creation process. For example, when, stain etching the fr nt side of the silicon substrate, one etching solution can fee configured to target the PS(J layer on the front surface: and quickly remove the PSG layers, A second etching solution can then replace the first etching solution and mostly perform the porous silicon creation. In another example, a first etching solution can be configured to etch back the front side of the silicon substrate more uuitonniy (i,e, ₅ etch away a smooth laye Iron* the front side). A. second etching solution can be configured. to.-c^ate ^' iKmsift ^' -Oi iceTmiuiag.s eoAi substrate, thereby creating the porous silicon region,: In ye another example, the etching .solution, can: be configured to have diffcreni directional preference when doing the etching. One etching solution can preferably etch the silicon substrate in a vertical direction, and another etching solntion ean preferably etch, the silicon, substra te in a. lateral direction. Ttiuing tire clati ve etching time of these two etchin solution ears therefore create porous silicon layers with desirable morphology (e.g., pore sise, shape, alignment, etc,}. The above examples are for illustrative purposes only, in practice, the number of etehing soiutlon can be _: varied and adjusted depending on applications,

ff I24 j In. each of the two stain etching steps, the etching solution, according to one example, cap include a first percentage of a bydroflnorie acid (BP), a. second percentage of an oxidant,, a third percentage of a mineral acid, a a fourth percentage of balance water, The mineral acid can be, for example, ¾$ ⁽ ¾., HQ, HBr, ¾K>4, BNC , and HI, among others. The oxidant can fee, for example, HIGH, which can have an amount of about 0,02 gram: per lifer (g/L) to about 0,8 grams per liter (g/L), fil lSJ la another example, the etching ^ l«tidn can Include a first percentage of a hydro fluoric acid (ΒΨ a second: percentage of f!h¾ a third percentage of a H¾$0* :« fourth percentage of a surfaetnal m$ .f ufth. srcentage of water; The surfactant cars he, for example, ammonium lauryl sulfate (ALS),

The overall etching speed of the potOUs stilk creation process may be timed. either by the composition of the etching soltuioa, or by the temperature at which the chemical reactioo occur. On the solution composition side, for example, increasing the BP concenteatioo cm in general increase the etching rate, .Similarly, higher percentage of oxidant can also result in fester etching. The purpose of H€i and H ₂ SO ₄ . and/or any other acid is to, _: at least partially, shift the pB valise of the solution to lower values such thai he oxidant is in pm ona form, whieh is the active form. For example, the acidity ( K _s ) of BlO¾ is a out 0,75. Therefore, at one pH step below this value fi.e, "0,25), the HIO.3 is almost completely protonated. Accordingly, additional acid cart have a. wry small or negligible effect below certain threshold. On the temperature side, increasing the reaction tern erstare can increase reaction speed in general. Therefore, a variable growth speed during solar cell fabrication, can be achieved if desired.

fiil 27) Converting existing tools in. solar cell processin to an advanced passivation, platform for solar cells described in the above exemplary embodiment can have several advantages. First of ail, the conversion involves almost no modification of existing syslems and therefore equires nearly se o capital expenditure {C APEX).

|112S) Moreover, the converted system can ftdfill severai purpose in. a single step. For example, the back side passivation, can simultaneously remove phosphorous diffusion, on the substrate edge and achieve junction isolation, and tlm front side passivation can concurrently create at least portion of anti-reflection coatin (ARC), remove any PSG on the substrate surface, etch, back the fr nt side of th silicon substrate, and texiurtee the: front surface of the resulting solar ce l to increase efficiency. This simplifies the fabrication process for solar cells by eliminating at least the use: of extra el&mieal reservoirs in the junction isolation unit, and the silicon porous etch process tank and. the associated rinse station, The method also renders unnecessary several thermal steps that are normally part of a fabrication process when silicon oxide layers are thermally diffused.

111-29) T he converted: advanced passivation platform can also he more efficient than previous passivation systems such as dry/wet deposition systems and therniai/cheraieal. growth systems, More specifically, the advanced assivation platform, can produce po ous silicon layers within a

the application of .the porous s licon layers. The etching speed of the advanced passivatio platform can also vary in a. wide range - from a few nanometers per minute op t as high as 500 tonometer per minute depending nt least in par on the composition of the stain etching solution or operation temperature. The resulting orous silicon layers can have excellent passivatio effect and extend the lifetime of clmrge carriers o as to improve the solar cell efficiency.

$130 ^' ] Comparing to other methods of passivation layer fabrication, the passivation system according to exemplar embodiments of the irrv¾ntion etm have a. wider thickness range than both thermal and: chemical growth systems, a hotter passivation effect than wet deposition technique, a lower€ APEX than dry deposition technique, and a shorter process time than thermal, growth method. In summary, the advanced pa-ssivaiion system can reduce overall manufacturing cost by streamlining the process and eliminating several steps and modules. The system can also improve environmeotal eudlmess by eliminating at least one rinse station (save water) and several thermal steps (save electricity or gas).

101311 FIG. 7 shows an input and output system 700 for an advanced passivation platform like the one shown in FIG 6. On the input end, a semiconductor substrate can be thermally diffused in step 710 with, doping materials before being sent to the advanced passivation platform for back side and front side processing as in step 720. Al eraatkely or in addition, the doping materials (f e„ dopants) may be introduced into . the substrate via ion. impl ntation, laser-assisted: doping, or other means known in the aft On the output end, the passivated substrate can he delivered for additional coatings, in one example, a layer of silicon nitride (SlNx) can he deposited over the front side porous silicon layer via a plasma enhanced chemical vapor deposition (FECVD) process to furthe improve the anti-reflection property of the resulting solar cell. 1ft another example, a layer of aluminum Oxide (AM¼) can he deposited on the front side porous silicon layer via an atomic layer deposition (ALD) technique to further improve the passivation effect,

111331 Li ~m mul E y- i 4m≠m ni Process of Fabricating Highly Effieknt Seiar Cetfs In admg Porous Silicon Layers

¾9 fill 33) One more advantage of. tfce passH¾lk«i. method via stain etching rocess s is its eoitipatibiliiy with conventional screen printing meialimat n thai creates frost and back electrical contacts. The stain etching process allows the use of screes priming pastes which offer lower contact resistance and more conductive from grid contacts. As a result, the advanced passivation systeni that implements the passivation method can be conveniently integrated into conventional solar fa rication systems,

|II134| As described above, the advanced passivatioa system can in a single step: (i) in-situ chemicaliy clean the silicon substrate surfaces, including the ntetalteed surfaces making them; interconnec ready, (ii) produce porous s licon layer that passiva es the sur ace and reduce reflection losses, (in) create textures on the front surface of the re ulting solar cell to improve efficiency, and/or (iv) etch back at least a portion of the front side of the solar cell to remove surface dead layers and. improve the sheet resistance. Based on this advanced passivation system, a modif ed fabrication method tor passtvated emitter and rear ceils (PER.Cs) can comprise steps outlined below.

|0i3Sj The first ste can be texturing a semiconductor substrate by creating a plurality of inverted pyramids on the front surface of the semiconductor substrate. The inverted pyramids cm. be either periodic or random and can be produced by a KObl/isopi-opanoi d ution.

Alternatively, a photolithography mefbod e ii be atilked to create the inverted pyramid pattern,. In: operation, the inverted pyramid structure can decrease optical, losses due to reflection.

Moreover, due to the .min mized contact area, between, the metal contacts and the silicon stibsirate, electrical losses can also be reduced by this Inverted pyramid structure,

I } Following the ^■ surfa e texturing, the semiconductor substrate can he doped, or diffused with, for example, phosphorous on the fr nt side as is readily understood in the art.

Alternativel or in addition, both the front side and the, back side can be doped so as to construc a bifacial o heterostruoture solar cell. Doping material m also, inchtde k>ron, aluminum or gallium, in addition to phosphorous. A variety of techniques can be employed here. For example,, a phosphmmrs coating can be ap lied, to the surface, and the coated substrate can be p t in a belt furnace to d ffuse a. small -amount of phosphorous into the substrate. In another example, doping the semiconductor snbs-traie may be achieved vis an km Implantation process, in which ions containing doping materials ace: accelerated and fired into the substrate. fil 37) Doped semiconductor substrates can the be ex osed to a,.f¾st M etching solvndort for back side processing, including junction isolation and back side passiv¾tiop layer formation, followed fey .-front side processing to remove FSG Impurities on. the front surface, to etch back the front side, and to create a porous silicon layer for passivation and anti-reflection coating. This step can be implemente b an ad anced passivation, system converted from existing tools for solar cell fabrication* more specifically for junction isolation and BSG etch.

1 1.38.} Passivated semiconduetor substrate can then be coaled with a layer of silicon nitride (Sif¾) on. the front side to create an anti-reflection coatin (ARC) via a plasma enhanced chemical vapor deposition (PEC¥D). i one example, the SiNx layer alone can function as an ARC layer. In another example, the SIMs and the porous silicon layer together form a effective ARC layer.

f 0139 One or more metal, contacts can be screen printed in on semiconductor substrates with ARC layers to conduct electricity generated by the solar cells. As is readily understood in tbe art,, the front side metal contact can eon rlse silver (Ag} _5; while Aluminum (A!) Is ^■ commonly used on the back side. Screen printing method and the metal pasted used therem are compatible witb. stain etching solutions for porous silicon layer formation, thus the screen printing step and the passivation step vis stain etching processes may be arranged in arbitrary orders.

|;0 ^' 1 0} One ar mors via can be created to facilitate the back side screen printing and ensure that the printed metal contact can. have electrical contact with, the semiconductor substrate beneath, the back; ¾ide passivation, layer that includes porous silicon regions.

$141]

of the silicon, substrate. The resist: dot can be created b manually stamping, or

photoiithograpby techniques, Irs which a resist film is spin coated onto the surface, followed by selecti ve: etching irsing a radiation. Stain etchin processes applied on the back side co vered by resist dots can then create a patterned, orous silicon layer, which is disposed onl in areas no covered by the resist dots, Renioviog the resist dots eaa therefore expose the base region of the semiconductor on the back side for screen printing. The resulting metal layer from screen printing ca accordingly have electrical contact with the semiconductor ssria.ee at least in locations where the -resist dots are placed. In this exemplary embodiment, the metal contacts are non-fire through, but fire-through contacts may also be osed, fil 42) Follo ing the screen printing tsf metal cental, the semiconductor substrate can be placed in one or more _. furn cs. or dry in.g-.M ¾i¾g. More specifically, _* the rnetal pasfe can ..first fee dried at about iJO to remove ntuch of me solvents, wthchtnay cause excessive out gassing a«d lead to cracks and voids. The dried substrates are t fired «slde a firing .furnace that cars, titther decomposed int fou steps. The first step is the initial temperature ramp up where the paste solvents are volatilized. T e second step i the boor onf which can remove substantially all o.f the organic binder used in paste ..formation at-SOO^OO^C Tie third ste is the sintering, or the firing process, hieh ears be done between the ranges of TOD- KfC I a furnace. During this process, t he metal forms a bond with the underlying 'Semiconductor substrate to form, metal contact. The final step in the drying and firing process is the cool down ^' p ase,

fil 431 Solar cells alter drying and firing step can then be sorted according to, for example, their electrical performance. Simulated sunlight, provided by a pulsed xenon lam with an optical filter to produce a close match to the air ass 1.5 global, s ter -spectrum, _. -can be used for the testing of electrical performance.

|0i44J The modified solar fabricatio process can be farther modified to produce passlvated emitter and rear locally (PERL) diffused cells. In diss process, only areas that would have electrical contacts with the- ba k side metal contact are doped withboron. The rest of the process can be substantially similar to the above described process.

101 5] Porous SIMeosi Laye s Fabricated via Sta n efjing /Teeh qaes

fll FICSS, 8A-8B show Scanning Eieetron Microscope (SF.M) images of two porous silicon films created f roru n. ype silicon substrates via a slain etching technique. The etching technique starts front a doped n-ty e silicon substrate, followed by an etch-back to re ove some surface dead layers and diffused Phosphosllieate glass (PSG) layers. Then the etched back substrate is disposed in as* etch-back solution, which comprises :G,2%~] 0% Hydrofluoric Acid ^' HF), d,9§4%- 0.1 % Iodic Acid (HICK), ί%-2% Hydroch rie aeld (BC ), and balance water. In addition., ethanol can lso fee added to the solution to te j>«n¾ the wettabili ty of the silicon substrate. A practical range of ethanol in the eteh-baefc solution can be up to 20%.

101 7] Table 2 below shows the conditions for creating the porous silicon layers {labelled as "Top and "l op 2 ^M ) shown in FIG. $A and 8B. Substantially similar silicon substrates re used as the base substrate on which porous silicon layers are created. For example, the substrate for Top ! layer and- Tfcp layer te a .sneet resisianos ( of 61 i¥sq and 62 l¥s , respectively. After he etch-baek of SOnm - O0¾m-, the sheet resistance increases to M l sq and I32i¾/sq for 1 op 1 layer and l ^" op 2 layer, respectively. ^" Then both etched back substrates are iinmersed in the same stai etchi g .solutio to fabricate porous silicon layers. After the stain etching. Top 2 layer is treated by a series of thermal processing, iue!ndmg 15 inutes of the mal drying at 100 °C, 5 nnntnes of thermal firing at 400 *G (simulating the the m l effect from a FECVD treatmeai bat without coating say fi lms oft the solar cells), 20 seconds of thermal firing at 550 "C, tbllowed by 5 seconds of thermal firing at 800 "C and another 5 seconds of thermal firing at 900 "C In contrast, ^' Fop 1 layer is not subject to any thermal treatment and is dried at room temperature, .0148 The resulting Top I and ^' lop 2 layers are shown i FIGS, 8A and 8B, respectively. The poroas st!icon 801 shown in FIG. 8A includes porous silicon layer 812 disposed on a silicon substrate 814. The thickness of the porous silicon layer 1.2 is about 41.7 urn. The porous stiicon 802 show in FIG. 8B includes a porous silieos layer 822 disposed o a silicon substrate 824. The thickness of the porous silicon layer 822 is about 34.3 am. he resulting difference in thickness of the two porous silicon layers 812 and 822 ma be attributed to the thermal treatmont (or the absence of treatment).

Table 2 - Conditions for creating the porous silicon layers shorn in FIGS, 8A and SB

If 1.49:| Table 3 below shows the conditions for creatin the porous silicon layers {labelled * "Middle 1" a "Middle 2") showu In FIG. §A and ?!i The starting silicon substrates have; sheet Rh - of 61 i¾¾ and 59 Q sq for the; Middle 1 layer and Middle 2. layer, respectively. Then a etch-back of only 5 urn ·-- 10 urn Is carried out to remove diffused PSG layer on the surface, followed by slain etching to create the porous silicon layers. After the stain etching, Middle 2 layer is treated by the same series of thermal processing as for the Top I layer in FIG. 8 A (i.e., 15 minutes of thermal drying at 100 *€, 5 min utes of thermal firing at 400 X, 20 seconds o therm l firing at 530 _r followed b 5 seconds of thermal firing at 800 X. and another 5 seconds of thermal firing at 900 *C), In contrast. Middle I layer U t subject tcf-fciy thermal treatment and is. dried ¾t room temperature.

11159) The resulting porous silicon 901 shown in FIG, 9A includes a porous silicon layer 912 disposed on a silicon substrate 914. The thickness of the porous silicon layer 912 is about 10.3 stm. The porous s licon 902 sho n ih FIG, 9B includes a porous siilcoft layer 922 disposed on a silicon substrate 24. The thickness of the porous sillcdu lay¾r 922 is about 1 ,9 am,

pi!Sij Comparing the conditions listed in Table 2 and Table.3 _S It can be seen that she resulting porous silicon layers eas be sensitive to the conditions of the silicon substrate before the stain etching i .g, ₅ removal of PSG laye k these two exam pies). The silicon substrate used in FIGS. 8A-SB and FIGS. A-9B have at least two differences. First, die etch-back ndifferent Silicon substrates iu FIGS. BA-8B are etched back by §¾ro -lOlTam, while silicon substrates in FIGS. 9A-9B are etched back by $n -10 nni. Second, the resolting sheet resistance the etch- back is also different, Silicon substrates in PIGS. 8A ¾ have a sheet l¾ho of around 132: - 140 ί /s after etch-baci while silicon substrates: in FIGS. A-9 h e a sheet Rho of around 69-70 Ω/sq after etch-back,

f The resulting porous silicon, layers also have at least two diifeeuces. First, porous silicon layers shown in PK5. 9A-9B in general are much thinner than those shown in. FIGS, SA- BB, Thi rnay be attributed t the smaller efcn-baefc for the "Middle" group. Without being ibound by any particular theory or mode of operation, silicons: substrates used tor the "Middle" group may still ha e res ne.PSG layers so ihe stain etching m y used to overcome the residue P CJ layers, or other impurities on the s rraee, before creating porous silicon. Also, the different sheet resistances may engage different efeemistry during the formation of the porou silicon layers. | ίΙ 53) Second, thermal treatments have opposite ffects on the resulting dtiefcness of ibe p ro s silicon in FIGS. -SB and FIGS, -f 8, in FIGS. -SA¾ ¾ seems that thermal treatment can decrease the thiekaesa of the resulting poroos silicon, wlp!ek FIOS. 9.A-9B the same thermal t eatment may be the as n of t¾e thicker porous silicon layer (Middle layer). Therefore, the possible residue PSC* layer, or othe impurities on or sear me substrate surface, rnay also play a role d«rin¾the thermal treatments in intlperieing the final ihiefcness: of the pormss silicon layers.

|0i54] Moreover, the different effect Induced by thermal treatment may also be related to the sheet tssistanee. In FIGS, 8A-8B, the difference of sheet Rfeo between tbe substrates for Top 1 layer and Top 2 layer is about 8 q, while the difference of sheet Rho between the snbstrate for Middle I layer and Middle 2 layer is only I £*/sq. The change of sheet Rho difference ma reverse the effect ©f thermal treatment on the thickness of the resulting porons silicon, f § 1.55] In p c tfce, the manufacture of porou silicon can take advantage of the dependence of porous silicon properties on the substrate condition before stain etching, or other techniques used i creating porous silicon layers. In particular, the surface conditions (PSO layer, imparities, etc.) and the sheet ho may be employed to tune the properties of the ma«a.fact.»red porous silicon, layers.

| i 56) Table 4 below shows th conditions for creating the po ns silicon layers (labelled as "Bottom and "Bottom ^* shown hi FIG,, 10A and 1QB. The tw silicon substrates used in. FIG. ICIA arai FIG. 10B are etched back b 20 nm, between the 5f}~100 ntu eteh-haok in BIOS. 8A-8B and the 5-l!l m elcb-baekin FIGS. 9A-¾, The sheet Rho (and the difference of sheet Rh within the group) alter the etch back (-81-15 Ω sq) is also between: the sheet Rh listed in Table 2 (-132-140 il soj and the sheet Rise listed to. Table 3 (-69-10 i¾/sqk

|;0I57| The resultin potons silicon 1001 and l(W2 dfcwtrin FIGS. IDA and 1. OB, respectively, More specifically, the thickness of the porous silicon layers 1012 arid 1022, in ..general is between the t cfcness shown in FIGS, 8A-8B and FIGS. 9A-9B. l« ltloi tl¾et » i ^: tfoati«¾ai is this example tends to Increase the th ckness of the resulting porous silicon layer, hut the percentage: o increase G 12%) ^" is imxtt smaller eonipared to the percentage esf increase in FIGS, ¾A-f 8 (-50%).

|0iSf| Table 5 below shows the conditions for creating the porous silicon, layers shown m FIG, 1 1 A d I I B , la these tw s mples, the etch-back is greater than any of the previoos samples shown in FIGS. 8A-8B, as indicated by the sheet Rho after etcli ^» baek 60 il?sq). The resulting porous silicon layers 1 1 12 and 1 122 arc accordingly thicker.

Table 5 ^■ ··· Conditions for creating the porous silicon l ers shown In FIGS, HA aad 1 IB

10139] Tabl 4 and Table § in eombhiatio with, the resulting porons silicon layers shown m FIGS,. 1OA-10B and FIGS. Π Α- ! S B. can qualitatively indicate of the influence of eich-baek on. the thickness of the resakhrg porous silicon. In general, deeper etch-hack (or higher sheet Rho after the etch-back) results ¾ thicker porous silicon la e s, given that other conditions are the same. Moreover, with higher sheet Rho, thermal treatments tend to decrease the thicknes of the resulting, porous silicon, while with lower sheet Rho, thermal ireainiersts have the opposite effect, i.e. increasing the resulting thickness. The threshold value of sheet Iho may be aronnd -81^5 IWs , above which thermal treatments decrease the thicknes of the resulting porous silicon i avers.

|0lii FFGS. 12AG2D show pnrnns silicon layers (fiirns) fabricated by anot er stain etchin technique. In this stain etching technique, the etching: s lution includes approdmarely 0.03% HiC , 2-4% %S ¾> 2-8% HF, 0, 1 -1.8% of surfactant such, as ammonium lauryl Mf (AL¾ and balance BjO. The urfacta t, in general, can lower the surface tension between the etching solution and t surface of the silicon substrate, thereby improving the cherry eal reaction between the etching solution and silicon in the substrate.

I SI 1 FIG, J 2A shows .-an SE imag of a porous silicon layer created from a silicon s bstra a an etching solution inc luding 1 ,6% IP. The .silicon substrate has a 100 Cl sq etch- back before being exposed to the etching solution, FIG, 12B shows a 2oom n image of the porous silicon shown n FIG. 12A, in comparison, BO. 12C shows ¾ or us silicon layer created from, a. same silicon substrate (with KM ⁾ O/ q eteh~ha.ck), but the etching solution used In FIG, !2€ contains 10% FFF acid. A zoom-in image of the orous silicon in FIG. 12C is shown in FIG. 12D, it can be seen that a higher concentration of FIF acid in the etching solution tends to increase the porosity of the resulting porous silicon, given that other conditions are substantially the same ,

01621 !ar Cells tocMlng ^' Porous Silicon Layers

p1.63| FIGS. .!3A~i.3€ show photos of solar ceils treated by three different techniques, FIG, 13A shows a photo of a solar cell (baselin e solar cell), on which no etch-baek is performed:, The performane-e of this solar cell functions as a baseline, with respect to which the performance of the other two solar cel ls is compared. FIG. 13B shows a photo of a solar cell processed by a siain-eiching salutio.ru which can remove surface dead layers, clean PSG layers, and create porou silicon films in single step. able 6 below shows a detailed list of parameters used in one example. The stain etching solution contains 0.2% BP, .1 , 1%: B€L 0,008% oxidant, and corresponding percentage of balance water. The process time is 84 seconds, after which, the sheet Rho increases fia>rn 72 Ω sq to 89 Ω sq, FIG, 13C shows a photo of a solar cell processed HF and oz e (ί¾ . la operation, 6 can oxidfee the SI surface and the FIF then removes the oxidized product (e.g, _> SiOj), About 20 Qtsq of etch-back is achieved after the processing using HF/Q.3, However,, «© porous si I icon is ex ected to be created by IIF/CK solution.

HP Conceafration 0.2 %

mCI Cm mimikm 1.1%

Mamt C mu 0, )68 %

Prscess T me 84 s

nitial S&eetK&n (av age) 72 O/sq

ilial Sheet Rise ^' (Average) §9 0/s

Table 6 - Processing parameters for solar cells shown in. PIG. :1 B

1016 1 FIG. I4A shows 1-V curves of the three solar cells in FIGS. I3A-J3C. F G. 14B shows fill f ctors (FF) with respect to series resistance (R _s ) of the three solar cells hi FIGS. i3A~I3€. in general, the solar cell processed by tairs etching solution display a higher short circuit enrrent I¾ with respect to open circuit voltage ¥„ _e > The fill factorof the solar cell processed by the stain etching solution is slightly lower compared to that of the baseline solar cell, but the difterenee is negligible and can be well compensated b the Increase in- l _se , in both FIGS. 14A and ! 4B , the perforrnaBoe of the solar ceil processed by the stai etching solntion is ^" better thari that of the solar cell processed By :HF/0j, Considering that the difference between, these two solar cells is the presence ( r absence) of porous silicon, layer on the front surface, it ca be confirmed that tbe porous silicon layer can noticeably improve the performance of a solar cell . ί€5} FIG . i 5 shows measured contact resistivity of solar ceils proeessed b the stain etching solution and. the baseline solar cells. Contac resistivi t of sola ceils processed by HP ®-* is not incirsded here because these cell have a much higher resistivity and lower fill factor (see FIG. I4B). For each sample, group, at least two samples are included I the measurement For each sample in. the sample group*, multiple measurements are performed at different locations on the sample to ealeaiate an. average value lo comparison. In. general,, solar cells processed by the stain, etching soluf k>n have a higher contact resistivity, but the contact resistivity is still in a egi n that is practicall uselul in applications,

|§I66] FIGS. 16A~ l.b€ show measurements of reverse saturation current densit , 1 sun implied V _¾ , and, lliehme of the three groups of solar cells show In FIGS. Ι3Α-Ι3Β, In FIGS, 16A-16C (on. the x-ajds), group 1 represents solar cells processed by the stain etching solution, group 3 represents solar cell processed by OF/Cb, and group 4 represents baseline solar cell (n etch -back ).

3¾. fi 67} FIG. .16Λ sho s tne nred reverse saturation current density ¾ of Urc three groups of solar c lls s o n in FIGS. 13A-13C. In general ¾ is a measure of the leakage for

recombination) of minority m across tire --n junetioo in reverse bias. This leakage ean be a result of eaixier recombifiatiori i«, the neutral regions on . ither side of the junction. Therefore, can control the vaiue of o en circuit voltage -V^ I solar ceils. Since: minority carriers are typically generated through ihem ! effect, ¾ can e dependent on tenv erature eharrges. In general a lower can Indicate a better periwrnauee of the corresponding solar ceil Tire reverse saturation evitfo ft density of group I„ on average, is the lowest among the three gro¾ps, indicating that eieh^b&ck mi. pcumrs silicon layers rosy contribute to the decrease of J ₀ .

|0i68| FIG. loB shows implied opesi circuit voltage V^- t one sua of theihtee groups of solar cells shown in FIGS. ! 3A- 13€. Implied ¥ _< > _e is derived from the carrier eoneeairaflorp instead of direct measur ment. Solar cells processed by the .stain etching solution shows -a. lower Con average) implied V^, and a larger finctnaiion among data points,

1:01 »} FIG. .16€ shows lifetime of the thre groups of solar cells shown in FIGS, 1.3 A- 13C. In this meaat emem, solar cells processed by the stairs etching s lution are comparable to baseline solar cells, both of which have a shorter lifetime than that of the solar cells processed, by HF/Qj. 10171?} Stain Efc ag Solutions Used in Forotft Silicon Creation

fffl 71} There are a least two types of solution th&t can be used to create porous silicon i¼.m silicon, sobstrrips. The first sohAioa (referred to as IIF-Hi trie: solution) eontaift HP acid and Nitric Acid (Η 0 ₃ ) ₅ and the second solution (referred to as HF-IICi) contains iIF _s HO, and Oxidant (HIO5), but does not contain, any Ni ric acid. FIGS. 17A-47E show cor am n of properties of solar ceil including porous silicon layers created by these t¾¾ s Sulions,

Samples DI BP BCi ox Nitric Agitation Light

(mL) uni.l (mL) (s) Acid { Ri>M >

i l.)

3 125 ¾3 .0 0 42 155 " LIGHT ^'

125 8 0 0 42 555 LIGHT

3 125 8 0 0 42 155 LIGHT

4 125 83 0 0 42 155 .LIGHT

s 125 S3 0 9 42 155 LIGHT

6 125 83 0 0 42 1.55 LIGHT

7 .125 83 0 0 42 1,55 LIGHT

8 125 83 0 0 42 155 LIGHT ^"

Table ? ···· Conditions fbrcreatiug omus sljicoft via HF-N c solution Samples Df HP eci OX Nitric- Agitation Light

(mL) {ml,} (mL) Ae.kl (R Tv!)

(mL)

I 210 33 7 0 155 LIGHT

210 33 7 0 Λ 0 155 LIGHT

3 210 33 7 0.1 0 155 LIGHT

4 210 33 7 O. i i§§ LIGHT

5 210 33 ? 0. 1 0 155 LIGHT

6 210 33 ? 0.1 0 155 LIGHT

7 210 33 ? 0.1 155 LIGHT

b' 210 33 7 0.1 155 LIGHT

9 210 33 7 0.1 15 _. 5 LIGHT

10 210 33 7 0.1 0 15.5 LIGHT ^'

Tabic 8— Cendit ons for creating porous silicon via BF-T1CI solution f 0l?2| Table 7 and Table summarize eooipesite of solutions used in re arin _. the sample solar .cells -compared in FIGS. 1.7A-I7E. An. exem lary BF-M e solution includes 125 mL de- ionize water, S3 mL IIP acid, and 42 mi, Nitric Acid. In comparison, an exemplary HF-BCl solution includes .210 mL d.e onized water, 3 mL HE acid, 7 rnL HCh <«* 0.1 gram- oxidan (!:!!<¾ in. solid state).. n addition, when fabricating the po« us silicon, both solutions are agitated % a shaker at 155 RPM and under ambient room light conditions. Same silicon substrates, which bave a bare sheet Mto of 73 Π/sq, ate used in. these two solutions.

Ill 731 Table 9 and Table 10 Felow show responses of the silicon substrates: to the HF-NrSric solution and HF-HCI solution, respectively. The responses include the sheet resistance, color, and lifetime of the silicon, substrates after being processed in the two solutions for -about 13 seconds.

J¾!?4) FIG. 17 A shows, the sheet resistance PJio of silicon substrates before and after the processing in HF-Miric solution: and FiP-HCi solution.. Among the four groups (two gronps of data points of silicon siibstrstes before processing are o verlapping) , on average, silicon substrates alter processing: in. HF-HCI solution results is the highest sheet Rho, Stain etening In either HF- Uiitk solonon or MF~RP solution, can. increase the sheet resistance Rho by nearly 50%, depending, for example, on the etching time and composition of the etc ing so!atlon (e.g., percentage of HF or oxidants). However, the sheet resistance increase induced in HF~HCi solatiou is much more rep oducible ^■■ among different samples m the group. The fiuctuaiioo of ^■ sheet resistance after processing in BF-HCI so io is less than 3 olim/sq, or ^' %%. tu contrast, the fluctuation of sheet resistance ater processing ia BF-N ic solution ean fee as large as 20 o &% or 20%, Therefore, in practice,: rocessing in HF-HC1 solution can have a better reproducibility in the resulting roducts-.

i¾l?5] FIG. 178 shows !i rae of silicon substrates before and after processing is. HF- itric solution and BF-HCl solution. Moreover, silicon substrates after glebing in the two solutions are further fed at 400 °C.

ftl76) The starting silicon subst ates have substantially th : same charge carrier isle time ^' efore ^' an processing, and the ftnetuaiion among data points are negligible, After processing in the etching s lution, silicon s ks rates processed by the HF-HCT solution, on average, ^' have a slightly shorter hfetirae, compared to silieon s bstra es processed by the HF-N e solution. However, fluctuation among data points in t he BF- ^' HCl group is very small, while the corresponding fluctuation in the HF- itric solution is noticeably larger. Thermal treatment also reverses the relative magnitude of lifetime ^■ between the two groups - after therraai treatment, silicon substrates in the HF-HCI group have longer lifetime. Therefore, in practice. Including a firing treamte in solar cell manufacturing can he beneficial .

a e - arameters o porous s con create v a - so ut on f ¾ I ?7| Table ! and 1 able 12: sumtmrrfee parameter of the pow silicon crested b die BP- krie solution and F _^ HCI so!utioa, tespectkeiy. Data, listed in Ta e 11 and Table 12 is visually shown m HO. 17C-I7E,

f 1178] FIG. 17€ shows thickness of die potts s silico layer created on silicon substrates: vt& HF~Ritrie solution and HF~H€i solution. On ave e porous silicon layers created _: foy HF-H l solution ms a larger thickness _* compared to porous silicon, layers created % HFdSbirle sohniorL At certain points (e.g.,, ample pdrst J , 5, or b), the diffbreric eaa be as large as oio.re than diree times. lids indicates that using HF-HCl solution to create porous silicon layers can go deeper into the silicon substrate mikm the same time compared to using HF-Nitric solution,

flh! 79) Moreover, the relative fluctuation (percentage change} among data points In the HP- Nitric group is also larger, More specifically, the thickest porous silicon layer created by HF- Nitric solution, is abou t six times ^' thicker than the thinnest porous silicon layer created by the same solution under th same conditions. In contrast, die thickest porous silicon layer created by HF-HCI solution is .only about three times thicker than the thinnest porous silicon layer created by the same solution. Therefore, HF-HCl solution nmy benefit the reproducibility of the resulting porous silicon layers in practice.

f il \ F G. .17D shows porosity of the porous silicon layer created on silicon substrates via HF-Nitric solution and HF-BC1 solution. On average, porosity of the porous silicon layers created by HF-HC! is higher, compared to porosity of porous silicon layers created b HF- iric solution. At certain, pohits (e,g., sample poin 31, the dif&rence can be as large as two: times. Therefore, HF-HCl solution etches the silicon substrate n: a more thorough manner, he. at the same depth, ^' HF-HCi sol ution etches away more silicon.

|»1 } Combining HQ, 17C and FIG. 17:0, it ean be seen that using BF~HCI solution to c eate: porous silicon, can be more efficient hi both vertical direction and lateral direction, in vertical direction, HF-HCI solution can etch deeper Into the silicon substrate, in lateral direction, the HP- HCi solution can etch the stliePa substrate more d^oroughly,

[ΘΙ ^{' '} ] FIG. 17B shows goodness of fit (G0F) of the resulting porous silicon to theoretical model. Measure o goodness of fit typically summarise the discrepancy between observed values and the values expected under the model in question. Therefore, a higher GOF can indicate a more predictable quality of the porous silicon. In FIG. I7£, porous silicon created by :HF-H I. solution on avemgs, has a h¾r GOF, thereby indicating a higher predictability. Moreover, the fluctuation ainong data points within the BF-HC! group is also smaller. Ill contrast, two data points in the HF-Nitde group are significantly far away from the test of the oitUs within tbe satne group* indicating p0ss#iy:abnorrnal properties of the porous silicon,: Accordingly, using HF-HCI solution can create more: predictable porous silicon from silicon substrates, which ca ^' he beneficial n practical manufecturing.

f»lB3j FIGS. 18A-I 8C are SEM images of three sample silicon substrates processed by FiF- Nitrie solutions. Parameter used in Ikbricafeg these substrates including porous silicon layers are the same. However, the resulting silicon substrates are noticeably different. First of all, he thickness: can be fluctuating, from about 10 nm to as large as 35 s«i I addition, a visual inspection of the three sample silicon substrates also indicate that the porosity among the three samples may also be different. The silicon substrate shown la FIG. 18Λ seems; to have larger porosity than that shown In FIG. 1 SC. Therefore,: in practice, if reproducibility is of primary: interest in manufacturing solar cells, or other semiconductor ap aratus Including porous silicon layers, it can be beneficial to use solution containing HF and. PIC!, instead of HMC¾.

IM ] Thermal Treaim rsis in Porous Silico Create

101851 FIGS. .19A~ 19B show peribnrmnce of sample solar cells in terms ofV^. aad-I^, respectively, In each figure, the kft most m le a baseline sample, and the rest of the samples -S«J prepared under different firing conditions. FIG. Ϊ9Α shows that firing the solar cell at a temperature 2b. degrees lower than the baseline firing temperature can result in a high open circuit voltage FIG. 19B sho s, that the same firing condition (20 degrees lower than the baseline temperature) ean also result hi a high short circuit current L _c , Under this .-firin condition, the improves f½m about 0.616 V at: baseline to about 0.624 V, and the I _se improves from, about: 8.85 A at baseline to about 8.93 A.

Ι»Ι86| FI S. 2 A-30D stew perfomranees of sample solar cells fabricated under different firing temperatures. At each temperature; ¾¾> aola cell samples are fabricated and tested. Same silicon substrates are used in ail samples shown in FI0S. 20A-20D, FiG, 20A shows the short circuit current density 3;¾ as a function of peak firing temperature. In general, within th tested temperature window (i,e, 8SQ ^{, <J} C - 910 ^' '€), lower firing temperature is beneficial in achieving a higher j _¾ . More specifically, at 853 ^* £,· the measured Jss is around 37.65 n A cm" on average of the two data points, in contrast at 90S ¾, hut measured isc is around 37,4 mA/en . Jftl B7J HQ. 20B ste s thfe op¾n circuit voltage V _iW wit respec t the ^" Mn temperature. ^' V a 855 ¾ to 0,629 V at 905 ^a €.

10188 FIG. 20C shows the fill factor (FFj of solar cells as & fimctloo of the firing temperature used.1B t¥bricai g the solar cells. The geftofcal treed is opposite to the treed in previous two figures. As the temperature increases from 855 *C to 0 5 °C _S the fill factor also increases, froru about 78.97% to about 79.2%.

F G. 20D shows the energy cauversinn. efficiency (from optical energ to electrical energy) of solar cells s function of the firing temperature, used in fi¾brieatkg the solar cells, ¾ FIG, 20D ₅ the energy conversion efficiency decreases as the firing temperature increases. At 850 °C _S the conversion efficiency is close to 18.77%·. At 905 *€, the conversion efficiency drops to less than I8,f?25%,

£01 £8] FIGS. 20A-20D also show a consisten t observation that solar cells processed under a lower firing temperature cars !mve more . fluctuating performances, i.e. the stability of performance is poorer. For example, the of the two sample sola cell, fired at 855 ^'' C fluctuates between less iten 0.6305 V and mere t aa.0,632 V ₅ inducing -a dif&renee of more than 0,015 V between, the two samples. In contrast, at 90S ^;<> € ₉ the ν _<* difference between the two samples is negligible. Therefore, in practice the firing temperatiire may be set depending on application need, such, as .reproducibility of the products, highest possible ¾, FF, or energy conversion et&ieoey. among others. The optimal condition aybe tradeoff between.•different constraints.

91] iG. 2ί Siimma ixes erfermanees: of solar cells with respeet t three pafarnetets: metal pastes (electrodes to; transport electrical energy out of the solar cell), firin temperature, and anttreilectiou/passiYstion coating, Metal pastes used in the sam les include commercially available silver pastes SOL9 1 1 , SOL9600A and SOLOCiOOB torn Heraeus Freeloos Metals em e & Co. KG,: Firing teameratures used here range from. 70 ¾ to 920 ¾, The firing temperature, in operation. ca¾ affect the contact between the metal electrodes and the silicon substrate, ihere mflneneing me ability of charge carrier transport across the rnetaF

semiconductor interface and the resulting solar eel! pesibrmance. The antirefieetion/passivat!Dn layer includes either Sl ^' Nx coating or SH¾ coating. The overall best result is achieved in solar cells fired at 920 with SOL9600B paste and a SiOj passivation layer, However, in. terms of ^: V * and the best result is achieved in solar cells fired at 870 ¾ with: SQL 9411 - paste and SrO _¾ passivation layer, FIG. 18 Indicates that a global op misatio (optimization of more than one parameter! ma be seeded m order to. achieve desired performances of solar cells,

{lil®2\ FiGS. 22A-22G show performances of sola eeils before firing and after firing. I each condition (before after firing}, the. implied of solar cells with respect to the amount of eicli- baek is _; also Shewft, FIG. 22Ά shows the implied V _i>e : of solar cells before firing, In general, as the silicon substrates are etched back by a larger amount (e.g., f om no etch -back to 60 A¼j}» the sprea d of implied Υ _¾: increases, indicatin a more fluctuating beha vior among different solar ceils, Simitar tread can he also seers, in FIG. 22B* which shows the implied of sol ar cells after firing. Comparing FIGS. I9A and 198, it can be seen that the firing treatment, in -general, increases the implied ^' W This effect can he also seen in FIG, 22€, in which the implied after firing is plotted against the implied. V _iie before, firing. For each efore firing in FIG, 22C _S the corresponding V after firing is normally larger,

|;0! \ FIG. 23 shows the effect of plasma enhanced chemical vapor deposition (PECVD) on the implied V«e _. of the result ing hr cells. The three greops of solar cells are trea ted by FECVO a different conditions, under which, the PECVD deposits a SiNx layer on the solar cells for antirefiechort and passivation purposes. Within the 95% confidence level* as shown by the circle on the right of FIG, 23, the. PECVD seem to have negligi ble eflec on the im e V of the resulting sokr cells. This may be attributed o the fact that the porous silicon layers in these solar ceils alread hs sufficient, antireifection eflect, Alternariveb/, or in addition, porou silicon layers in the combination of SiNx and porons silicon as antirefieeiion coatings play a dominant role, such that the variation of SiNx properties introdnces negligible effect.

|0Ϊ 94{ Sarfoeiaui lit Porous Silicon Creation

J#I 95] FIGS, 24Ά-24Β show the effect of sur&ehmt level in the solution on the implied Y _t>e of the resulting solar cells. The s ltition used in FIGS. 24A--24B contains FlF, BIO¾ H¾S0 _4? and serfaetast (ALS), FIG. 23 s o s the eteh-baek conditions of each group (Bom group A to group Ft). Generally, the eight groups can be divided into two categories, one category with about I S a¾if of etch-back, and the other category with 60 Ω«¾ of etch-back. PIG, 24B shows the implied V _i¾ . of solar cells created with stain etching solution including different percentage of HF and AL& surfactant. The best result is achieved when 10% BF and 0.005% ALS -surfactant is included in the stain etching solution and the etch- back is 60 O sq. This data point is noticeably Better than the test of the -data po Indicating that certain: threshold may be overcome. For example, tEe por sit may be over certain threshold such that the enlarged band gap has better passivation effect.

li &l FIG. 25 shows the averaged implied V« of solar ceils sho a in FIG. 24B, At tower HF coneesrtrations (1 ,6%), adding sut&etant to the solution tends t decrease the: imp lied Vise, In contrast, at higher HF concentrations (1 Q% t e trend is opposite; adding snr faefant tends to increase the implied Y _oe .. Bo ever, these two different trends may also be . ^■ attributed to the different mo-UB ofsBi Qtsatiivtbe stain etching solution: 0,2% snrfaciaut tends to decrease the implied ¥ _<ltf while 0.005% surfactant tends to increase the Y ^' _;¾ ,

ffl Tj Conclusion

|01 8| While various inventive embodiment have bee described, and illustrate herein, those of ordinary sk ll in the art will readily envision a variety of other means and or structures for perfbmring the inaction, and/or obtaining the results and/or one or more of the advantages described: herein., and each, of such variations an d/or modi fications: is deemed to be wittea the scope of the inventive embodiments described herein. More generally, those skilled in the art will readil appreci te that all parameters, dimensions, materials, and configurations described herein are meant to be exemplary and that the actual, parameters, dimensions, materials, and/or configurations will depend, upon the specific application or applications for which the inventive teachings is/are used, Those skilled In the art will ecognise, or be able t ascertain using no more tha routine experimentation., many equivalents to the specific inventive embodiments described herein, it is, therefore, to be understood that; the foregoing embodiments are presented by way of example: only and thai, within the scope of die appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed, Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and/or method described herein. In addition, any combination of two or more such features, systems, articles, materials, kits, and/or methods, if such features, systems, articles, materials,. kits, and/or methods am not mutually inconsistent, is Ineioded within the inventi e scope/: of the present disclosure .

fill ^s * The above-described embodiments can be implemented: in any of numerous ways. For example, embodiments of designing and making the coupling structures and diffi-acti ve optical elemeuis disclosed herein may be implemented using hardware, software or a combination thereo When iB¾ ft¾eatei! -k software, the sofovare code c-aft be executed on any siutable processor: or collection of processors, whether provided in a single computer or distributed among multiple computers.

(0288 Further, it should be appreciated thai a computer may be embodied in any of a n urnber of forms, such as a rack-mounted computer, a desktop computer, a laptop computer,: or a tablet boiHjmier. Additionally, a computer may be embedded a device not generally regarded as a computer but with suitable processing capabilities, iaciudmg a Personal Digi al Asskiant (PDA), a smart phone or any other suitable portable or feed eiectraoie device.

Also, a computet may have one or more input and output devices. These devices ears be used, among other things, to present a oser interface. Examples of output devices that can be used to. provide a user interface Include prmiers or display screens ibr visual presentation of output and speakers or other sound generating devices for audible presentation of .outpu

Examples ofinpyt devices thai can be used for a user kter&ee include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As anothe example, a computer may receive input iufommtion through speech recognition or in other audible format,

|02β2 ^' | Such computers may be interconnected b one or more networks in any suitable form, including a local area, network or a wide area network, s»c¾ as an enterprise network, and intelligent network (IN) or the internet. Such networks may be based on an suitable technology and ^' ma operate according to any suitable protocol and may include wireless networks, wired networks or fiber optic networks.

f §2&3 The various method or processes (e.g.. of designing and making the coupling structures and dlfl cbve optica! elements disclosed above} o tline herein ma be coded as software that i eseeniable on. one or more processors that employ any one of a variety of operating systems or platforms. Addi tionally , such software may be written using any of a number of suitable programming languages and/or programming or seripimg tools, and also may be compiled as execm&bfe machine language code or mtermediaie code that is executed on ia f tne ork or virtual machine.

(0284} In this respect, various inventi e concepts may be embodied as a computer readable storage medium (or multiple computer readable storage media) (e.g., a computer memory-, one or more floppy discs, compact discs, optical discs, magnetic tapes, fiasb memories, circuit configurations in Field Progt¾ntm-abls Gate Arrays or other semiconductor devices, or -other non.- trm i j medium ortangible computet storage ^ u ) encoded wl¾ one or more programs thai, when executed on one or more computers or other processors, .perform methods that imple ent the -var ous embodimen s of the invention discussed above. The computer readable medium or media cart be transportable, such thai tbe program or programs stored thereon can he loaded onto one or more different computers or other processors to implement various aspects the present invention as discussed above,

|0285 The terms "program" or "software" are used erein in. a generic sense to refer to any type of computer code or set of computer- executable instructions that can be employed to program a computer or other processor to implement various aspects of embodiments as discussed above, Additionally, it should be appreciated tha according- to one aspect, one or more computer programs that when executed perform methods of the present invention need, not reside on a single computer or processor, but may fee distributed in a. modular fashion, amongst a number of different computers or processors to implement various aspects of the present invention,

f $W6\ Computer-executable Instructions .may fee in. many forms, such, as pro ra modules, executed by one or more compaiers-or other devices, ©eneraily, program modules include routines, programs objects, components, data structures, etc, that- perform, particular lasfos or implement particular abstract data types. Typically the functionality of the program modules may be comb ed or distributed as desired In variola embodiments,

{0267] Also, data structures may be stored I computer-readable media in any siutafole form:. ■For simplicity of illustration, data structures may be shown t have fields that are related through location in the data structure. Such relationships may likewise foe achieved by assigning storage ferine fields with locations in a con5puter-reada¾le medium, that convey relationship betwee the fields. However, any suitable mechanism may be used to establish a relationship between information, inllelds of a data structure, including duOugh the use of pointers, tag or other mechanisms that: establish relationship between data elements,

|§208] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed, as partof the method may be ordered in any suitable way. Accordingly, embodiments may be constructed In which acts are performe in an. order drflereni tha illustrated, -which may include perfo ming some acts shiiultaneously, even thoogh sho n as. sequential, acts in illustra ive embodiments.

All definitions, as define md used herein, should Be understood to control over dictionary definitions, definitions in documents incorporated by reference, anel¾ ordinary meanings of the; defined terms..

|02II | The indefinite articles "si" and ¾ as used herein in the ^' salific tion and i the.

claims, unless clearly indicated to th contrary, should be understood to mean. ^u at least one,' ⁵

$211 J The phrase "and/or," as used herein in the specification d in tile claims, should he understood 1» mean "either or both" of the elements so conjoined, .he., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with "and/o ' should be construed in the same fashion, i.e., "one or more" of the elements so conjoined. Other elements may optionally be presen , other than the elements .specifically identified b the '"aad o ^* clause, whether related or unrelated to those elements specifically identified. Thus, a non-Hntiting example, a reference to "A. and/or B" when used in conjunction with open-ended language such as "comprising" can refer, in one embodiment, to A only (optionally including elements other than B): in another embodiment, to B onl (optionally including elements other than A); in yet another embodime t:, to both A and .8 (optionally including other elements);; etc,

102121 As used herein in the specification and. i the cl m _* "or" should, be understood to have the same meaning as " nd r" as defined above. For exa le, when separating items in a list, "of or ¾nd/oh ^! shall, he interpreted as being inchrsive, he,, the inclusion of at least one, but also including ffiors than one, of a number r list of elements, and. optionally, additional unlisted items. Only terms clearly indicated to the contmry, such as "only one of or "exactly one of," or, when used, in the claims, "consisting of'' will refer to the inclusion of exactl QJ¾¾ element of a number or list of elements. In general, the term "of as u ed^ herein shall only be interpreted as indicating exclusive alternatives the. "one or the other hut not both' ^* ) when preceded by terms ©f exclusivity, such as ¾thetf ' "one of/" "only one of," or "exactly one of" "Consisting essentially off ' when used in the claims, shall have its ordinary meaning as used in the field of paten t law. 102131 As used here n ti\ the specification «o4 in tfce claims, t¾6 phrase "at k in reference: to a list e<f one or more elentents, should be understood to mean at least on element selected fi'OBi »y arte or mor of the elements i he list of elemen ts, but not necessarily including at least one of each and every element specifically listed within the list of elements and not esel udlng any combinations of elements i tire fist of elements. This definition also aito s that elements ma optionally be present other than the elements spees&aily Identified within the list of demerits to which the phrase "at Least one" refers, whether related or unrelated i& those elements specificall identified. T!nrs, as a non-limi tmg example, " t least one of A and B" (or, eqmvalentiy, "at least one: of A or B," or, e uivalently "at l east one of A and/or B") can refer, in one embodiment, to at least e _* optionally including more than one. A, with no B present (and optional iy including elements other than B); in another embodiment, t at. least one, optionally including more than one, B ₅ with no A present land optionall including elements othe than A); in yet anot er embodiment to at least one, optionally including more than o e. A, and at least one, optionally including more than, o e, B (and optionally including other elements}; etc. Θ214| In. die claims, as well as in the specification above, ail transitional phrases s icu s "ootnprisiugf ' "including, ⁵⁵ "carrying," "having," "containing," 'Involving," "holding,"

"composed, of," and the like are to be understood to be open-ended, i.e., to mean including hut u«t limited to. Only the tmnsiiional phrases ^onsisiing f and "consisting essentially of ^! shall be closed or semi-closed transitional |tsrases, respectively, as: set f rth in the United Sta es Patent Office Manual of Patent Examining Procedures, Section. 2111 ,03.