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Title:
SILICON INTEGRATED, OUT-OF-PLANE HEAT FLUX THERMOELECTRIC GENERATOR
Document Type and Number:
WIPO Patent Application WO/2016/046713
Kind Code:
A1
Abstract:
Enhanced electrical yield is achieved with an integrated thermoelectric generator (i TEG) of out-of-plane heat flux configuration on a substrate wafer (1) having hill-top junction metal contacts (7) and valley-bottom junction metal contacts (6) joining juxtaposed ends of segments (4, 5), alternately p-doped and n-doped, of defined thin film lines of segments of a polycrystalline semiconductor, extending over inclined opposite flanks of hills (3) of a material of lower thermal conductivity than the thermal conductivity of the thermoelectrically active polycrystalline semiconductor, by keeping void the valleys spaces (V) among the hills(3) and delimited at the top by a planar electrically non conductive cover (8) with metal bond pads (10) defined over the coupling surface, adapted to bond with respective hill-top junction metal contacts (7). The junction metal contacts (6, 7) have a cross sectional profile of low aspect ratio, with two arms or wings overlapping the juxtaposed end portions of the segments. Preferably the inner void is evacuated upon packaging the iTEG.

Inventors:
MASCOLO, Danilo (Via S. Vitale 33, Bologna BO, I-40125, IT)
BUOSCIOLO, Antonietta (Via Santa Regina 25, Ariano Irpino AV, I-83031, IT)
LATESSA, Giuseppe (Via Emilio Gallori 43, Roma RM, I-00133, IT)
PUCKER, Georg (Via Spolverine 72, Pergine Valsugana TN, I-38057, IT)
GHULINYAN, Mher (Via Salterio 18, Melta di Gardolo TN, I-38121, IT)
DI MARCO, Simone (Via Del Terzolle 11, Firenze FI, I-50127, IT)
Application Number:
IB2015/057194
Publication Date:
March 31, 2016
Filing Date:
September 18, 2015
Export Citation:
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Assignee:
CONSORZIO DELTA TI RESEARCH (Via Vittor Pisani 16, Milano MI, I-20124, IT)
International Classes:
H01L27/16; H01L35/32
Domestic Patent References:
WO2009100809A22009-08-20
WO2009125317A22009-10-15
WO2011007241A12011-01-20
WO2011073142A12011-06-23
Foreign References:
JPH10303469A1998-11-13
US20060102223A12006-05-18
JPH04101472A1992-04-02
JP2005328000A2005-11-24
US7875791B22011-01-25
EP1083610A12001-03-14
US7875791B22011-01-25
US5374564A1994-12-20
Other References:
ISRAEL BONICHE: "Silicon-Micromachined Thermoelectric Generators for Power Generation from hot gas streams", THE DOCTORATE THESIS, 2010
DIANA DAVILA PINEDA, MONOLITHIC INTEGRATION OF VLS SILICON NANOWIRES INTO PLANAR THERMOELECTRIC GENERATORS, 2011
HUESGEN, T.; WOIS, P.; KOCKMANN, N.: "Design and fabrication of MEMS thermoelectric generators with high temperature efficiency", SENS. ACTUATORS A, vol. 145-146, 2008, pages 423 - 429
XIE, J.; LEE, C.; FENG, H.: "Design, fabrication and characterization of CMOS MEMS-based thermoelectric power generators", J. MICROMECH. SYST., vol. 19, 2010, pages 317 - 324
WANG, Z.; LEONOV, V.; FIORINI, P.; VAN HOOF, C.: "Realization of a wearable miniaturized thermoelectric generator for human body applications", SENS. ACTUATORS A, vol. 156, 2009, pages 95 - 102
WANG, Z.; FIORINI, P.; LEONOV, V.; VAN HOOF, C.: "Characterization and optimization of polycrystalline Si70%Ge30% for surface micromachined thermopiles in human body applications", J. MICROMECH. MICROENG., 2009
SU, J.; LEONOV, V.; GOEDBLOED, M.; VAN ANDEL, Y.; DE NOOIJER, M.C.; ELFRINK, R.; WANG, Z.; VULLERS, R.J.: "A batch process micromachined thermoelectric energy harvester: Fabrication and characterization", J. MICROMECH. MICROENG., 2010
YANG, S.M.; LEE, T.; JENG, C.A.: "Development of a thermoelectric energy harvester with thermal isolation cavity by standard CMOS process", SENS. ACTUATORS A, vol. 153, 2009, pages 244 - 250
KAO, P.-H.; SHIH, P.-J.; DAI, C.-L.; LIU, M.-C.: "Fabrication and characterization of CMOS-MEMS thermoelectric micro generators", SENSORS, vol. 10, 2010, pages 1315 - 1325
WANG, Z.; VAN ANDEL, Y.; JAMBUNATHAN, M.; LEONOV, V.; ELFRINK, R; VULLERS, J.M.: "Characterization of a bulk-micromachined membraneless in-plane thermopile", J. ELECTRON. MATER., vol. 40, 2011, pages 499 - 503
A. JACQUOT; W.L LIU; G. CHEN; J.P FLRIAL; A. DAUSCHER; B. LENOIR: "Fabrication and Modeling of an in-plane thermoelectric micro-generator", PROCEEDINGS ICT'02. 21ST INTERNATIONAL CONFERENCE ON THERMOELECTRICS, 2002, pages 561 - 564
A. I. HOCHBAUM; R. K. CHEN; R. D. DELGADO; W. J. LIANG; E. C. GARNETT; M. NAJARIAN; A. MAJUMDAR; P. D. YANG, NATURE, vol. 451, 2008, pages 163 - U5
A. I. BOUKAI; Y. BUNIMOVICH; J. TAHIR-KHELI; J.-K. YU; W. A. GODDARD III; J. R. HEATH, NATURE, vol. 451, 2008, pages 168 - 171
M. STRASSER ET AL.: "Miniaturized Thermoelectric Generators Based on Poly-Si and Poly-SiGe Surface Micromachining", THE 11TH INTERNATIONAL CONFERENCE ON SOLID-STATE SENSORS AND ACTUATORS, MUNICH, GERMANY, 10 June 2001 (2001-06-10)
"Micromachined CMOS Thermoelectric Generators as On-Chip Power Supply", THE 1IH INTERNATIONAL CONFERENCE ON SOLID-STATE SENSORS AND ACTUATORS AND MICROSYSTEMS, BOSTON, USA, 8 June 2003 (2003-06-08)
Y. S. JU; K. E. GOODSON: "Process-dependent thermal transport properties of silicon-dioxide films deposited using low-pressure chemical vapor deposition", AIP JOURNAL OF APPLIED PHYSICS, vol. 85, no. 10, pages 7130 - 7134
JEN-KAN YU; S. MITROVIC; D. THAM; J. VARGHESE; J.R. HEATH: "Nature Nanotechnology", vol. 5, October 2010, MACMILLAN PUBLISHERS LIM, article "Reduction of thermal conductivity in phononic nanomesh structures"
Attorney, Agent or Firm:
BARBARO, Gaetano et al. (Società Italiana Brevetti S.p.A, Via Carducci 8, Milano MI, I-20123, IT)
Download PDF:
Claims:
C L A I M S

1. An integrated thermoelectric generator of out-of-plane heat flux configuration on a substrate wafer (1) having hill-top junction metal contacts (7) and valley-bottom junction metal contacts (6) joining juxtaposed ends of segments (4, 5), alternately p-doped and n-doped, of defined thin film lines of segments of a polycrystalline semiconductor, extending over inclined opposite flanks of hills (3) of a material of lower thermal conductivity than the thermal conductivity of said thermoelectrically active polycrystalline semiconductor, useful for converting in electricity part of the heat flowing in a direction orthogonal to the planar generator, characterized in that

all valleys among said hills (3) are void spaces (V) delimited at the top by a planar electrically non conductive cover (8), having metal bond pads (10) defined over a coupling surface of the planar cover (8), adapted to bond with respective hill-top junction metal contacts (7).

2. The thermoelectric generator of claim 1, wherein said void spaces (V) are permanently sealed during packaging or back-end operations by occluding side gaps between the substrate wafer (1) and said planar cover (8).

3. The thermoelectric generator of claim 1 or 2, wherein said void spaces (V) are evacuated upon packaging.

4. The thermoelectric generator of claim 1, wherein said planar cover is a wafer (8) similar to the substrate wafer (1), and has a dielectric film (9) over the coupling surface that electrically insulates from one another said metal bond pads (10) defined thereon.

5. The thermoelectric generator of claim 4, wherein said substrate wafer (1) and/or said cover wafer (8) are thinned or ultra-thinned silicon crystal wafers.

6. The thermoelectric generator of claim 5, wherein said planar cover is a silicon wafer (8) similar to the substrate wafer (1), and they are bonded in alignment with a technique belonging to the group of thermo-compressive metal-to-metal bonding, plasma bonding, benzocyclobutene bonding, polymides bonding, inter-metallic compounds bonding, solid-liquid-interdiffusion (SLID) bonding, eutectic bonding, copper-to-oxide bonding ,metal-to-(metal-oxide) bonding, anodic bonding or micro- bump stacking.

7. The thermoelectric generator of claim 5, wherein the substrate silicon wafer (1) and the planar cover silicon wafer (8) are micro-machined wafers (8) bonded together by smart-cut processing or with Soitec's Smart Stacking™ layer transfer technology.

8. The thermoelectric generator of claims 6, wherein aligned bonding is carried out in chip-to-chip, chip-to-wafer or wafer-to-wafer mode, or in chip-on-wafer- on-substrate or chip-on-chip-on substrate mode.

9. The thermoelectric generator of claim 1, wherein said junction metal contacts (6, 7) have a cross sectional profile of low aspect ratio, with two arms or wings overlapping juxtaposed end portions of a p-doped and of an n-doped segment (4, 5), respectively, of a defined line (L) of segments of polycrystalline semiconductor.

10. The thermoelectric generator of claim 9, wherein said metal contacts (6, 7) are of aluminium, copper, silver or alloys thereof.

11. The thermoelectric generator of claim 8, wherein electrical contact of said overlapping metal contact arms with the polycrystalline semiconductor thin film takes place via an interfacing multi-layer comprising a film of a silicide belonging to the group composed of TiSi2, WSi2, MoSi2, PtSi2 and CoSi2.

12. The thermoelectric generator of claim 8, wherein electrical contact of said overlapping metal contact arms with the polycrystalline semiconductor thin film takes place via an interfacing multi-layer comprising an intermediate film of a refractory metal belonging to the group composed of W, Ti, Ta and a film of titanium nitride in contact with the metal.

13. The thermoelectric generator of claim 1, wherein said hills (3) are of a material belonging to the group composed of silicon oxide, silicon nitride, deposited oxides of enhanced resistance to heat conduction, nanomesh structures of phononic material, and superlattices of nanoscale thin film silicon.

14. The thermoelectric generator of claim 1, wherein said hills (3) are regularly spaced along parallel lines orthogonal to said lines of segments (4, 5) of polycrystalline semiconductor and have a truncated rectangular pyramid shape or a trapezoidal cross section along one axis and straight sides or flanks orthogonal to it.

15. The thermoelectric generator of claim 1, wherein said n-doped and p- doped thin film segments are of polycrystalline silicon.

Description:
SILICON INTEGRATED, OUT-OF-PLANE HEAT FLUX THERMOELECTRIC GENERATOR

BACKGROUND

Technical Field

This disclosure relates in general to solid state thermoelectric devices, in particular to thermoelectric generators (TEGs) amenable to be fabricated with planar processing technologies and related techniques of heterogeneous or hybrid 3D integration.

Discussion of related prior art

Thermoelectric generators (TEGs) are earnestly investigated as low enthalpy waste heat exploitation devices of outstanding robustness, reliability and virtually unlimited service life, besides being made of environmental friendly materials.

As power consumption of increasingly popular electronic devices is constantly minimized, TEGs begin to be considered as supplementary power source in conjunction or even in substitution of batteries or other energy storage devices like super-capacitors.

There is an increasing number of publications concerning thin film technology TEGs exploiting well established processing techniques developed in the Microelectronics and Micro-Electro-Mechanical-Systems (MEMSs), like planar processing, micromachining implant and post implant treatments, flip-chip and bonding techniques and alike.

The doctorate thesis "Silicon-Micromachined Thermoelectric Generators for Power Generation from hot gas streams" by Israel Boniche, University of Florida, 2010, and "Monolithic integration of VLS silicon nanowires into planar thermoelectric generators" by Diana Davila Pineda, Autonomous University of Barcelona, 2011, offer an extensive introductory review of state-of-the-art practices in the field of thermoelectric devices for solid state heat pumps and power generators.

The review encompasses also two families of TEGs manufactured with silicon- compatible micro and nano technologies: in devices of a first family heat flow is parallel and in the other family orthogonally to the substrate. The architectures of these integrated TEGs generally comprise a number of elementary cells having n-p doped legs, arranged in such a way that the elementary cells are thermally in parallel and electrically in series.

Typically, integrated TEG devices in which heat flows parallel to the substrate may have conductive legs of thermoelectncally active materials deposited over a very high thermal resistance material or a membrane, suspended several hundreds of micrometers above the substrate, or the legs of active materials themselves are freestanding [membrane-less].

Other relevant examples are reported in :

Huesgen, T.; Wois, P.; Kockmann, N. Design and fabrication of MEMS thermoelectric generators with high temperature efficiency. Sens. Actuators A 2008, 145-146, 423-

429.

Xie, J.; Lee, C; Feng, H. Design, fabrication and characterization of CMOS MEMS- based thermoelectric power generators. J. Micromech. Syst. 2010, 19, 317-324.

Wang, Z.; Leonov, V.; Fiorini, P.; van Hoof, C. Realization of a wearable miniaturized thermoelectric generator for human body applications. Sens. Actuators A 2009, 156,

95-102.

Wang, Z.; Fiorini, P.; Leonov, V.; van Hoof, C. Characterization and optimization of poly crystalline Si70%Ge30% for surface micromachined thermopiles in human body applications. J. Micromech. Microeng. 2009, doi: 10.1088/0960-1317/19/9/094011. ■ Su, J.; Leonov, V.; Goedbloed, M.; van Andel, Y.; de Nooijer, M.C.; Elfrink, R; Wang,

Z.; Vullers, R.J. A batch process micromachined thermoelectric energy harvester: Fabrication and characterization. J. Micromech. Microeng. 2010, doi: 10.1088/0960- 1317/20/10/104005.

Yang, S.M.; Lee, T.; Jeng, C.A. Development of a thermoelectric energy harvester with thermal isolation cavity by standard CMOS process. Sens. Actuators A 2009, 153, 244-

250.

Kao, P.-H; Shih, P. -J.; Dai, C.-L.; Liu, M.-C. Fabrication and characterization of CMOS-MEMS thermoelectric micro generators. Sensors 2010, 10, 1315-1325.

Wang, Z.; van Andel, Y.; Jambunathan, M.; Leonov, V.; Elfrink, R.; Vullers, J.M.

Characterization of a bulk-micromachined membrane less in-plane thermopile. J.

Electron. Mater. 2011, 40, 499-503.13. Patent US 7,875,791 B 1 "Method for manufacturing a thermopile on a membrane and a membrane-less thermopile, the thermopile thus obtained and a thermoelectric generator comprising such thermopiles" Vladimir Leonov, Paolo Fiorini, Chris Van Hoof (2011)

Miniaturized thermopile on a membrane are also described by A. Jacquot,W.L Liu, G.

Chen, , J.P Flrial, A. Dauscher, B. Lenoir, in "Fabrication and Modeling of an in-plane thermoelectric micro-generator", Proceedings ICT'02. 21st International Conference on Thermoelectrics, p. 561-564 (2002).

Other examples of parallel heat flow TEG structures rely on the ability of growing or defining populations of parallel and extremely slender conductors (nanowires) with a mean diameter of few tens of nanometers on a planar substrate of low heat conductivity and in eventually stacking tile-modules to form a thermo- electrical active septum, through which heat flows in the same direction of the parallel nanowires. The articles: "A. I. Hochbaum, R. K. Chen, R. D. Delgado, W. J. Liang, E. C. Garnett, M. Najarian, A. Majumdar, and P. D. Yang, Nature 451, 163-U5 (2008)" and "A. I. Boukai, Y. Bunimovich, J. Tahir-Kheli, J.-K. Yu, W. A. Goddard Iii, and J. R. Heath, Nature 451, 168-171 (2008)"; WO2009/125317; EP1,083,610; WO2011/007241; WO2011/073142; offer a review of practices following such an approach.

US 7,875,791 B l (by Leonov et al.) discloses thermopiles that may be supported by a membrane layer or that may be self-supporting. Despite the apparent easy manufacturability of these devices, heat is forced to move in a complicated structure with significant thermal losses. In addition, in some cases adhesive are needed in order to assure thermal contact to a heat source at the top or the bottom surface of the initial substrate. This results in poor thermal coupling at system level, lossy thermal paths and mechanical fragilities, all features that penalize performance of the thermopile.

A second family of TEG devices is often referred to as "out-of-plane" heat flux TEGs. They are characterized by the fact that heat flows orthogonally to the substrate. In these devices the thermoelectrically active materials are usually laid on or are part of high aspect-ratio supporting structures standing onto the substrate. Despite a more sophisticated and apparently expensive fabrication process, this configuration minimizes thermal losses, simplifies thermal coupling at system level enhancing overall performance.

Being manufactured with conventional CMOS\BiCMOS\MEMs materials and processes, the "out-of-plane" heat flux TEGs are amenable to miniaturization and integration in microelectronic and optoelectronic devices, among other applications.

Examples are reported by M. Strasser et al. in "Miniaturized Thermoelectric

Generators Based on Poly-Si and Poly-SiGe Surface Micromachining", (presented in The 11 th International Conference on Solid-State Sensors and Actuators, Munich, Germany, June 10-14, 2001) and "Micromachined CMOS Thermoelectric Generators as On-Chip Power Supply" ( presented in The 12 th International Conference on Solid- State Sensors and Actuators and Microsystems, Boston, USA, June 8-12, 2003) .

Out-of-plane or orthogonal heat flux thin film structures are useful for innumerable applications, for example for micro power generation or for temperature management in complex integrated systems, for energy recovery or harvesting

Electric power yield from a given heat flow and electric power yield versus the footprint area of out-of-plane or orthogonal heat flux devices of the prior art, based on a common semiconductor or any material compatible with ICs fabrication processes, are yet poor and there is a need of more efficient and power intensive devices.

SUMMARY OF THE DISCLOSURE

A significantly increased conversion efficiency is achieved with a silicon integration compatible out-of-plane (or orthogonal) heat flux TEG having a novel "Z- device" structure as defined in the appended claims, the content of which is intended to be integral part of this description and herein incorporated by express reference.

Basically, internal by-pass heat transfer by heat conduction normally occurring through a dielectric filler, typically an oxide (e.g. silicon oxide) deposited in the valleys over defined tracts or segments of sequentially alternated p-type and n-type deposited semiconductor thin-film and over metal bridges that provide electrical continuity between juxtaposed ends of defined segments of p-type and of n-type semiconductor at valley bottom junctions, between spaced hills of generally trapezoidal cross section, over opposite slanted flanks of which lay the defined semiconductor thin-film legs of an elementary cell of a typical Z-device profile, is significantly reduced by realizing junction metal contacts of relatively low profile (i.e. low aspect ratio) and reduced encumbrance and by leaving void the valley spaces, thus no longer filled with dielectric oxide nor hosting metal bridges of high profile of electrical connection of juxtaposed ends of a p-type and an n-type leg.

Reducing internal by-pass heat transfer from hot metal junctions to cold metal junctions of a Z-device has a dominant effect on efficiency, in view of the fact that the delivered electrical power of an integrated thermoelectric generator (iTEG) besides other factors is tied to the second power of the temperature difference between the two tiers of metal contacts.

According to a preferred embodiment, the void spaces are evacuated upon packaging the finished device for substantially eliminating heat convection contribution there through to heat transfer from hot junction metal contacts to cold junction metal contacts along by-pass paths, rather than the thermoelectrically useful heat conduction paths along the semiconductor thin-film lines of the Z-device structure.

According to an aspect of the novel architecture, both the valley-bottom and hill- top junction metal contacts, connecting p-doped and n-doped thin film segments of a line of doped polycrystalline semiconductor (e.g. of heavily doped poly-Si or poly- SiGe), respectively extending over one side and the opposite side flank of every dielectric\thermal insulating hill of a line of regularly spaced hills, are in form of defined tracts of a deposited metal layer, partly overlapping the juxtaposed end portions of a p-doped and of a n-doped leg of a semiconductor thin film for connecting electrically in series alternated cold and hot thermoelectric junctions thus organized in a single or in a plurality of chains.

The hills may generally have a truncated rectangular pyramid shape or they may have a trapezoidal cross section along one axis and straight sides or flanks orthogonal to it, though other shapes including that of a truncated cone could be used.

The hills material should have a low thermal conductivity, lower than the thermal conductivity of the material of the p-type and n-type legs of material supported thereon. The hills may be of a thermally grown (e.g. a so-called locos oxide) or of a deposited layer of a material such as oxides, oxy-nitrides, silicon nitride or even of purposely formed nanometer length scale structures of phononic material such as superlattices of nanoscale thin films of silicon, eventually to be successively masked and etched under controlled etching conditions and/or in an eventually stepwise manner, in order to slant the walls of etched valleys toward a substantially flat bottom.

This shape of the junction metal contacts, as far as the valley-bottom junctions (either hot or cold relatively to coherently cold or hot hill-top junctions) are concerned, leaves interior separation spaces between adjacent hills, over the inclined flanks of which lay the thin film conductive legs of p-doped and n-doped semiconductor, substantially unobstructed for fully exploiting the reduced heat transfer afforded by the empty spaces.

These internal void spaces are closed at the top by a planar cover having metal contacts defined over a coupling surface of the planar cover, adapted to bond with respective hill-top junction metal contacts.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a cross sectional view of the elementary cell of an integrated Z-device according to a basic embodiment of this disclosure.

FIG. 2 is a fragmentary, three dimensional cross sectional view showing two lines of elementary cells of the integrated Z-device structure.

FIG. 3 shows a possible layout of parallel conductive lines of elementary cells constituting an integrated TEG module of a string of a number of cells in electrical series with connection pads to circuit.

FIG. 4 is a three dimensional view of an arrangement of the conductive parts of the integrated cells in series showing the flow path of electrical current generated by the integrated TEG device under a temperature difference between hot hill top metal junctions and cold valley bottom metal junctions.

DETAILED DESCRIPTION OF EMBODIMENTS

With reference to FIG. 1 and FIG. 2, a silicon wafer 1 is used as substrate for fabricating thereon the novel Z-device structure of an integrated TEG of out-of-plane (orthogonal) heat flux type.

Commercially available silicon wafers of any size and having a thickness generally not exceeding 675 micrometers (μπι) may be used.

A dielectric base layer 2 of substantially uniform thickness that may be generally comprised between 1 nanometer (nm) and 1 micrometer (μπι), preferably of about 10 nm, provides a necessary bottom electrical insulation without introducing a significant thermal resistance.

According to well established techniques of micro-machining processing, arrangement of spaced hills 3 of a relatively low thermal conductivity material such as, for example, of thick oxide, thermally grown or deposited over unmasked areas of a firstly grown base layer 2, up to a height that generally may be comprised between 0, 1 and 50 μπι. The typical inclined flanks of hills 3 define valleys there between, the substantially planar bottom of which generally may have a width comprised between 0, 1 and 100 μπι, most preferably between 0.2 and 50 μπι, similarly to the width of the top of the hills 3.

Alternatively, the hills 3 may be defined starting from a layer of deposited oxide or other material such as silicon nitride, through a succession of masking and etching steps, under controlled isotropic etching conditions, in order to slant the walls of the progressively etched valleys toward a substantially flat bottom by an angle of inclination from the base plane that preferably is comprised between 45 and 85 degrees.

LPCVD silicon oxide, deposited with varying amounts of phosphorous and/or hydrogen impurities and specific processing and post processing conditions promoting structural disorder (re: Y. S. Ju and K. E. Goodson," Process-dependent thermal transport properties of silicon-dioxide films deposited using low-pressure chemical vapor deposition", AIP Journal of Applied Physics, Volume 85, Number 10, 7130- 7134) is also an effective material with which hills 3 of enhanced resistance to heat conduction may be formed over the oxidized surface of the substrate wafer 1.

Yet another alternative material with which hills 3 of enhanced resistance to heat conduction with two suitably inclined opposite sides may be formed over an oxidized surface of a substrate wafer is the family of nanomesh structures of phononic silicon (re: "Reduction of thermal conductivity in phononic nanomesh structures" by Jen-Kan Yu, S. Mitrovic, D. Tham, J. Varghese and J.R. Heath, Nature Nanotechnology, Vol. 5, October 2010, ©2010 Macmillan Publishers Lim.).

The hills material should have a low thermal conductivity, significantly lower than the thermal conductivity of the material of the p-type and n-type legs of conductive material supported thereon, in order to further penalize by-pass paths of heat conduction flow alternative to the paths of productive heat conduction along the polycrystalline doped semiconductor thin film segments or legs defined over opposite slanted surfaces of the truncated rectangular pyramid shaped hills 3 or of hills with a trapezoidal cross section along one axis and straight sides or flanks orthogonal to it.

Examples of suitable materials of lower thermal conductivity than the thermal conductivity of a thermoelectrically active polycrystalline semiconductor and their respective heat conduction coefficients are reported in the following table.

Material Thickness[nm] Conductivity [W m K ]

Thermal Si02 > 250 ~ 1.2

Si02 30 -50 0.82 ± 0.02 (PECVD@300C)

Si02 90 -180 1.00 ± 0.10 (PECVD@300C)

Si02 >200 ~ 1.2 (Bulk) (PECVD@300C)

SiNx 20 -40 0.55 ± 0.05 (PECVD@300C)

SiNx 60 -120 0.65 ± 0.05 (PECVD@300C)

SiNx 180 -1.45

(APCVD@900C)

Hills 3 of a superlattice of nanoscale thin films of phononic silicon realized over a dielectric base layer on the surface of the substrate is another alternative capable of markedly reducing the thermal conductivity of the hills 3 of the integrated TEG structure.

Parallel lines of defined tracts or segments of alternately p-doped and n-doped, 4 and 5, respectively, of a polycrystalline semiconductor material such as, for example, doped Si or SiGe, deposited in form of a thin film of substantially uniform thickness over the bottom isolation dielectric 2 and the spaced hills 3, constitute the two legs of thermoelectric material that electrically connect a junction at the valley bottom to the two adjacent junctions on top of the hills 3 (i.e. a unit or elementary cell of a Z-device structure). The deposited doped polycrystalline silicon layer of the segments 4 and 5 may have thickness, generally comprised between 10 and 1000 nm, but may even be as thick as one or more micrometers, depending on contemplated applications, scaling of the elementary cell structure, properties of the polycrystalline semiconductor material used and design choices of the integrated TEG.

Physically, the cold and hot junctions, respectively at valley bottoms and at hilltops or vice versa, are both constituted by metal contacts of low aspect ratio, respectively 6 and 7, electrically bridging an interruption gap between the defined end of a p-doped segment or leg 5 and the defined end of a n-doped thermoelectric segment or leg 4 of polycrystalline thin-film semiconductor, in order to avoid formation of p-n junctions along the string of elementary integration modules or cells in series of an electrically conductive line (chain) of cells.

The deposited metal layer of the junction metal contacts 6 and 7 that extend over and in electrical contact with the end portions of the two segments 4 and 5 of polycrystalline semiconductor, for a good part of their portions laying onto the substantially planar valley bottoms and hill-tops, may have thickness ranging from about 0, 1 to about 5 μπι.

The cross sectional view of the drawing well represents the characteristic "Z profile" of the conductive legs 4 and 5 of thermo-electrically active material of the elementary cell.

Preferably, there is a multi-layer interfacing between the metal overlapping the polycrystalline semiconductor thin film to control the electrical interface resistance between the metal and the semiconductor materials thereat and eventually disproportionate electrical conductivity versus thermal conductivity for reducing heat conduction toward the metallic bulk of the metal contacts, namely, the valley bottom contacts 6 and the hill-top contacts 7. As depicted in the enlargement lens, an effective interfacing multi-layer may comprise a 1-50 nm film 6a of a silicide belonging to the group: TiSi 2 , WSi 2 , MoSi 2 , PtSi 2 and CoSi 2; in contact with the polycrystalline doped semiconductor, an intermediate 1-10 nm thick film 6b of W or Ti and a 5-30 nm thick film 6c of TiN in contact with the metal layer 6, 7 of Al or of Al-Si alloy or copper. According to a preferred embodiment of the novel integrated out-of-plane TEG structure, the void valley spaces among parallel lines or other arrangement of spaced hills 3 are closed at the top by a second wafer 8, provided with a thin dielectric layer 9 formed over a surface of the wafer to render it electrically non conductive, and over which are then defined metal bond pads 10, adapted to bond with respective hill-top metal contacts 7 according to one of the many flip-chip bonding techniques, preferably using an aligned-bonding technique of thermo-compressive metal-to-metal bonding Cu- Cu,W-W, Ti-Ti ..etc., with or without diffusion layers, after a CMP planarization, or via plasma bonding (Y-Ox/Y-Ox), PECVD Si02-Si02, benzocyclobutene (BCB) to BCB bonding. Hybrid bonding techniques such as BCB and a variety of polymers or polymides, metal layers such Ti films and inter-metallic compounds (IMCs), Cu-Sn Solid-Liquid-Interdiffusion (SLID) bonding, Au-Sn or Au-In eutectic bonding, may alternately be used as well as anodic bonding or micro-bump stacking.

Also the so-called smart-cut processing or the layer transfer technology Smart Stacking™ of Soitec, described in US Patent No. 5,374,564, may be used.

Flip-chip aligned bonding, may be carried out on whole processed wafers, from which TEG device dices are successively cut to be packaged, or alternatively on cut dices thereof. Generally, depending on the specific application, aligned bonding for realizing the TEG devices of this disclosure may be carried out in chip-to-chip, chip-to- wafer, wafer-to-wafer mode or according to chip-on-wafer-on-substrate or chip-on- chip-on-substrate approaches.

Preferably, both the top and bottom wafers may be subjected to a backside thinning process aiming to reduce the thickness of commercial wafers, after devices manufacturing, including mechanical or chemical treatments, such as mechanical grinding, dry polishing, chemical-mechanical grinding, spin etching chemical- mechanical polishing and plasma dry etching. The aim is to reduce the original thickness to less than 100 μπι or to ultrathin values of less than 40 μπι. Thinning of the wafers reduces overall thermal resistance of the integrated out-of-plane TEG structure and makes it amenable to be deployed in next generation 3D integrated circuit.

A fragmentary, three dimensional cross sectional sketch, showing the features of two lines L of elementary cells of the integrated Z-device structure may be observed in FIG. 2

The manner in which parallel electrically conductive lines of defined tracts or segments of alternately p-doped and n-doped, 4 and 5, of a semiconductor material, joined by valley-bottom and hill-top junction metal contacts 6 and 7 are created, orthogonally to array lines of spaced hills 3, may be immediately recognized.

The width of the conductive lines L may be generally comprised between 0.1 and 500 μπι, more preferably between 0.5 and 10 μπι.

A plurality of lines L of microcells are normally connected in electrical series, for example in an arrangement of a number of adjacently integrated parallel lines. FIG. 3 shows an exemplary layout of the electrically conductive parts of five parallel lines L of elementary cells, for constituting an integrated TEG module composed of a string of cells in electrical series corresponding to the sum of the number of cells of all the lines L terminating with connection pads A and B.

Connection of the adjacent ends of two lines L is realized by defining lateral metal connections 6', i.e. defining by masking and selective etching step a secondly deposited metal layer, after having removed a firstly deposited metal layer for filling the gap space between the opposed ends of the polycrystalline semiconductor legs 4 and 5 from planar surfaces.

In the tri-dimensional view of the arrangement of the conductive parts of the cells in series of FIG. 4, arrow heads describe the flow path of electrical current generated by the integrated TEG device under a temperature difference between hot hill-top metal junctions 7 and cold valley-bottom metal junctions 6.

Of course, the DC voltage produced at the terminals A and B corresponds to the sum of the DC voltage developed by every elementary series connected cell of the string.

A TEG device may include numerous modularly integrated multi-cell TEGs, each requiring two pads for connecting to one or several external circuits harvesting or exploiting the generated electrical power according to application needs. In order for one or several series/parallel networks of the plurality of monolithically integrated TEGs of a packaged device to be externally organized, the device must account for two pins for each individual integrated TEG. Therefore, an appropriate multi-TEG layout of monolithic integration, besides providing for the desired number of individually integrated TEGs must be compatible with the maximum number of pins that the packaged device may have.

Alternatively, the finished TEG device may have few output pin pairs or even be a two-pin device by choosing to maximize serialization in order to achieve a large open- circuit output voltage.




 
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