| JP2001015766 | METHOD FOR FABRICATING INSULATED GATE FIELD EFFECT SEMICONDUCTOR DEVICE |
| JP2024009540 | semiconductor equipment |
| JPH04100241 | MANUFACTURE OF SEMICONDUCTOR DEVICE |
LOCKMAN ZAINOVIA (MY)
CHUNG LEW KAM (MY)
ABDULLAH AHMAD MAKARIMI (MY)
WAHAB YUSSOF (MY)
HUTAGALUNG SABAR DERITA (MY)
LOCKMAN ZAINOVIA (MY)
CHUNG LEW KAM (MY)
ABDULLAH AHMAD MAKARIMI (MY)
WAHAB YUSSOF (MY)
| KR100740531B1 | 2007-07-18 |
MARTINEZ, J. ET AL.: "`Silicon Nanowire Transistors with a Channel Width of 4 nm Fabricated by Atomic Force Microscope Nanolithography", NANO LETTERS, vol. 8, no. 11, 1 October 2008 (2008-10-01), pages 3636 - 3659
CLEMENT, N. ET AL.: "Electronic transport properties of single-crystal silicon nanowires fabricated using an atomic force microscope", PHYSICA E, vol. 13, March 2002 (2002-03-01), pages 999 - 1002
| CLAIMS What is claimed is: 1. A process for fabricating a silicon nanowire transistor with the components of a source pad, a drain pad, a lateral gate pad, and a silicon nanowire as channel, said process comprising: providing silicon-on-insulator (SOI) wafer having a chemically reactive substrate, wherein the components of a silicon nanowire transistor are pre-designed on the substrate of the SOI wafer; patterning the substrate of the SOI wafer by local anodic oxidation using atomic force microscope (AFM) nanolithography according to the pre-designed components of the silicon nanowire transistor, thereby forming a nanoscale oxide pattern corresponding to the components of the silicon nanowire transistor on top of the substrate; etching the substrate with a basic, anisotropic chemical etchant to remove the portions of the substrate that are not covered by the nanoscale oxide pattern; and further etching the substrate with an acidic, isotropic chemical etchant to remove the nanoscale oxide pattern; whereby a complete silicon nanowire transistor is fabricated. 2. The process of claim 1, wherein the SOI is p-type. 3. The process of claim 1, wherein the chemically reactive substrate of the SOI wafer is silicon. 4. The process of claim 1 , wherein the local anodic oxidation using atomic force microscope (AFM) nanolithography uses a conductive AFM tip which operates in contact mode. 5. The process of claim 4, wherein the conductive tip is a gold-coated tip. 6. The process of claim 5, wherein when the gold-coated tip is in contact mode with the substrate, a bias voltage is applied between the tip and the substrate; thereby when the tip is moving on the top surface of the substrate, the nanoscale oxide pattern of the components of the silicon nanowire transistor is formed. 7. The process of claim 6, wherein when the bias voltage is 9 volt, the tip writing speed is όμπι/β in air humidity of 55.8%RH-68.9%RH. 8. The process of claim 1, wherein the basic, anisotropic chemical etchant is tetramethylammonium hydroxide (TMAH). 9. The process of claim 8, wherein the TMAH is 25wt% in water solution, and the etching is performed at 65°C for 20 seconds. 10. The process of claim 1, wherein the acidic, isotropic chemical etchant is hydrogen fluoride (HF). 11. The process of claim 9, wherein the HF is 2wt% in water solution, and the etching is performed for 5 seconds. 12. A silicon nanowire transistor fabricated on a silicon-on-insulator (SOI) wafer, comprising a source pad, a drain pad, a lateral gate pad, and a silicon nanowire as channel. 13. The silicon nanowire transistor of claim 12, wherein the silicon nanowire transistor is fabricated by a process comprising: providing silicon-on-insulator (SOI) wafer having a chemically reactive substrate, wherein the components of a silicon nanowire transistor are pre-designed on the substrate of the SOI wafer; patterning the substrate of the SOI wafer by local anodic oxidation using atomic force microscope (AFM) nanolithography according to the pre-designed components of the silicon nanowire transistor, thereby forming a nanoscale oxide pattern corresponding to the components of the silicon nanowire transistor on top of the substrate; etching the substrate with a basic, anisotropic chemical etchant to remove the portions of the substrate that are not covered by the nanoscale oxide partem; and further etching the substrate with an acidic, isotropic chemical etchant to remove the nanoscale oxide pattern; whereby a complete silicon nanowire transistor is fabricated. 14. The silicon nanowire transistor of claim 13, wherein the SOI is p-type. 15. The silicon nanowire transistor of claim 13, wherein the chemically reactive substrate of the SOI wafer is silicon. 16. The silicon nanowire transistor of claim 13, wherein the local anodic oxidation using atomic force microscope (AFM) nanolithography uses a conductive AFM tip which operates in contact mode. 17. The silicon nanowire transistor of claim 16, wherein the conductive tip is a gold- coated tip. 18. The silicon nanowire transistor of claim 17, wherein when the gold-coated tip is in contact mode with the substrate, a bias voltage is applied between the tip and the substrate; thereby when the tip is moving on the top surface of the substrate, the nanoscale oxide pattern of the components of the silicon nanowire transistor is formed. 19. The silicon nanowire transistor of claim 18, wherein when the bias voltage is 9 volt, the tip writing speed is όμητ/β in air humidity of 55.8%RH-68.9%RH. 20. The silicon nanowire transistor of claim 13, wherein the basic, anisotropic chemical etchant is tetramethylammonium hydroxide (TMAH). 21. The silicon nanowire transistor of claim 20, wherein the TMAH is 25wt% in water solution, and the etching is performed at 65°C for 20 seconds. 22. The silicon nanowire transistor of claim 13, wherein the acidic, isotropic chemical etchant is hydrogen fluoride (HF). 23. The silicon nanowire transistor of claim 22, wherein the HF is 2wt% in water solution, and the etching is performed for 5 seconds. |
FABRICATING THE SAME
Field of the Invention
[0001] The present invention generally relates to nanoelectronic technology, and more particularly to a silicon nanowire transistor (SiNWT) and further to a process for fabricating the SiNWT. Background of the Invention
[0002] At present, silicon nanowire transistor (SiNWT) has become an intensively researched electronic device and holds great potential in the nanoelectronics industry. Nanowires which are one dimensional nanostructures with good electrical properties make them suitable for the nano-scale device fabrication. Many techniques have been developed for silicon nanowire transisitor fabrication such as chemical-vapor-deposition (CVD), electron-beam lithography, laser induced decomposition, field-emission induced growth on a scanning tunneling microscopy tip and atomic force microscope (AFM) nanolithography process.
[0003] Atomic force microscope (AFM) has become a useful tool not only for observing surface morphology and topography but also for fabrication of various nanostructures and nanodevices. This is due to AFM not just suitable for conducting materials but also for insulating material like polymer. There are several methods for nanopatterning such as dip-pen nanolithography (DPN), chemo-mechanical surface patterning and local anodic oxidation (LAO) patterning.
[0004] However, current processes for fabricating a complete silicon nanowire transistor are complicated and not easy to handle.
Summary of the Invention
[0005] One object of the present invention is to provide a process for fabricating a silicon nanowire transistor with the components of a source pad, a drain pad, a lateral gate pad, and a silicon nanowire as channel. In one embodiment, the process comprises providing silicon-on-insulator (SOI) wafer having a chemically reactive substrate, wherein the components of a silicon nanowire transistor are pre-designed on the substrate of the SOI wafer; patterning the substrate of the SOI wafer by local anodic oxidation using atomic force microscope (AFM) nanolithography according to the pre-designed components of the silicon nanowire transistor, thereby forming a nanoscale oxide pattern corresponding to the components of the silicon nanowire transistor on top of the substrate; etching the substrate with a basic, anisotropic chemical etchant to remove the portions of the substrate that are not covered by the nanoscale oxide pattern; and further etching the substrate with an acidic, isotropic chemical etchant to remove the nanoscale oxide pattern; whereby a complete silicon nanowire transistor is fabricated.
[0006] In another embodiment of the process, the SOI is p-type.
[0007] In another embodiment of the process, the chemically reactive substrate of the SOI wafer is silicon.
[0008] In another embodiment of the process, the local anodic oxidation using atomic force microscope (AFM) nanolithography uses a conductive AFM tip which operates in contact mode.
[0009] In another embodiment of the process, the conductive tip is a gold-coated tip. In a further embodiment of the process, when the gold-coated tip is in contact mode with the substrate, a bias voltage is applied between the tip and the substrate; thereby when the tip is moving on the top surface of the substrate, the nanoscale oxide pattern of the components of the silicon nanowire transistor is formed. In yet a further embodiment of the process, when the bias voltage is 9 volt, the tip writing speed is όμπυ^ in air humidity of 55.8%RH-68.9%RH.
[0010] In another embodiment of the process, the basic, anisotropic chemical etchant is tetramethylammonium hydroxide (TMAH). In a further embodiment of the process, the TMAH is 25wt% in water solution, and the etching is performed at 65°C for 20 seconds.
[0011] In another embodiment of the process, the acidic, isotropic chemical etchant is hydrogen fluoride (HF). In a further embodiment of the process, the HF is 2wt% in water solution, and the etching is performed for 5 seconds. [0012] Another object of the present invention is to provide a silicon nanowire transistor fabricated on a silicon-on-insulator (SOI) wafer. In one embodiment, the SiNWT comprises a source pad, a drain pad, a lateral gate pad, and a silicon nanowire as channel.
[0013] The objectives and advantages of the invention will become apparent from the following detailed description of preferred embodiments thereof in connection with the accompanying drawings.
Brief Description of the Drawings [0014] Preferred embodiments according to the present invention will now be described with reference to the Figures, in which like reference numerals denote like elements.
[0015] FIG 1 is a perspective view of a silicon-on-insulator (SOI) in accordance with one embodiment of the present invention.
[0016] FIG 2 is a cross section view of the SOI shown in FIG 1.
[0017] FIG 3 is a perspective view of the SOI showing the nanoscale oxide pattern of the SiNWT in accordance with one embodiment of the present invention.
[0018] FIG 4 is a cross section view of the SOI shown in FIG 3.
[0019] FIG 5 is a perspective view of the SOI showing the uncovered portions of the silicon layer being removed by etching in accordance with one embodiment of the present invention.
[0020] FIG 6 is a cross section view of the SOI shown in FIG 5.
[0021] FIG 7 is a perspective view of the SiNWT in accordance with one embodiment of the present invention.
[0022] FIG 8 is a cross section view of the SiNWT shown in FIG 7.
[0023] FIG 9 is a perspective view of the finished SiNWT device in accordance with one embodiment of the present invention.
Detailed Description of the Invention
[0024] The present invention may be understood more readily by reference to the following detailed description of certain embodiments of the invention. [0025] Throughout this application, where publications are referenced, the disclosures of these publications are hereby incorporated by reference, in their entireties, into this application in order to more fully describe the state of art to which this invention pertains.
[0026] The present invention provides a silicon nanowire transistor (SiNWT). As a nanoelectronic device, the SiNWT comprises a source (S) pad, a drain (D) pad, a lateral gate (G) pad, and silicon nanowire as channel. The present invention also provides a process for fabricating the SiNWT, where the process fabricates the SiNWT using silicon- on-insulator (SOI) wafer by atomic force microscope (AFM) nanolithography and subsequent wet chemical etching operations.
[0027] In one embodiment, the SiNWT is fabricated onto a silicon-on-insulator
(SOI) wafer, preferably a p-type SOI wafer. As shown in FIGS 1 and 2, the SOI wafer comprises an insulator buried oxide layer and two chemically reactive Si layers that sandwich the insulator layer. In one embodiment, the SOI wafer is with top Si layer -lOOnm, buried oxide layer ~200nm and bottom Si substrate ~6.25μπι. The SOI wafer can be cut to size of 1cm x 1cm and cleaned by standard wafer cleaning procedures.
[0028] In one embodiment, the SOI wafer is first pre-designed to locate the components of the SiNWT on the top surface of the chemically reactive Si layer. Then local anodic oxidation (LAO) patterning is performed so that a SiOx mask layer is formed covering the pre-designed components of the SiNWT including a source (S) pad, a drain (D) pad, a lateral gate (G) pad, and silicon nanowire as channel as shown in FIGS 3 and 4. For LAO patterning method, the SiOx mask layer is grown on the chemically reactive Si substrate by the application of a bias voltage between a conductive AFM tip and the substrate surface. The conductive AFM tip is preferably a gold-coated one operating in a contact mode with the top surface of the reactive substrate. The LAO patterning is influenced by various parameters including tip radius, air humidity, tip sample voltage and tip writing speed. In one embodiment, the formation of the SiNWT nanoscale oxide pattern was drawn with the bias voltage of 9 Volt that applied between tip and substrate, and tip writing speed όμΓη/β in air humidity of 55.8%RH-68.9%RH. LAO patterning was chosen for lithography process because the oxidation process is easy to produce the mask of the nanoelectronic device without reaction with any extra chemical substances. In addition, the process is simple comparing to other methods and easy to handle. [0029] Then, the SOI with the SiOx mask pattern was undergone the first wet etching process to remove the uncovered portions of the Si reactive layer. In one embodiment, the first wet etching process was performed with tetramethylammonium hydroxide (TMAH). The TMAH was chosen because it is an anisotropic chemical etchant with the high ratio of etching selectivity to silicon. In addition, the TMAH is nonflammable, non-toxic, less harmful and CMOS compatible. Preferably, the TMAH was 25wt% in water solution, and the etching was performed at 65°C for 20 seconds. The resultant product after the first wet etching process is shown in FIGS 5 and 6.
[0030] Then a second wet etching process was performed with hydrogen fluoride (HF) to remove the oxide mask layer. The HF is an isotropic chemical etchant. Preferably, the HF was 2wt% in water solution, and the etching was performed for 5 seconds. The complete SiNWT is shown in FIGS 7 and 8. FIG 9 shows a finished product of SiNWT device.
[0031] The process for fabricating SiNWT by AFM nanolithography of the present invention is a new promising alternative technique and architecture to the existing technology for nanoelectronic device fabrication. The AFM nanolithography technique is advantageous due to its ability to write various nanoscale patterns by controlling the probe movement on substrate surface. In the present invention, SiNWT is fabricated via formation of nanoscale silicon oxide pattern on SOI wafer using AFM nanolithography. To fabricate the SiNWT patterned by AFM nanolithography, the applied voltage between tip and substrate, tip writing speed and environment humidity are controlled.
[0032] The process for fabricating SiNWT of the present invention has many advantages over the current techniques. The advantages include that the process is simple, the cost for hardware and maintenance is low, the mask area is less, the space needed for equipment is small, no critical hazardous materials are needed, and the alignment of subsequent pattern with sample programming is accurate.
[0033] While the present invention has been described with reference to particular embodiments, it will be understood that the embodiments are illustrative and that the invention scope is not so limited. Alternative embodiments of the present invention will become apparent to those having ordinary skill in the art to which the present invention pertains. Such alternate embodiments are considered to be encompassed within the scope of the present invention. Accordingly, the scope of the present invention is defined by the appended claims and is supported by the foregoing description.