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Title:
SILICON WAFER POLISHING METHOD, SILICON WAFER PRODUCTION METHOD, AND SILICON WAFER
Document Type and Number:
WIPO Patent Application WO/2018/070108
Kind Code:
A1
Abstract:
Provided are: a silicon wafer chamfer polishing method with which it is possible to inhibit the generation of slips from a notched part during heat treatment in a device formation process; a silicon wafer production method; and a silicon wafer. This method for polishing a silicon wafer having a notch is characterized in that the notch is overpolished on at least one main surface side of the silicon wafer by a mirror finish chamfer polishing process.

Inventors:
NISHIMURA MASASHI (JP)
TANAKA HIRONORI (JP)
Application Number:
PCT/JP2017/030148
Publication Date:
April 19, 2018
Filing Date:
August 23, 2017
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Assignee:
SUMCO CORP (JP)
International Classes:
H01L21/304; B24B9/00; C30B29/06; C30B33/02; C30B33/08; H01L21/324
Foreign References:
JP2002018684A2002-01-22
JP2003077872A2003-03-14
JP2009259959A2009-11-05
JP2009016602A2009-01-22
Attorney, Agent or Firm:
SUGIMURA Kenji (JP)
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