SILICON WAFER PROCESSING METHOD - SUMITOMO MITSUBISHI SILICON

Title:

SILICON WAFER PROCESSING METHOD

Document Type and Number:

WIPO Patent Application WO/2005/057645

Kind Code:

A1

Abstract:

A silicon wafer processing method includes an etching step (13) at which an acid etching solution and an alkaline etching solution and an alkaline etching solution are placed in etching baths and a wafer having a process transformation layer and passed through a lapping step (11) and a cleaning step (12) is dipped in order in the acid etching solution and the alkaline etching solution, a surface mirror-polishing step (18) of mirror-polishing one side of the etched wafer, and a cleaning step (19) of cleaning the wafer subjected to the surface mirror polishing. The method is characterized in that at the etching step, after acid etching, alkaline etching is carried out, and the acid etching solution contains 100 wt% of acid aqueous solution mainly containing hydrofluoric acid and nitric acid and 30 wt% or more of phosphoric acid. According to this method, the planarity after the lapping is maintained, and the surface roughness can be reduced. Further, the wafer after the surface mirror polishing can have a favorable planarity and a low back surface roughness.

Inventors:

KOYATA SAKAE (JP)
TAKAISHI KAZUSHIGE (JP)

Application Number:

PCT/JP2004/015999

Publication Date:

June 23, 2005

Filing Date:

October 28, 2004

Export Citation:

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Assignee:

SUMITOMO MITSUBISHI SILICON (JP)
KOYATA SAKAE (JP)
TAKAISHI KAZUSHIGE (JP)

International Classes:

H01L21/308; H01L21/304; H01L21/306; (IPC1-7): H01L21/306; H01L21/308

Foreign References:

JP2003100701A	2003-04-04
JPH08502148A	1996-03-05
JP2002203823A	2002-07-19
JPH11135474A	1999-05-21
JPH11233485A	1999-08-27

Other References: