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SIMPLIFIED BIAS CIRCUITRY FOR DIFFERENTIAL BUFFER STAGE WITH

SYMMETRIC LOADS

FIELD OF THE INVENTION

[0001] The present invention relates to biasing circuitry for differential buffer stages.

BACKGROUND OF THE INVENTION

[0002] A block diagram of a conventional DLL (delay-locked loop) is shown in

Figure 1. A voltage controlled delay line consisting of differential delay elements 12, 14, ... 16 takes an input clock signal refclk 10 and delays it by a precise amount based on its bias voltages 26,28. When the DLL is locked to the reference clock, the delay of each delay element is T _C | _k /n, where T _C | _k is the clock period, and there are n differential delay elements 12, 14, ..., 16. The delay line produces a delayed clock dclk 18. A feedback portion of the circuit compares the delayed clock dclk 18 to the reference clock refclk 10 and produces and adjusts the bias voltages V _nbιas 26 and V _pbιas 28 such that the delay is one clock period of the input clock. To do this, the feedback portion of the circuit has a phase detector 20 that compares the phase of refclk 10 to the phase of dclk 18. If the two are the same, the bias voltages should remain as they are. If the two are out of phase, the bias voltages should increase or decrease to speed up or slow down the delay line accordingly. The phase detector 20 produces digital up or down pulses whose duration is proportional to the phase difference detected. The up and down pulses are used by the charge pump 22 to adjust a control voltage V _ctr ι 23, typically stored on a loop filter capacitor. V _ctr i is used by the biasing circuit 24 to set the bias voltages 26, 28.

[0003] A specific example of a differential delay element is shown in Figure 2.

The amount of delay introduced into a digital waveform passing through the delay element can be controlled with the analog bias voltages. The analog bias voltages change the trip points at which the delay element changes logical state. The delay

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elements use a differential structure in order to increase noise rejection. Input devices M2 42, M3 44 are a differential pair which steer output current through two branches. The analog voltage V _nbιas on transistor M1 40 helps determine the delay through the delay element by controlling the total current through each branch. Devices M4 48, M5 50, M6 52, M7 54, make up two symmetric load elements 49, 51 that are used to provide a linear resistance load. Only load element 49 will be described in detail. The symmetric load 49 is made up of two PMOS devices 48, 50 connected in parallel. One device M5 50 has its gate tied to V _pblas while the other device M4 48 is diode connected. Vp _b i _as also helps control the delay by determining the signal swing. [0004] In order for the differential delay stage to operate properly, the bias voltages V _n bιas, V _pblas must be set. These voltages are derived from another voltage, V _ctri 23 of Figure 1. Figure 3 shows an example of a conventional feedback circuit for generating the bias voltages V _pbιa s and V _n bιas from V _c tri - V _c tri 23 is connected to an inverting input of an operational amplifier 102. The output of operational amplifier 102 is connected to the gate of transistor 104 and to the gate of transistor 114. A symmetric load 108 is connected to transistor 104 through additional transistor 106. The symmetric load 108 includes a first transistor 110 having its gate connected to a non- inverting input of the operational amplifier 102, and a second transistor 112 that is similarly connected. Transistors 114,116,1 11 ,113 are connected in the same manner as transistors 104,106,110,112, and operate as a buffer for the output. The bias voltages are indicated at V _pb ,as 28 and V _nbias 26.

[0005] The feedback circuit of Figure 3 generates bias voltages that have the DC behaviour illustrated in Figure 4. Figure 4 shows a first curve 120 for V _ctr i, a second curve 122 for V _pbιas , and a third curve 124 for V _nb ιas-

[0006] Disadvantageously, the circuit of Figure 3 includes significant complexity, in particular including operational amplifier 102 which in itself includes many transistors not shown in detail.

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SUMMARY OF THE INVENTION

[0007] According to one broad aspect, the invention provides a biasing circuit comprising: an input for receiving a control voltage 23, and a V _nb ι _as output 26 for outputting a V _nbιas voltage comprising: a feedback-free circuit 200,202,204 that produces the Vn _b i _as voltage from the control voltage such that the V _n bιas voltage is near one V _D D over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range.

[0008] In some embodiments, the feedback-free circuit comprises: a pull-up network 200 for pulling up the V _nbιas voltage when the control voltage is low; a pull-down network 204 for pulling down the V _nb ι _as voltage when the control voltage is high; and a variable resistive element 202 for impeding the pull-down network from pulling down the

Vnbias-

[0009] In some embodiments, the first voltage range is from about 0.0V to about

0.2V, the second voltage range is from about 0.2V to about 0.4V, and the third voltage range is a range above about 0.4V.

[0010] In some embodiments, each of the voltage ranges is a respective range between 0 and V _DD .

[0011] In some embodiments, the feedback-free circuit comprises: a CMOS output stage having a P-type transistor 150 and an N-type transistor 152, with a diode connected transistor 154 between the P-type transistor and the N-type transistor, the output stage receiving the control voltage as input, and producing the V _nbιas between the

P-type transistor and the diode connected transistor.

[0012] In some embodiments, the biasing circuit further comprises: V _pbιas output

28 for outputting a Vp _bιa s voltage; a direct connection between the input and the V _pbιas output.

[0013] In some embodiments, a delay locked loop comprises: a delay line comprising a plurality of differential delay elements 12,14,16; the biasing circuit is

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connected to provide the Vp _bιas voltage and the V _nb ι _as voltage as biasing inputs to the differential delay elements.

[0014] According to another broad aspect, the invention provides a method of biasing comprising: receiving a control voltage and outputting a V _nb ιas voltage; producing the V _nb i _as voltage in a feedback-free manner from the control voltage such that the V _n bιas voltage is near one V _D D over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range.

[0015] In some embodiments, the first voltage range is from about 0.0V to about

0.2V, the second voltage range is from about 0.2V to about 0.4V, and the third voltage range is a range above about 0.4V.

[0016] In some embodiments, each of the voltage ranges is a respective range between 0 and V _D D-

[0017] In some embodiments, the method further comprises outputting a Vp _bιas voltage that tracks the control voltage.

[0018] Other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Embodiments of the present invention will now be described, by way of example only, with reference to the attached Figures, wherein:

[0020] Figure 1 is a block diagram of a delay locked loop;

[0021] Figure 2 is a schematic diagram of an example of a delay element;

[0022] Figure 3 is a schematic diagram of an example of a biasing circuit;

[0023] Figure 4 is a graph showing various voltages produced by the biasing circuit of Figure 3;

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[0024] Figure 5 is a schematic diagram of a biasing circuit provided by an embodiment of the invention;

[0025] Figure 6 is a graph showing various voltages produced by the biasing circuit of Figure 5; and

[0026] Figure 7 is a schematic diagram of another example of a biasing circuit provided by an embodiment of the invention.

DETAILED DESCRIPTION

[0027] Figure 5 is a schematic diagram of a biasing circuit provided by an embodiment of the invention. The biasing circuit of Figure 5 will be described in the context of its application in providing biasing voltages to the delay element of Figure 2. However, it is to be understood that the biasing circuit may find application to providing biasing voltages to other delay element designs. This circuit also takes the input V _ctr ι 23 and produces biasing voltages V _pbιas 28 and V _n bι _as 26. The circuit directly connects the input voltage V _ctr i 23 to V _pbl as 28. V _c tri 23 is also connected to the gate of transistor P1 150 and the gate of transistor S1 152. Transistor P1 150 is connected to transistor S1 152 through diode connected transistor M1 154. Transistor P1 150 is also connected to a supply voltage V _D D- The bias voltage V _n bιas 26 is taken at the drain of transistor M1 154. Transistor S1 may be implemented with a size larger than that of M1 to accommodate the current generated by M1.

[0028] The purpose of this circuit is to mimic the DC behaviour of the biasing circuit of Figure 3. With reference to Figure 4, when V _ctr i is between 0.3V and 0.9V if can be seen that V _ctr ι and V _pbιas are approximately equal. With reference back to Figure 5, this behaviour is reproduced by a direct connection between V _ctr ι 23 and V _pbιas 28. Operation of the circuit for other values of V _ctr ι will result in different behaviour than that shown in Figure 4. The remaining circuitry of Figure 5 is for producing a V _nbιas that mimics the behaviour of V _nbιas shown in Figure 4 for the circuit of Figure 3. The behaviour of the circuit of Figure 5 is shown in Figure 6. Shown are curves 160 for V _ctr i= V _pbιas , and 162 for V _nbl as-

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[0029] It is noted that a biasing circuit that produces only V _pbιa s 28 is also contemplated. The control voltage V _ctr ι 23 might for example be directly connected to the Vp _b . _as inputs of the differential delay elements, or the V _pbιa s inputs might be generated in some other manner.

[0030] In operation, as V _ctr i rises, transistor S1 , which is selected for its switching characteristics, starts to turn on, and transistor P1 150 starts to turn off. This starts to pull down the voltage V _nbιas - When transistor S1 152 is completely on, transistor P1 150 will be completely off and V _nbιas will then be very close to zero volts (or V _S s)- Between approximately .2 volts and .4 volts the transistor S1 is transitioning from being completely off to being partially on. During this period, the transistor P1 150 and the switch S1 152 are both trying to pull V _nb ι _as in one way or the other, but outside of that range, S1 overtakes P1. The result is that, again referring to Figure 6, V _nb ι _as drops sharply between .2 and .4 volts, and then levels off to a more moderate rate of decline between .4 volts and 1.0 volts.

[0031] It can be seen that the curve 162 for V _nb ι _as in Figure 6 is very similar to the curve for V _nbιas 124 in Figure 4. Furthermore, the curve for V _Pbias in Figure 6 is the same as curve 122 for V _pblas in Figure 4 over the range of .3 through .9 volts. [0032] The bias voltages V _Pb ι _as , V _n bιas together define the voltage swing at the output of the differential delay element. The effect of the inaccuracy in V _Pb , _as between .2 volts and .3 volts is that the voltage will swing a little bit lower, and the swing will be non-symmetric. The assumption is that the circuits operation is non-critical below .3 volts. Setting V _P bιa _s sets the swing.

[0033] In more general terms, the biasing circuit includes a complementary MOS output stage (P1 150, S1 152) with a diode-connected transistor 154 in series between the two complementary transistors. However, the transistor 154 clearly makes the operation very different from that of a standard CMOS output stage, which would have a steep transition between high and low states of the output voltage as the control or input voltage is changed.

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[0034] More generally still, a feedback-free circuit is provided that produces the

V _nb i _as voltage from the control voltage such that the V _n bιas voltage is near a supply voltage V _D D over a first control voltage range, sharply declines over a second control voltage range that follows the first control voltage range, and less sharply declines in a substantially linear manner over a third control voltage range that follows the second control voltage range. In some implementations, V _D D is about 1V, and the first voltage range is from about OV to about 0.2V, the second voltage range is from about 0.2V to about 0.4V, and the third voltage range is a range above about 0.4V. These ranges are process and design dependant. In some implementations, the ranges are a function of V _D D, for example 0 to 0.2V _D D, 0.2 V _DD to 0.4V _DD and above 0.4V _DD . Another specific example is 0 to 0.3V _DD , 0.3V _D D to 0.5V _D D, and above 0.5V _D D-

[0035] Referring now to Figure 7, shown is a schematic diagram of another biasing network provided by an embodiment of the invention. This circuit again receives the V _ctr i 23 input and produces a V _nbιas output 26. The input 23 is connected to a pull-up network 200 and a pull-down network 204. There is a variable resistor element 202 for impeding the pull-down network from pulling down V _nbιas 26. It can be seen that the circuit of Figure 5 is a specific example of the Figure 7 embodiment. Specifically, for the Figure 5 embodiment, the pull-up network 200 is P transistor 150, the pull-down network 204 is the transistor S1 152, and the variable resistor 202 is the diode connected transistor M1 154. However, it is to be understood that other elements can be used. [0036] In the embodiments described above, the device elements and circuits are connected to each other as shown in the figures, for the sake of simplicity. In practical applications of the present invention to semiconductor ICs and DRAM devices, elements, circuits, etc. may be connected directly to each other. As well, elements, circuits etc. may be connected indirectly to each other through other elements, circuits, etc., necessary for operation of the semiconductor ICs and DRAM devices. Thus, in actual configuration of semiconductor ICs and DRAM devices, the circuit elements and devices are coupled with (directly or indirectly connected to) each other.

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[0037] The above-described embodiments of the present invention are intended to be examples only. Alterations, modifications and variations may be effected to the particular embodiments by those of skill in the art without departing from the scope of the invention, which is defined solely by the claims appended hereto.