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Patent Searching and Data


Title:
SIMULATOR AND SYSTEM AND METHOD FOR ASSISTING DESIGN OF SEMICONDUCTOR CIRCUIT DEVICE
Document Type and Number:
WIPO Patent Application WO/2017/009956
Kind Code:
A1
Abstract:
The present invention relates to a simulation method for evaluating the effects of soft errors on a CRAM in an FPGA. In order to integrate functions in an FPGA, information about circuit connections (netlist) to be integrated in the FPGA is converted into a bit sequence (bitstream) for a configuration memory (CRAM) in the FPGA. At this time, by utilizing the fact that a netlist obtained by converting RTL code for implementing functions in an FPGA corresponds one to one to a CRAM data sequence (bitstream) that is stored in the FPGA, the inversion of bit information in the CRAM (failure injection) is mapped to the circuitry. The problem is solved by providing a means for testing the effects of the inversion of the individual bits of the CRAM by way of logical simulation based on the above fact. Furthermore, a means for comparing the simulation results with the expected values of anticipated dangerous-failure outputs separately set by a user is also provided.

Inventors:
KANNO YUSUKE (JP)
SAEN MAKOTO (JP)
TOBA TADANOBU (JP)
Application Number:
PCT/JP2015/070188
Publication Date:
January 19, 2017
Filing Date:
July 14, 2015
Export Citation:
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Assignee:
HITACHI LTD (JP)
International Classes:
G06F17/50
Foreign References:
JP2014134842A2014-07-24
Other References:
ASADI, GHAZANFAR ET AL.: "Soft Error Rate Estimation and Mitigation for SRAM-Based FPGAs", PROCEEDINGS OF THE 2005 ACM/SIGDA 13TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE GATE ARRAYS, 20 February 2005 (2005-02-20), pages 149 - 160, XP058292544
MANSOUR, WASSIM ET AL.: "An Automated SEU Fault-Injection Method and Tool for HDL-Based Designs", IEEE TRANSACTIONS ON NUCLEAR SCIENCE, vol. 60, no. 4, 9 July 2013 (2013-07-09), pages 2728 - 2733, XP011526281
Attorney, Agent or Firm:
SEIRYO I.P.C. (JP)
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