Title:
SIMULATOR
Document Type and Number:
WIPO Patent Application WO/2017/149641
Kind Code:
A1
Abstract:
A multicore model simulator according to the present invention is characterized by being provided with: a plurality of processor core models for executing an inputted instruction; a processed time calculation unit for calculating a time of day, as a processed time, at which each of the processor core models has executed an instruction; a scheduler for selecting a next processor core model to execute from among the plurality of processor core models on the basis of the processed time calculated by the processed time calculation unit; and an overall time-holding unit for holding the overall processed time of the simulator that is determined from the processed time calculated by the processed time calculation unit, the processor core model selected by the scheduler executing a next instruction following directions of the scheduler. This configuration enables the accuracy of synchronization between multi-CPUs or multi-cores to be maintained while allowing the multi-CPUs or multi-cores to execute with different accuracies of execution, and makes accurate evaluation of performance possible.
Inventors:
OGAWA DAISUKE (JP)
TOYAMA OSAMU (JP)
TAKEO TETSUYA (JP)
NISHIKAWA KOJI (JP)
TOYAMA OSAMU (JP)
TAKEO TETSUYA (JP)
NISHIKAWA KOJI (JP)
Application Number:
PCT/JP2016/056198
Publication Date:
September 08, 2017
Filing Date:
March 01, 2016
Export Citation:
Assignee:
MITSUBISHI ELECTRIC CORP (JP)
International Classes:
G06F11/28
Foreign References:
| JP2012146148A | 2012-08-02 | |||
| JP2008210107A | 2008-09-11 |
Other References:
KAZUKI KUNO: "Design of Distributed Simulator for Shared Memory Multiprocessors", IPSJ SIG, vol. 2004, no. 80, 31 July 2004 (2004-07-31), pages 103 - 108, ISSN: 0919-6072, [retrieved on 20040731]
Attorney, Agent or Firm:
INABA, Tadahiko et al. (JP)
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