SINGLE ENDED SENSE AMPLIFIER

CLAIM OF PRIORITY

Benefit of Priority is hereby claimed to U.S. Patent Application No. 11/673,105, filed February 9, 2007 and entitled "SINGLE ENDED SENSE AMPLIFIER FOR VERY LOW VOLTAGE APPLICATIONS", which is incorporated herein by reference in it entirety.

TECHNICAL FIELD

The present invention relates to sense amplifiers, more particularly, to single-ended sense amplifiers operating with electrically erasable programmable read-only memories (EEPROMs) at very low magnitude supply voltages.

BACKGROUND ART hi memory design, a sense amplifier is a critical analog circuit, hi EEPROM and flash memories the sense amplifier function is twofold. First, the precharge of a bitline to a proper value of clamp voltage is significant for providing calibrated sensing of a selected memory cell. A sense amplifier performs a critical function in assuring the bitline is precharged to a clamp voltage of sufficient magnitude to ensure proper sensing of memory cell current. Second, sensing a selected memory cell current flowing through the bitline is also critical. Magnitude of the memory cell current depends on the state of the cell and must be determined promptly and accurately in order to sustain a high level of system performance.

With reference to Fig. 1, a prior art sense amplifier 100 is based on a differential structure 130 in order to compare a current coming from a selected memory cell (not shown) to a fiducial current coming from a reference cell (not shown). The fiducial current flows on a reference bitline 110 and a memory cell current flows on a bitline 120 from the selected memory cell. The differential structure 130 compares the relative magnitudes of the voltages on the reference bitline 110 and the bitline 120. As different memory cells with differing states (i.e., cells storing either a 1 or a 0) are selected, the current flowing on the bitline

120 varies, producing different voltage levels at the corresponding input to the differential structure 130. The differential structure 130 amplifies the voltage difference and provides a corresponding voltage level to an output amplifier 140. The output amplifier 140 in turn amplifies and inverts the voltage level and provides it to the sense amplifier output terminal OUT.

With reference to Fig. 2, a prior art single-ended current sense amplifier 200 has a precharge circuit 205 to maintain a stable voltage on a bitline BITLINE, a sensing circuit 210 coupled to the bitline BITLINE for sensing an amount of current flowing into the bitline BITLINE, a direct current amplification circuit 215 coupled to the sensing circuit for amplifying the current sensed on the bitline BITLINE, a current-to-voltage conversion circuit 220 for converting the sensed current to a voltage, and a voltage amplification circuit 225 for amplifying the voltage at the sense amplifier output. The sense amplifier also includes an overshoot filtering circuit 230 to filter out positive glitches on the bitline BITLINE.

Generally, a single-ended structure provides an advantage by eliminating a need to have a reference cell and a comparator circuit as are commonly used in differential sense amplifier structures. The single-ended amplifier provides a savings in test time and in the amount of die area used by the sense amplifier circuit. Additionally, the single-ended structure provides other advantages over the standard differential structures such as providing less sensitivity to mismatched circuit components, less process variation sensitivity, and improved access time at low supply voltages.

SUMMARY

In one embodiment, a sense amplifier comprises a transimpedance amplifier configured to sense a current variation into a bitline and produce an output voltage level proportionate to a current variation sensed. A transconductance device is coupled to the transimpedance amplifier and the bitline, the transconductance device capable of produce varying bitline current responsive to the transimpedance amplifier output voltage. An output amplifier is coupled to the transimpedance amplifier and is capable of producing an output signal level proportionate to the transimpedance amplifier output voltage. A bias circuit is coupled to the transimpedance amplifier and the output amplifier, the

bias circuit is capable of producing bitline current through the transimpedance amplifier and the output amplifier.

In a second embodiment, a sense amplifier comprises a transimpedance means for sensing variation of a bitline current and produces an output voltage level proportionate to the variation in the bitline current sensed. A transconductance means produces varying bitline current responsive to an output voltage level of the transimpedance means, the transconductance means coupled to the transimpedance means and the bitline. An output means produces an output signal level proportionate to the transimpedance means outputs a voltage level, the output means coupled to the transimpedance means. A biasing means produces bitline current through the transimpedance means and the output means, the biasing means is coupled to the transimpedance means and the output means.

A further embodiment is a method of producing a clamp voltage on a memory bitline, the method comprises configuring a magnitude of the clamp voltage, injecting a bitline current into the bitline, monitoring a magnitude of bitline current being injected on the bitline, producing a magnitude of feedback voltage responsive to the bitline current magnitude monitored, throttling the bitline current injected responsive to the magnitude of feedback voltage produced, and determining a magnitude of bitline current injected being less than a minimum bitline current to establish the clamp voltage configured.

An additional embodiment is a method of sensing a state of a memory cell, the method comprising selecting a memory cell, producing a bitline current, coupling the bitline current to the selected memory cell, sensing a magnitude of the bitline current, producing an output voltage level responsive to the magnitude of bitline current sensed, and detecting a magnitude of output voltage passing through a threshold voltage level.

BRIEF DESCRIPTION OF DRAWINGS Fig. 1 is a schematic diagram of a prior art differential sense amplifier.

Fig. 2 is a schematic diagram of a prior art single-ended sense amplifier.

Fig. 3 is a schematic diagram of an exemplary embodiment of a single- ended sense amplifier.

Fig. 4 is a process flow diagram of a method to produce a clamping voltage according to the circuit of Fig. 3.

Fig. 5 is a process flow diagram of a method of sensing a memory cell state according to the circuit of Fig. 3.

DETAILED DESCRIPTION

With reference to Fig. 3, a bias circuit 330 is coupled to a transimpedance amplifier 315 in an exemplary embodiment of a single-ended sense amplifier 300. The bias circuit 330 is coupled between V _DD 310 and Ground 305. The bias circuit 330 comprises, for example, a first current mirror 332 in parallel with a second current mirror 334. A first ENABLE-BAR terminal EN is coupled as an input node to both the bias circuit 330 and a first current mirror pullup device PbO. The first current mirror pullup device PbO and a first current mirror pulldown device NbO are coupled in series between V _DD 310 and Ground 305. The first current mirror pullup device PbO and a first current mirror pulldown device NbO may be, for example, implemented as a PMOS and an NMOS transistor, respectively. A drain and gate of the first current mirror pulldown device NbO are coupled together at a series coupling point with the first current mirror pullup device PbO to produce a first current mirror output node 335. One skilled in the art will appreciate that even though the first current mirror 332 is an exemplary current biasing circuit, alternate examples of current biasing circuits exist. For example, using solid state circuit elements or device configurations that take into account fundamental thermal characteristics of voltage or current generation versus temperature produce current biasing circuits with characteristics proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT) with regard to electrical characteristic tracking.

The first current mirror output node 335 is coupled to a second current mirror pulldown device NbI. A second current mirror pullup device PbI is coupled in series with the second current mirror pulldown device NbI, the series combination coupled between V _DD 310 and Ground 305 forming the second current mirror 334. The second current mirror pullup device PbI and a second current mirror pulldown device NbI may be, for example, implemented as a PMOS and an NMOS transistor respectively. A drain and gate of the second

current mirror pullup device PbI are coupled together at a series coupling point to produce a second current mirror output node 360.

The first current mirror output node 335 and the second current mirror output node 360 are input nodes to a transimpedance amplifier pulldown device Nl and a transimpedance amplifier pullup device Pl, respectively. The transimpedance amplifier pullup device Pl and the transimpedance amplifier pulldown device Nl may be, for example, a PMOS and an NMOS transistor, respectively. The transimpedance amplifier pullup device Pl and the transimpedance amplifier pulldown device Nl are coupled in series between a bitline 380 (B ITLINE) and ground 305, the series combination forming the transimpedance amplifier 315. The series coupling point between the transimpedance amplifier pullup device Pl and the transimpedance amplifier pulldown device Nl forms a transimpedance amplifier output node 350 and an output node of the transimpedance amplifier 315. The transimpedance amplifier output node 350 is coupled as an input to the transimpedance amplifier pulldown device Nl.

The transimpedance amplifier output node 350 is coupled to an input node of a transconductance device 320. The transconductance device 320 is coupled between V _DD 310 and the bitline 380. The transconductance device 320 may be, for example, a transconductance PMOS transistor PO.

The transimpedance amplifier output node 350 is coupled at a first input node to an output amplifier 325 and an input node to an output pullup device P2. The first current mirror output node 335 is coupled to a second input node to the output amplifier 325 and an input node to an output pulldown device N2. The output pullup device P2 and the output pulldown device N2 may be, for example, a PMOS and an NMOS transistor respectively. One skilled in the art would readily recognize that PMOS and NMOS transistors configured as pullup and pulldown devices, as exemplified in various occurrences above, may alternatively be implemented with complementary bipolar devices or any of a number of corresponding semiconductor switching devices with complementary switching characteristics.

A switching threshold node 328 is formed at a series coupling point between the output pullup device P2 and the output pulldown device N2. The switching threshold node 328 is coupled to an input node of an output inverter

INV. An output node of the output inverter INV forms the output terminal OUT of the single-ended sense amplifier 300. An output enable device N3 is coupled between the switching threshold node 328 and ground 305. A second ENABLE B AR terminal EN is coupled as an input node to the gate of the output enable device N3.

A first function of the exemplary single-ended sense amplifier 300 is to precharge the bitline 380. The single-ended sense amplifier 300 produces a source current Ip ₀ , which is the current through, for example, the transconductance PMOS transistor PO. The source current Ip ₀ provides the source of current for a bitline current I _BL and a sense current I _sen se- The bitline current I _BL is the current flowing into the bitline 380. The sense current I _sense is the current flowing into the transimpedance amplifier 315.

The bitline current I _BL is the sum of the current components provided to the bitline 380 for a precharge current I _prech g and a memory cell current I _ce ii. The magnitudes of the precharge current I _prech g (not shown) and the memory cell current I _ce n (not shown) depend on selection of a memory cell (not shown), the selected memory cell state, and the electrical condition of the bitline 380.

A precharge current Ip _rech g is that component of the bitline current I _BL supplied for precharging the bitline 380 during a precharge phase of operation. In the case where a memory cell is not selected, the precharge current I _pre chg is supplied to the bitline 380 until the bitline voltage V _BL reaches the bitline clamp voltage VB _L _ _CL AMP- The magnitude of the bitline clamp voltage V _B L_ _C LAMP is configured to be close to V _DD in order to establish a reference level of voltage on the bitline 380. With low magnitude supply voltages, for example, when V _DD < 1.2 V, being able to configure the bitline clamp voltage V _BL _ _CLAMP as close to the supply voltage V _DD as possible is significant in the exemplary single-ended sense amplifier 300 compared to previous attempts to design sense amplifiers.

If the bitline voltage V _BL is initially 0 volts (V), the transimpedance amplifier pullup device Pl is off. In this bias situation, the drain voltage of the transimpedance amplifier pullup device Pl is the bitline voltage VB _L 0-e., 0 V) and the gate voltage is a second current mirror voltage V _b2 , which is the output voltage on second current mirror output node 360. With the transimpedance amplifier pullup device Pl off, a transimpedance amplifier output voltage Vj, which is the voltage on the transimpedance amplifier output node 350, is set to 0

V by the transimpedance amplifier pulldown device Nl. The transimpedance amplifier pulldown device Nl is on due to a gate input node being supplied by a first current mirror voltage V _b i, which is the voltage on the first current mirror output node 335. The transimpedance amplifier output voltage Vi (0 V) is provided to a gate input of the transconductance device 320. With 0 V supplied to the gate input, the transconductance PMOS transistor PO is turned on and injects the precharge current I _pre chg to the bitline 380. The magnitude of bitline current IBL is equal to the transconductance PMOS transistor PO saturation current, since, for example, V _S G_PO = V _D D-

The bitline voltage V _BL increases due to the injection of the precharge current I _prech g- As the bitline voltage V _BL increases, the transimpedance amplifier pullup device Pl begins to turn on and conduct a transimpedance amplifier pullup device current Ip ₁ . With the transimpedance amplifier pullup device Pl turning on, a magnitude of the transimpedance amplifier output voltage V ₁ increases. The increase in magnitude of the transimpedance amplifier output voltage V] occurs since the bitline voltage V _BL is the source node voltage and the second current mirror voltage V _b2 is the gate voltage of the transimpedance amplifier pullup device Pl. As the magnitude of the transimpedance amplifier output voltage V ₁ increases, the precharge current I _prech g decreases. Increasing transimpedance amplifier output voltage V ₁ , applied to the gate of the transconductance PMOS transistor PO, reduces the V _g5 of the transconductance PMOS transistor PO, until finally, the precharge current I _preCh g stops.

The bitline voltage V _BL reaches the bitline clamp voltage V _BL _ _CLAMP when the capacitance of the bitline is charged up as fully as possible by the biasing from transconductance device 320 (i.e., the transconductance PMOS transistor PO). The bitline clamp voltage V _BL _ _CLAMP is attained at the maximum precharge condition, which occurs when the precharge current I _prech g and the bitline current IB _L are zero and

Where INI is a transimpedance amplifier pulldown device current I _NI - This equality occurs when the transconductance PMOS transistor PO, the transimpedance amplifier pullup device Pl, and the transimpedance amplifier

pulldown device Nl are all in saturation. The saturated condition of the devices leads to the expression

(where K _p is a p-type device process gain factor, W is the width, and L is the length of the device Pl) which, when the expression is that solved for V _BL yields

Additionally, the transconductance PMOS transistor PO must be in saturation, which is a condition which gives

V BL - ^* V ' DD — ds sal PO , which yields which when solved for V _BL produces V * BL — < V * 1 + ^ V ' t ^{1 1} FPO

where V ₁ = V _DD

Due to electrical proximity to V _DD and the fact that the transconductance device 320 may be, for example, comprised of a transconductance PMOS transistor PO, the bitline clamping voltage may be produced at a voltage level within one device voltage drop of the power source voltage level VD _D - Additionally, since an input to the transimpedance amplifier 315 is coupled to the bitline 380, the transimpedance amplifier input is also electrically coupled within a single device voltage drop of the power source voltage level V _DD -

A second function of the exemplary single-ended sense amplifier 300 is to sense a memory cell state. A memory cell is coupled to the bitline 380 when selected, for example, in a read operation. The current flowing through a selected memory cell is the memory cell current I _ce ii.

In the case where a selected memory cell is off, the current flowing through PO is equal to the mirror current Ibias- The transimpedance amplifier output voltage Vi depends on the sizing of PO. A sizing ratio, the geometry

dependent term ( —wλ in a typical MOS device Beta (β) for the output of pullup \ L J device P2, is lower than the sizing ratio for the transconductance PMOS transistor PO. Therefore, the relative drive strength of the transconductance PMOS transistor PO is greater than the drive strength of the output of pullup device P2. With the transconductance PMOS transistor PO configured with relatively strong drive, the bitline voltage V _BL is held stiffly to a high voltage level and the magnitude of the transimpedance amplifier output voltage Vj is relatively high.

With the relatively high voltage level of the transimpedance amplifier output voltage Vi being the gate voltage of the output pullup device P2, the drive strength of the pullup device P2 is relatively weak in addition to the weakening effect due to the sizing ratio configured for the device as mentioned above. The relatively weaker drive strength of the output of pullup device P2 allows the output pulldown device N2 to pull down the switching threshold voltage V ₂ low enough that the inequality V ₂ < VthiNv is true, where VthiNv is the logic- inversion threshold voltage for the output inverter INV. With the inequality V ₂ < Vthi _N v true, V _OUT , the voltage on the output node OUT rises to VDD.

If the memory cell current I _ce ii is not equal to 0 amps (i.e., the memory cell is on), the source current Ip ₀ is the memory cell current I _ce ii plus the sense current I _sense . With the current mirror effect present at the transimpedance amplifier pulldown device Nl, the sense current I _sense is equal to the mirror current Ibia _s - With the sum of the memory cell current I _ce ii plus the mirror current I _b i _as flowing as the source current Ipo, the transconductance PMOS transistor PO drain-source voltage VDSp ₀ commences to increase and causes a relatively lower voltage level input for the source node voltage of the transimpedance amplifier pullup device Pl, which in turn commences to cause a relatively lower voltage level for the transimpedance amplifier output voltage Vj.

The transimpedance amplifier output voltage Vi is fed back as the gate voltage of the transconductance PMOS transistor PO by a feedback path through the bitline 380, the transimpedance amplifier pullup device Pl, and the transimpedance amplifier output node 350. Through the feedback path, the commencement of the increase in the drain-source voltage VDSpo promptly produces a relatively lower transimpedance amplifier output voltage Vi, which

increases the drive strength of the transconductance PMOS transistor PO and maintains a stable bitline voltage VBL-

With the relatively lower transimpedance amplifier output voltage Vi being the gate voltage of the output pullup device P2, the drive strength of the pullup device P2 is relatively stronger. The relatively stronger drive strength of the output of pullup device P2 counteracts the output pulldown device N2 and pulls up the switching threshold voltage V ₂ high enough that the inequality V ₂ > Vthi _N v is true, where Vthπw is the logic-inversion threshold voltage for the output inverter INV. With the inequality V ₂ > Vthi _N v true, V _O uτ, the voltage on the output node OUT is pulled down to the Ground voltage level.

The feedback path, mentioned above, creates a variation in the transimpedance amplifier output voltage Vi as a function of the memory cell current I _ce ii- A time-variant form of the transimpedance amplifier output voltage Vi as a function of the associated gains in the feedback loop is given by 1 ^rdS N\ T where the resistance rds _N i is the gain of the transimpedance amplifier 315 and gmpo is again of the transconductance PMOS transistor PO. In consideration that grn _PO τds _N1 » 1 the time- variant form OfV ₁ becomes vi « _L_ . /

Solving for a source current Ipo time-variant form yields ipo gmpo * vl=Iceii.

Determining the inversion threshold of the output amplifier 325 begins with the observation that the output pullup device current Ip ₂ equals the output pulldown device current I _N2 or

Ip2 ⁼ IN2

By the current mirror operation between the first current mirror pulldown device NbO and the output pulldown device N2

IN2 ⁼ Ibias The β-ratio, n, between the transconductance PMOS transistor PO and the output pullup device P2, where

determines the channel current relationship between the devices and is given as _th where Iς _e ii _j h is the memory cell threshold current. Since the gate threshold voltage V _g8 is the same for the transconductance PMOS transistor PO and the output pullup device P2, I _b i _as is given as th Solving for the memory cell threshold current yields

Icelljh ~ Ibias * (n - 1) with the note that a condition is n ≠ 1.

The exemplary single-ended sense amplifier 300 is enabled by providing a low logic level voltage on the ENABLE_BAR terminals EN . The low logic level voltage is provided as the gate voltage to the output enable device N3. The low level gate voltage disables the output enable device N3 and allows the switching threshold output 328 to operate freely. Additionally, the low logic level voltage provided to the ENABLE-BAR terminal EN at the first current mirror pull-up device PbO turns on the device and enables the first current mirror 332.

The exemplary single-ended sense amplifier 300 is disabled by providing a high logic level voltage on the ENABLE_BAR terminals EN . The high logic level voltage is provided as the gate voltage to the output enable device N3. The high level gate voltage enables the output enable device N3, turning the device on which pulls the switching threshold output 328 to Ground voltage level.

Additionally, the high logic level voltage provided to the ENABLE_BAR EN terminal at the first current mirror pull-up device PbO turns off the device and disables the first current mirror 332.

With reference to Fig. 4, an exemplary method of producing a clamp voltage on a memory bitline 400 commences with a first step of configuring a magnitude of a clamp voltage 405. The method continues with injecting a bitline

current into the bitline 410 followed by monitoring a magnitude of bitline current being injected into the bitline 415. A next step is producing a magnitude of feedback voltage responsive to the bitline current magnitude monitored 420 followed by throttling the bitline current injected responsive to the magnitude of feedback voltage produced 425. Next, a determination is made of whether a magnitude of bitline current injected is less than a minimum to establish the clamp voltage 430. If the bitline current is less than a minimum to establish the clamp voltage, a next step is ceasing to inject bitline current 435. If the bitline current is greater than a minimum to establish the clamp voltage, a step is taken to continue inj ecting bitline current 410.

With reference to Fig. 5, an exemplary method of sensing a state of a memory cell 500 begins with selecting a memory cell 505. A next step of the method is producing a bitline current 510 followed by coupling the bitline current to the selected memory cell 515. The method continues with sensing a magnitude of the bitline current 520 and producing an output voltage level responsive to the magnitude of bitline current sensed 525. The method goes on with determining whether a magnitude of output voltage passes through a threshold level 530. The method continues with producing a first output signal level 535 if the determination of the output voltage being greater than a threshold is true. If the output voltage is less than the threshold, the method continues with outputting a second output signal level 540.

It would be clear to one of skill in the art that alternate embodiments of the above detailed description may exist. Therefore, the above description is illustrative and not restrictive. The scope of the invention should therefore be determined by reference to the appended claims and not by the above description.