Title:
SINGLE-LINE SERIAL DATA TRANSMISSION CIRCUIT AND SINGLE-LINE SERIAL DATA TRANSMISSION METHOD
Document Type and Number:
WIPO Patent Application WO/2018/173623
Kind Code:
A1
Abstract:
A single-line serial data transmission circuit having a master circuit 1 and a slave circuit 4, the master circuit 1 having a data clock adder 2 for writes and a data receiver 3 for reads. The slave circuit 4 has an active generator 5, a data clock separator 6 for writes, and a data transmitter 7 for reads. The master circuit 1 and the slave circuit 4 are connected by one length of a signal line 8. When the master circuit 1 writes data to the slave circuit 4, a signal synthesized from a clock signal and a data signal is transmitted to the slave circuit 4 via the signal line 8 by the master circuit 1, and the clock signal and the data signal are extracted from the transmitted signal in the slave circuit 4 through the data clock separator 6.
Inventors:
FUKUMOTO YOSUKE (JP)
Application Number:
PCT/JP2018/006604
Publication Date:
September 27, 2018
Filing Date:
February 23, 2018
Export Citation:
Assignee:
ROHM CO LTD (JP)
International Classes:
H04L5/14; H02M3/155; H04L7/00; H04L7/04; H04L25/38
Foreign References:
| JP2010114636A | 2010-05-20 | |||
| JPS55147054A | 1980-11-15 | |||
| JP2011010450A | 2011-01-13 | |||
| JP2016032322A | 2016-03-07 |
Attorney, Agent or Firm:
SANO PATENT OFFICE (JP)
Download PDF: