BACKGROUND OF THE INVENTION

Field of the invention

The present invention relates to radio engineering, electronics and measuring technology and is designed for undistorted transmission of wideband signals in miscellaneous electronic systems with single supply operation.

Description of related art

Unlike well-known apparatus for signal transmission using bipolar supply, obtaining output voltage close to zero turns out to be challenging for single-supply apparatuses. For example, if a pedestal is added to output voltage to offset same closer to zero, then a need arises to accurately control a preset level of the pedestal, particularly with the transmission of small signals that may have amplitude of about several millivolt. That said, diminishing supply voltage (especially for mobile devices), which is the primary trend in the above-mentioned fields, results in a dire need of lowering minimal non-distorted output voltage to keep or widen the dynamic range of the transmitted signals.

That is why the problem of having minimal (“near-zero”) output voltage in single supply apparatus for signal transmission is one of pressing issues of modem electronics, particularly in designing analog and analog-digital chips. Also, it is important for any apparatus for signal transmission, including those with single supply operation, to provide high growth rate of a signal necessary for undistorted transmission of wideband signals.

Known in the art has been a single-supply operational amplifier (OA) for transmitting a signal disclosed in the Texas Instruments’ operational amplifier OPA189 specification (/data_sheets/ OPAxl89 Precision, Lowest-Noise, 36-V, Zero-Drift, 14-MHz, MUX-Friendly, Rail-to- Rail Output Operational Amplifiers datasheet (SBOS830I - SEPTEMBER 2017 - REVISED OCTOBER 2021). The disclosure shows a series connection of an OA input circuit, designed to operate in an input voltage range from - 0.1V to the power voltage decreased by 2.5V, and three amplifying modules providing transmission gain of 170dB with an open feedback circuit.

Since the output voltage in the prior art design depends on the load resistance, it lies between 20 mV (at the load resistance of lOKOhm) and 80 mV (at the load resistance of 2K0hm). In some cases, this would be unacceptably large and result in distortion of a near-zero transmitted signal. Inability of providing a near-zero output voltage, i.e., proportional to the transmitted signal, is considered a drawback of that design.

Also known has been a similar design disclosed in “Output stage for near rail operation” (US patent 9,548,707 of Jan. 17, 2017).

This design circuitry for non-distorted transmission of low- voltage signals under single supply comprises a differential amplifier with a non-inverting (“+”) and inverting inputs, a main transistor arranged in a common emitter configuration, a current generator, a buffer transistor, and an output current circuit. In the circuitry, the output of the differential amplifier is connected to the control electrode of the main transistor, the current generator is connected to one of the electrodes of the main transistor and to the control electrode of the buffer transistor, whereas the buffer transistor’s emitter is connected to the input of the output current circuit and represents the output of the design.

The demerit of this design is that the output voltage thereof cannot be less 2 mV when implemented (col. 3, lines 63-65 of the patent). In practice, this is not enough to reach a nearzero output voltage and, thus, undistorted transmission of low- voltage signals.

Another analog is a technical decision described in an “Output stage bleeder circuit applied to ultralow quiescent current LDO” (Chinese application 1 1 1930167 of Nov. 13, 2020).

The design circuitry comprises operational amplifier OA with a non-inverting (“+”) input and an inverting (“-”) input which is an input of the design, a transistor, the gate thereof being connected to an output of the OA and the source thereof being an output of the design, a resistive divider connected between the output of the design and a current source made as a current mirror, and a current controller lb, the midpoint of the divider being connected to the non-inverting “+” input of the OA.

The downside of this design is that it cannot provide both the “near-zero” output voltage and high growth rate of the signal.

The analog believed the closest to the claimed design is a “Rail-to-rail input/output operational amplifier and method” disclosed in U.S. patent 6,356,153 of Mar. 12, 2002. This apparatus comprises an input stage, two gain boost amplifiers, and an output stage. Essential for achieving the goals of the proposed apparatus is the part of the prior art design having two amplifiers and output stage. This part chosen as a prototype comprises two OAs, four transistors, two resistors and a class AB operation circuit.

In the circuitry, a first terminal of the first transistor is connected to an output of the first OA, and a second terminal of the first transistor is connected to a first terminal of the class AB operation circuit and to a first terminal of the third transistor. A first input of the first OA is to be connected to a source of the signal, a third terminal of the first transistor is connected to another input of the first OA and to a first terminal of the first resistor, and a third terminal of the third transistor is connected to a second terminal of the first resistor.

Additionally, a first terminal of the second transistor is connected to an output of the second OA, a second terminal of the second transistor is connected to a second terminal of the class AB operation circuit and to a first terminal of the fourth transistor, a third terminal of the second transistor is connected to an input of the second OA and to a first terminal of the second resistor, a third terminal of the fourth transistor is connected to a second terminal of the second resistor, another input of the second OA is to be connected to the source of the signal, and second terminals of the third and fourth transistors are connected to each other. Common features of the proposed design and prototype are two OAs, two transistors and a resistor, the first terminal of the first transistor being connected to the output of the first OA, the first input of the first OA being for connection to the source of the signal, the first terminal of the second transistor being connected to the output of the second OA, the third terminal of the second transistor being connected to one of the inputs of the second OA and to the first terminal of the resistor.

The prototype operates using class AB amplifying state which tends to have nonlinear distortions of the signal. For that reason, the prototype cannot provide undistorted transmission of signals, particularly wideband “near-zero” signals.

Summary of the invention

The object of claimed invention is overcoming the drawbacks of the prior art and providing a single supply apparatus for signal transmission for undistorted signal transmission in a wide dynamic range which would be able to produce a minimal (“near-zero”) output voltage (of fractions of mV) when a wideband “near-zero” signal is suppled to an input thereof.

The technical result, which the prior art designs are unable to attain, is to substantially widen the dynamic range of a single supply apparatus for signal transmission, providing at the same time a high growth rate of the output signal.

The above technical result is achieved by providing a feedback circuit and output current setter in the apparatus comprising two OAs, two transistors and the resistor with abovedescribed connections thereof, a third terminal of the first transistor being connected to a second terminal of the second transistor, the connection being connected to a load and to the feedback circuit, the feedback circuit being also connected to a second input of the first OA, the output current setter being also connected to the second input of the second OA. The above connections of the elements of the claimed apparatus make it possible to define a current stabilizer therein comprising a second OA, a second transistor and a resistor along with their connections. That said, the output of the output current setter is an input of the current stabilizer, and the output of the current stabilizer is the second terminal of the resistor. The claimed apparatus has a simpler design as compared with the prototype and can produce a minimal (“near-zero”) output voltage (of fractions of mV versus units and tens of millivolts in prior art). At the same time, a high growth rate of the output signal is achieved which is necessary for undistorted transmission of wideband signals, and nonlinear distortions are eliminated due to using class A amplifying state.

This results in the substantial widening of the dynamic range of single-supply apparatuses for wideband signal transmission.

Also presented for patent protection is the claimed technical solution made as an integral circuit (IC) which combines a number of elements of the claimed apparatus.

In this embodiment, the above-mentioned technical result is achieved by providing an IC comprising a complex of elements of the apparatus, namely, two OAs, two transistors and a resistor. The output of the first OA is connected to the first terminal of the first transistor, the output of the second OA is connected to the first terminal of the second transistor. The second input of the first OA is connected to the IC terminal intended for supplying an input signal. The third terminal of the second transistor is connected to the first input of the second OA and to a terminal of the resistor. The third terminal of the first transistor is connected to the second terminal of the second transistor, and this connection is connected to the IC terminal intended for connecting to the load and to the first terminal of the feedback circuit, the circuit being external to the IC.

Additionally, the IC is provided with a terminal intended for connecting to a second terminal of the external feedback circuit, the above IC terminal being connected to the second input of the first OA and being able to be used for connecting to a source of a second input signal. Also, the integral circuit is provided with a terminal connected to the second input of the second OA and intended for connecting to an external current setter.

Brief description of the drawings

The claimed invention is explained further using accompanying drawings which present the implementations of the apparatus for signal transmission and where: Fig. 1 shows the prototype.

Fig. 2a illustrates the claimed invention as compared with the prototype. Fig. 2b presents the claimed invention made as an IC.

Fig. 3 shows the claimed invention in one of the implementations thereof.

Fig. 4 shows the claimed invention in another implementation thereof.

Fig. 5 is the claimed invention in one more implementation thereof.

Fig. 6 illustrates an embodiment of an output current setter for a current stabilizer in the claimed invention

Fig. 7 shows another embodiment of an output setter for a current stabilizer in the claimed invention.

Fig. 8 presents one more embodiment of an output setter for a current stabilizer in the claimed invention.

Figs. 9a-9f show charts illustrating the lowering of the transmitted signal distortion level when using the proposed technical solution; and

Fig. 10 presents a screenshot from an oscillograph screen, illustrates the results of an experiment verifying the achievement of the stated technical result.

Detailed description of the invention

With references to the drawings, the claimed apparatus and operation thereof are explained below.

Fig. 1 presents a portion of a prior art rail-to-rail differential amplifier according to US patent 6,356,153. The portion (prototype) comprises two OAs (58A and 57A), four transistors (26, 30, 37, and 45), two resistors (89, 88), and a class AB operation circuit (29), the prototype having two inputs (22, 33) connected to inputs of the first and second OA, respectively, a point (31) of the connection of third terminals of the third and fourth transistors being an output of the prototype.

The present invention in comparison to the prototype is shown in Fig. 2a. There, the claimed apparatus 100 comprises a first OA 101, a first transistor (MOSFET in Fig. 2) 103, an output current setter 155, a terminal 107 for connecting to a power supply (PS) positive pole, a first input terminal 109, a first, 111, and a second, 113, PS terminals of the first OA 101, a first input 115 (shown in Fig. 2a as a non-inverting “+” one) of the first OA 101 connected to the first input terminal 109, a second input 117 (shown in Fig. 2a as an inverting one) of the first OA 101 connected to a second input terminal 118, an output 119 of the first OA 101 is connected to a first (control) terminal 121 (gate terminal in Fig. 2a) of the first transistor 103. A second terminal 125 (drain terminal in Fig. 2a) of the first transistor 103 is connected with the first PS terminal 111 of the first OA 101 and with the terminal 107, whereas the second PS terminal 113 of the first OA 101 is connected to a terminal 127 serving for the connection to the common wire (ground) and the negative pole of the PS. A connection of a third terminal 123 (source terminal in Fig. 2a) of the first transistor 103 to a second terminal 191 (drain terminal in Fig. 2a) of a second transistor 153 (MOSFET in Fig. 2a) is used for connecting to a load (not shown) via a terminal 135.

A third terminal 193 (source terminal in Fig. 2a) of the second transistor 153 is connected to a first input 169 (an inverting (“-”) one in Fig. 2a) of a second OA 151 and to a first terminal 187 of a resistor 157.

A first (control) terminal 181 (gate terminal in Fig. 2a) of the second transistor 153 is connected to an output 165 of the second O A 151.

A first PS terminal 159 of the second OA 151 is connected to a contact 129 serving for the connection with a positive pole of the PS, whereas a second PS terminal 161 of the second OA 151 and the second terminal 189 of the resistor 157 are connected to the terminal 127 of the apparatus 100 intended to be connected to the common wire (frame) and the negative pole of the PS.

A first terminal 137 of a feedback circuit (FC) 143 is connected to the connection of the first, 103, and second, 153, transistors, a second terminal 139 of the FC 143 is connected to the second input 117 of the first OA 101, whereas a third terminal 141 of the FC 143 is connected to the terminal 127 of the apparatus 100.

It was noted above that the second OA 151, the second transistor 153, and the resistor 157 with the connections between them form a current stabilizer 105 with an input 131 connected to the second terminal 191 of the second transistor 153 and to the terminal 135 of the apparatus 100. A contact 133 connected to a second terminal 189 of the resistor 157 and to the terminal 127 serves an output of the stabilizer 105. A potential controlling the value of the current of the stabilizer 105 is supplied from a second terminal 173 of the output current setter 155 through a contact 163 of the stabilizer 105 to a second input 167 (a non-inverting (“+”) one in Fig. 2a) of the second OA 151.

A contact 171 of the output current setter 155, as well as the contact 129 of the stabilizer are to be connected to the positive pole of the PS, while a terminal 177 of the output current setter 155 is connected to the terminal 127.

Not shown in Fig. 2a are the PS, an input signal source and the load to be connected to respective terminals of the apparatus. For clarity, Fig. 2a uses thickened lines to show elements (the FC 143 and output current setter 155) and connections absent in the prototype. It is due to providing those elements and connections that the above-stated technical effect was achieved.

Schematics of the claimed apparatus made as an IC is presented in Fig. 2b. The apparatus 200 comprises first OA 101 , first transistor 103 (a MOSFET in Fig. 2b), and current stabilizer 105 implemented identically to that in Fig. 2a. Also, the apparatus 200 has terminal 107 for the connection to the positive pole of the PS, terminal 135 for the connection to the load and to external FC, terminal 127 for the connection to the negative pole of the PS, a first input terminal 109 for the connection to a signal source, a second input terminal 118 to connect to the external FC and another signal source, and terminal 163 to connect to a current setter output.

The first input 115 (a non-inverting (“+”) one in Fig. 2b) of the first OA101 is connected to the first input terminal 109 of the apparatus 200, the second input 117 (an inverting (“-”) one in Fig. 2b) of the first OA101 is connected to the second input terminal 118 of the apparatus 200, a first (control) terminal 121 (gate terminal in Fig. 2b) of the first transistor 103 is connected to the output 119 of the first OA 101. A second terminal 125 (drain terminal in Fig. 2b) of the first transistor 103 is connected to a first power supply terminal 1 1 1 of the first OA 101 and to the terminal 107 to be connected to the positive pole of the power supply. A second PS terminal 113 of the OA 101 is connected to the terminal 127 of the apparatus 200.

A point of connection of a third terminal 123 (source terminal in Fig. 2b) of the first transistor 103 and a first terminal 131 of the current stabilizer 105 is connected to the terminal 135 of the apparatus 200. An output 133 of the current stabilizer 105 is connected to the terminal 127 of the apparatus 200 intended to be connected with the negative pole of the PS. A contact 129 of the current stabilizer 105 is intended to be connected with the positive pole of the PS.

Not shown in Fig. 2b, and to be connected to respective terminals of the integral circuit 200, are the PS, an input signal source, the load, the FC, and the output current setter along with connections thereof.

The schematics of one of the embodiments of the claimed apparatus is presented in Fig. 3 where the apparatus 100 is shown comprising the OA 101, transistor 103, current stabilizer 105, output current setter 155, and FC 143. Designated 107 is the terminal for connecting to the positive pole of the PS. Also shown in Fig. 3 and related to the OA 101 are the first input terminal 109 of the apparatus, the first PS terminal 111, the second PS terminal 113, the first (non-inverting (“+”) in Fig. 3) input 115, which is connected to the first input terminal 109, the second (inverting (“-”) in Fig. 3) input 117, and the output terminal 119 connected to the first (control - gate terminal in Fig. 3) terminal 121 of the transistor 103. The third terminal 123 of the transistor 103 (source terminal in Fig. 3) is connected to the first terminal 131 of the current stabilizer 105 and to the terminal 135 of the apparatus 100, reserved for connecting to the load, whereas the second terminal 125 (drain terminal in Fig. 3) of the transistor 103 is connected to the first PS terminal 111 of the OA 101 and to the terminal 107 of the apparatus 100, intended for connecting with the positive pole of the PS.

The PS terminal 129 of the current stabilizer 105 is reserved for the connection to the positive pole of the PS source. Additionally, there is provided terminal 127 which is reserved for connecting to the negative pole of the PS source and is connected through the common wire (frame) of the apparatus with the second PS terminal 113 of the OA 101, the second terminal 133 of the current stabilizer 105 and the terminal 177 of the output current setter 155. The terminal 163 of the current stabilizer 105 is connected to the second terminal 173 of the output current setter 155.

A regular wire connecting the first, 137, and second, 139, terminals of the FC 143 is used as the FC 143 itself. The first terminal 137 of the FC 143 is connected to the connection of the transistor 103 and the current stabilizer 105, whereas the second terminal 139 of the FC 143 is connected to the second input 1 17 of the OA 101 , and the third, unused, terminal 141 of the FC 143 is connected to the terminal 127 of the apparatus.

Contacts 171 and 129 of the output current setter 155 and of the current stabilizer 105, respectively, are reserved for connecting to the positive pole of the PS source. Intended for connecting the load is the terminal 135 connected to the first terminal 131 of the current stabilizer 105, to the third terminal 123 of the transistor 103 and to the first terminal 137 of the FC 143.

Not shown in Fig. 3, and to be connected to respective terminals of the apparatus, are the PS source, an input signal source, and the load.

The schematics of another of the embodiments of the claimed apparatus is presented in Fig. 4 where the apparatus 100 is shown comprising the OA 101, the transistor 103, the current stabilizer 105, the output current setter 155, and the FC 143. Also depicted are the terminal 107 intended for connecting to the positive pole of the PS source, the first input terminal 109 of the apparatus 100, the first (111) and second (113) PS terminals of the OA 101. The OA 101 also has the first (non-inverting (“+”) in Fig. 4) input 115 connected to the first input terminal 109 of the apparatus 100, the second (inverting (“-”) in Fig. 4) input 117, and the output 119 connected to the first (control (gate terminal in Fig. 4)) terminal 121 of the transistor 103. The third terminal 123 of the transistor 103 (source terminal in Fig. 4) is connected to the first terminal 131 of the current stabilizer 105 and to the terminal 135 of the apparatus reserved for connecting to the load, whereas the second terminal 125 (drain terminal in Fig. 4) of the transistor 103 is connected to the first PS terminal 111 of the OA 101 and to the terminal 107 of the apparatus. The terminal 129 of the current stabilizer 105 is also reserved for connecting to the positive pole of the PS source. The terminal 127 is intended for the connection to the negative pole of the PS source and is connected through the common wire (frame) of the apparatus with the second PS terminal 113 of the OA 101, the second terminal 133 of the current stabilizer 105 and the terminal 177 of the output current setter 155. The terminal 163 of the stabilizer 105 is connected to the second terminal 173 of the output current setter 155. Contacts 171 and 129 of the output current setter 155 and of the current stabilizer 105, respectively, are reserved for connecting to the positive pole of the PS source.

Also shown in the schematics in Fig. 4 is the FC 143 comprising a first voltage divider of a first, 443, and a second, 445, FC resistors. The first terminal 447 of the first resistor 443 is connected to the first terminal 137 of the FC 143, and the second terminal 449 of the first resistor 443 is connected to the second terminal 139 of the FC 143 and to the first terminal 451 of the second resistor 445. The second terminal 453 of the second resistor 445 is connected to the terminal 141 of the FC 143. The first, 137, of three terminals of the FC 143 is connected to the junction point of the transistor 103 and current stabilizer 105, the second terminal 139 is connected to the second input 117 of the OA 101, and the third terminal 141 is connected to the terminal 127 of the apparatus 100. Reserved for connecting to the load is the terminal 135 of the apparatus 100, connected with the first terminal 131 of the current stabilizer 105, the third terminal 123 of the transistor 103, and the first terminal 137 of the FC 143.

Not shown in Fig. 4, and intended to be connected to respective terminals of the apparatus, are the PS source, an input signal source, and the load.

The schematics of a third of the embodiments of the claimed apparatus is presented in Fig. 5 where the apparatus 100 is shown comprising the OA 101, the transistor 103, the current stabilizer 105, the output current setter 155, and the FC 143. Also depicted are the terminal 107 intended for connecting to the positive pole of the PS source, the first input terminal 109 of the apparatus 100, the first (111) and second (113) PS terminals of the OA 101. The OA 101 also has the first (non-inverting (“+”) in Fig. 5) input 115 connected to the first input terminal 109, the second (inverting (“-”) in Fig. 5) input 117, and the output 119 connected to the first (control (gate terminal in Fig. 5)) terminal 121 of the transistor 103. The third terminal 123 of the transistor 103 (source terminal in Fig. 5) is connected to the first terminal 131 of the current stabilizer 105 and to the terminal 135 of the apparatus reserved for connecting to the load, whereas the second terminal 125 (drain terminal in Fig. 5) of the transistor 103 is connected to the first PS terminal 111 of the OA 101 and to the terminal 107 of the apparatus intended for the connection to the positive pole of the PS source. The terminal 129 of the current stabilizer 105 is also reserved for connecting to the positive pole of the PS source. The terminal 127 is intended for the connection to the negative pole of the PS source. This terminal 127 is also connected through a common wire (frame) of the apparatus with the second PS terminal 113 of the OA 101, the second terminal 133 of the current stabilizer 105, and the terminal 177 of the output current setter 155. The terminal 163 of the stabilizer 105 is connected to the second terminal 173 of the output current setter 155. The terminal 171 of the output current setter 155 and the terminal 129 of the current stabilizer 105 are used for connecting with the positive pole of the PS source.

Also shown in the schematics in Fig. 5 is the FC 143 comprising the resistor 443. The first terminal 447 of the resistor 443 is connected to the first terminal 137 of the FC 143, and the second terminal 449 of the resistor 443 is connected to the second terminal 139 of the FC 143. The first, 137, of three terminals of the FC 143 is connected to the junction point of the transistor 103 and current stabilizer 105, the second terminal 139 is connected to the second input 117 of the OA 101, and the third, unused, terminal 141 is connected to the terminal 127 of the apparatus.

Also, as depicted in Fig. 5, the apparatus 100 is provided with the second input terminal 118 and comprises a third, 545, a fourth, 547, and a fifth, 549, resistors, wherein the fourth, 547, and the fifth, 549, resistors, form a second voltage divider. The second input terminal 118 is connected to the first terminal of the third resistor 545, whose second terminal 555 is connected to the second input 117 of the OA 101 and to the second terminal 139 of the FC 143. The first terminal 559 of the fourth resistor 547 is connected to the input 115 of the OA 101, the second terminal 561 of the resistor 547 is connected to the terminal 127 of the apparatus 100. The fifth resistor 549 is connected via the first terminal 563 thereof to the first input terminal 109 and, via the second terminal 565 thereof, to the first input 115 of the OA 101.

Not shown in Fig. 5 and intended to be connected to respective terminals of the apparatus, are the PS source, input signal sources, and the load.

Fig. 6 presents one of possible embodiments of the output current setter 155 where the latter is made as a third voltage divider. This embodiment can be used in any embodiment of the claimed apparatus including, but not limited to, embodiments shown in Figs. 3-5. Shown in Fig. 6 are: the output current setter 155, a first resistor 605 of the third voltage divider and a second resistor 613 of the third voltage divider. A first terminal 621 of the first resistor 605 is connected to the first terminal 171 of the output current setter 155, intended to be connected to the positive pole of the PS source, a second terminal 629 of the second resistor 613 of the output current setter is connected to the third terminal 177 of the output current setter 155 reserved for connecting with the negative pole of the PS source, whereas a second terminal 625 of the first resistor 605 of the output current setter and a first terminal 627 of the second resistor 613 of the current setter are connected to the second terminal 173 of the output current setter intended to be connected to the current stabilizer 105.

Fig. 7 represents another of possible embodiments of the output current setter 155, using a field-effect transistor (FET) and a fourth voltage divider. This embodiment can be used in any embodiment of the claimed apparatus including, but not limited to, embodiments shown in Figs. 3-5. Shown in Fig. 7 are: the output current setter 155, a FET 703, a first, 707, and a second, 713, resistors of the output current setter serving as a first and a second elements of the fourth voltage divider. The drain terminal 741 of the FET 703 is connected to the output current setter first terminal 171 intended to be connected to the positive pole of the PS source, the source terminal 743 of the FET 703 is connected to the first terminal 737 of the first resistor 707 of the output current setter, the gate terminal 731 of the FET 703 is connected to the junction point of the second terminal 739 of the first resistor 707 of the output current setter and the first terminal 725 of the second resistor 713 of the output current setter and to the output current setter second terminal 173 intended to be connected to the current stabilizer 105. The second terminal 727 of the second resistor 713 of the output current setter is connected to the output current setter third terminal 177 intended to be connected to the negative pole of the PS source.

Fig. 8 represents one more possible embodiment of the output current setter 155, using a reference voltage source and a fifth voltage divider. This schematic can be used in any embodiment of the claimed apparatus including, but not limited to, embodiments shown in Figs. 3-5. Shown in Fig. 8 are: the output current setter 155, a reference voltage source 801, a first, 805, a second, 807, and a third, 813, resistors of the output current setter serving a first, a second, and a third elements of the fifth voltage divider. The first terminal 831 of the first resistor 805 of the output current setter is connected to the output current setter first terminal 171 intended to be connected to the positive pole of the PS source, the second terminal 833 of the first resistor 805 is connected to the first terminal 835 of the reference voltage source 801 and to the first terminal 839 of the second resistor 807, the second terminal 841 of the second resistor 807 is connected to the first terminal 843 of the third resistor 813 and to the second terminal 173 of the output current setter 155 intended to be connected to the current stabilizer 105. The second terminal 845 of the third resistor 813 of the output current setter is connected to the second terminal 837 of the reference voltage source 801 and to the output current setter third terminal 177 intended to be connected to the negative pole of the PS source.

Presented in Figs. 9a-9f are charts that illustrate the lowering of the level of distortion of the information signal as it is transmitted by the proposed apparatus. Numerated in Fig. 9 are: 901 — an input signal, 902 — an amplitude response for prior art designs, 903 — an amplitude response in the proposed apparatus; 904 — an output signal in the prior art designs (distorted), and 905 — an output signal in the proposed apparatus.

Presented in Fig. 10 are oscillograms of input and output signals of the claimed apparatus that confirm that the claimed technical result was obtained. Designated in the figure are 1001 — the oscillogram of an input test voltage and 1002 — an oscillogram of the output voltage.

Detailed description of the invention

A single-supply apparatus 100 for transmitting signals shown in Fig. 3 is one of the embodiments of the claimed invention which operates in a voltage repeater mode. As an input signal having voltage Uj _n is applied to the terminal 109, reserved for connecting with a source of the input signal, and then to the first, non-inverting (“+”), input 115 of the OA 101, voltage U] appears at the output 119 of the OA 101 and comes to the first, control, terminal 121 of the transistor 103 which operates in a linear mode. The current stabilizer 105 generates direct stable current Io, the value thereof depending on voltage UQ applied from the second terminal 173 of the output current setter 155 to the control input 163 of the current stabilizer 105.

Parameters of the current stabilizer 105 are selected in such a manner as to ensure that the minimal current stabilizer voltage drop (between terminals 131 and 133 thereof), U _min cs, corresponding to the beginning of the current stabilization mode, be, for example, 0.2 mV (or another value allowing for non-distorted signal transmission).

Flowing of the current Io through the current stabilizer 105 creates between the terminals 131 and 133 thereof output voltage U _out , which is applied from the terminals 135 and 127 of the apparatus connected to the terminals 131 and 133 to a load (not shown).

Current flowing through the transistor 103 is defined by both current I _o of the current stabilizer 105 and load current I ₂ = U _ou t / R where R is load resistance.

If the load is connected between the terminals 135 and 127 of the apparatus, then Ii = lo + U _ou t / R (1); and it is necessary that this current not exceed the maximum allowed value for the transistor 103.

If the load is connected between the terminals 135 and 107 of the apparatus, then

Ii = Io - U _out / R (2); and it is necessary that this current be no less than the value allowing for the linear mode of operation of the transistor 103.

From the first terminal 131 of the current stabilizer 105, the voltage U _ou t comes through the FC 143 made as a regular wire to the inverting input 117 of the OA 101, thus forming the following strong feedback circuit: the OA 101 - the transistor 103 - the FC 143 - OA 101. If, for some reason, the output voltage U _out at the inverting input 117 of the OA 101 becomes smaller than the Ui _n value at the non-inverting (“+”) input 115 thereof, then the voltage Ui at the first, control, terminal 121 of the transistor 103 increases and slightly opens the transistor 103, which results in the increasing of the output voltage U _ou t of the apparatus. The value of U _ou t reaches Uj _n , and the relation

U _0Ut = U _in (3); is thus met.

On the other hand, if the output voltage U _out at the inverting input 117 of the OA 101 exceeds the value Ui _n at the non-inverting (“+”) input 115 of the OA 101, then the voltage Ui at the first (control) terminal 121 of the transistor 103 decreases and slightly closes the transistor 103, which results in decreasing the output voltage U _ou t of the apparatus to reach the level of the Uj _n , and the relation (3) is met again.

Consequently, the output voltage U _out for the schematic of Fig. 3 is always as equal as practically possible to the value of the input voltage Uj _n .

The transmission response K of the above apparatus shown in Fig. 3 is equal to one, and, accordingly, it operates as a voltage repeater.

Conventional OA for a single-supply operation, such as OPA189, OPA365 of Texas Instruments,, and others, that can be used as the OA 101 in the proposed apparatus, are unable to ensure that the voltage Ui at the output 119 of the OA 101 be less than several tens of millivolts. However, Ui in the proposed apparatus according to Fig. 3 always exceeds the value of Uout by the amount of the potential difference between the control terminal 121 of the transistor 103 and the third terminal 123 thereof which is connected to the first terminal 131 of the current stabilizer 105. It is just this potential difference that ensures the bias of the output voltage Ui of a conventional OA 101 toward “near-zero” values at the output of the proposed apparatus, thereby contributing to the substantial lowering of the distortion level upon transmitting “near-zero” signals in the single-supply operation which, in turn, facilitates widening the dynamic range of apparatuses for signal transmission that have single-supply (the foregoing is ensured if the gate-source voltage of the transistor 103 exceeds the minimal output voltage of the OA 101, see U _m in in Fig. 9e).

Upon increasing the input voltage Uj _n up to several volts (depending on the parameters of a conventional OA 101), the apparatus operates in the same way ensuring the relation (3), the value of U _ou t being always less than Ui by the value of the potential difference between the control terminal 121 of the transistor 103 and the third terminal 123 thereof. The apparatus 200 mase as a integral circuit operates similarly, the only difference being that the FC 143 and output current setter 155 can be external relative to the integral circuit and connected to the above-mentioned terminals thereof.

Where it is desirable to obtain the transmission response exceeding one, such as 1.5 or 10, or any other practically feasible value (amplifying condition), the FC 143 has to comprise a voltage divider, such as a resistive one.

The schematics of such an embodiment of the claimed apparatus is shown in Fig. 4 (an amplifier circuit). The apparatus 100 in such a case operates as follows. When an input signal of voltage Uj _n is applied to the terminal 109, intended to be connected to an input signal source, and, accordingly, to the first, non-inverting (“+”) input 115 of the OA 101, voltage Ui emerges at the output 119 of the OA 101. The U| voltage proceeds to the first, control, terminal 121 of the transistor 103 operating in a linear mode. The current stabilizer 105 generates direct stable current Io, the value thereof depending on voltage Uo applied from the second terminal 173 of the current setter 155 to the control input 163 of the current stabilizer 105. Parameters of the current stabilizer 105 are selected in such a manner as to ensure that the minimal current stabilizer voltage drop (between terminals 131 and 133 thereof), U _{min C} s, corresponding to the beginning of the current stabilization mode, be, for example, 0.2 mV (or another value allowing for non-distorted signal transmission).

Flowing of the current Io through the current stabilizer 105 creates between the terminals 131 and 133 thereof output voltage U _out , which is applied from the terminals 135 and 127 of the apparatus connected to the terminals 131 and 133 to a load (not shown).

Current flowing through the transistor 103 is defined by both current I _o of the current stabilizer 105 and load current U = U _out / R where R is load resistance. If the load is connected between the terminals 135 and 127 of the apparatus, then the relation

(1) is met, and it is necessary that this current not exceed the maximum allowed value for the transistor 103.

If the load is connected between the terminals 135 and 107 of the apparatus, then the relation

(2) is met, and it is necessary that this current be no less than the value allowing for the linear mode of operation of the transistor 103.

From the first terminal 131 of the current stabilizer 105 and through the FC 143 comprising a first voltage divider (having the first, 443, and second, 445, resistors), the voltage U _out comes to the inverting input 117 of the OA 101. As a result, the following feedback circuit emerges: the OA 101 - the transistor 103 - the FC 143 - OA 101. Thus, voltage

U _out * R 445 / (R 445 + R 443) (4); where R 443, R445 — nominal values of resistance of the first, 443, and second, 445, resistors, respectively, ends up applied to the inverting input of the OA 101.

If, for some reason, the output voltage U _out is smaller than the U; _n value at the first input 115 of the OA 101, then the voltage Ui at the first, control, terminal 121 of the transistor 103 increases and slightly opens the transistor 103, which results in the increasing of the output voltage Uout of the apparatus. The increased value of U _out , via the FC 143 comprising the first voltage divider (443, 445), again comes to the second input 117 of the OA 101, and this process occurs until the relation is met

Uin = U _O ut / (1 + R 443 / R 445) (5);

On the other hand, if the value of the voltage U _ou t ( 1 + R443 / R445) at the inverting (“-”) input 117 of the OA 101 is larger than the value of U j _n at the non- inverting (“+’’) input 115 thereof, then the voltage Ui at the first, control, terminal 121 of the transistor 103 will be decreasing, thus closing the transistor 103. In response to that, the output voltage U _ou t of the apparatus will decrease, and, via the FC 143 comprising the first voltage divider (443, 445), will again be coming to the inverting (“-”)input 117 of the OA 101 until the relation (5) is met again.

Therefore, the output voltage U _ou t for the schematic of Fig. 4 is nearly always equal to the input signal voltage Uj _n , with the transmission response

K = U _ou t / Uin = I + R443 / R445 (6);

In this way, the transmission response exceeding one, for example 1.5 or 10 or any other practically feasible value (depending on the correlation between R443 and R445) is achieved in the embodiment of the proposed apparatus in Fig. 4. Therefore, it serves as an amplifier.

Conventional OAs for single-supply operation (such as OPA 189, OPA 365 of Texas Instruments, and others), which could be used as the OA 101 in the proposed apparatus, are unable to provide the voltage U i of less than several tens of millivolts at the output 119 of the OA 101. Because of that, Ui in the Fig. 4 embodiment of the proposed apparatus is always larger than U _out by the value of the potential difference between the control terminal 121 of the transistor 103 and the third terminal 123 thereof connected to the first terminal 131 of the current stabilizer 105. It is this potential difference that ensures the bias of the output voltage of the conventional OA 101 toward “near-zero” values at the output of the proposed apparatus, thus contributing to the substantial lowering of the distortion level upon transmitting low voltage signals in the single-supply operation and to widening the dynamic range of such apparatuses for signal transmission. The above is ensured where the gate-source voltage of the transistor 103 exceeds the minimal output voltage of the OA 101 (see U _min in Fig. 9e).

Upon increasing the input voltage up to units of volt (which depends on the parameters of the conventional OA 101), the apparatus operates the same way to ensure that the relation (5) is met, the value U _out being always less than Uj by the value of the potential difference between the control terminal 121 of the transistor 103 and the third terminal 123 thereof. The apparatus 200 made as an integral circuit (but with the difference that the FC 143 and output current setter 155 can be external relative to the integral circuit ) operates similarly.

Where a difference of two voltages is required to be obtained and then amplified, attenuated, or transmitted unchanged (a differential amplification mode), the apparatus will comprise an additional input connected to the inverting input of the OA via an additional resistor. Additionally, the apparatus will comprise a second voltage divider included between the main input of the apparatus and the input of the OA.

A schematic of such a differential amplifier (a third possible implementation of the apparatus) is presented in Fig. 5. The apparatus 100 operates as follows. A first input signal Umi is applied to the terminal 109 serving for connecting to a first source (not shown) of an input signal. Through a second voltage divider formed by the fifth, 549, and fourth, 547, resistors, the voltage Umi comes to the non-inverting (“+’’) input 115 of the OA 101, whereas a second input signal U; _n 2 comes from the terminal 118 of the apparatus through the third resistor 545 to the inverting (“-”) input 117 of the OA 101. With that, voltage Ui emerges at the output 119 of the OA 101 and comes to the first, control, terminal 121 of the transistor 103 which operates in a linear mode.

The current stabilizer 105 generates direct stable current Io, the value thereof depending on voltage Uo applied from the second terminal 173 of the output current setter 155 to the control input 163 of the current stabilizer 105. Parameters of the current stabilizer 105 are selected in such a manner as to ensure that the minimal current stabilizer voltage drop (between terminals 131 and 133 thereof), U _{min cs} , corresponding to the beginning of the current stabilization mode, be, for example, equal to 0.2 mV (or to another value allowing for non-distorted signal transmission).

Flowing of the current I _o through the current stabilizer 105 creates output voltage U _ou t at the terminals 131 and 133 of the latter. From the terminals 135 and 127 of the apparatus, which are connected to the terminals 131 and 133 of the current stabilizer 105, the voltage U _out is applied to a load (not shown).

The current Ii flowing through the transistor 103 is defined by both the current Io of the current stabilizer 105 and load current I2 = U _ou t/ R, where R is an active load resistance.

If the load is connected between the terminals 135 and 127 of the apparatus, then the relation (1) is met. In this case it is necessary that the value of this current be no more than what is maximum permissible for the transistor 103. If the load is connected between the terminals 135 and 107 of the apparatus, then the relation (2) is met and it is necessary that the value of this current be no less than that allowing for the linear mode of operation of the transistor 103. At the same time, a portion of the output voltage U _ou t through the first resistor 443 of the FC 143 comes to the inverting (“-”) input 1 17 of the OA 101 (wherein the first resistor 443 and the third resistor 545 form a sixth voltage divider). The output voltage U _ou t in the schematic of Fig. 5 is correlated with the input voltages U j _ni and Uj _n 2 in accordance with the known relation

U _out = a * (U _ml - U _in2 ) (7); where a = R443 / R545 = R547 / R549 (8); a differential coefficient of transmission of input voltages, and R 43, R545, R 47, R449 — rated values of resistance of the first, 443, third, 545, fourth, 547, and fifth, 549, resistors, respectively.

As a specific apparatus is implemented according to this embodiment, strict adherence to the relation (8) is optional: the rated values for the first, 443, third, 545, fourth, 547, and fifth, 549, resistors can be chosen based on a particular problem to be solved in the apparatus. Depending on the rated values of resistance of the resistors, the differential coefficient a can be more than one, less than one, or equal to one, making it possible to amplify, or attenuate the difference of the two voltages, or to transmit it unchanged. In this way, the output voltage Uout is always proportional to the difference Uj _ni - Uj _n of the input voltages. Additionally, this embodiment makes it possible to amplify, or attenuate the difference of the two voltages under a proper selection of the rated values for the first, 443, third 545, fourth 547, and fifth 549 resistors. Accordingly, it functions as a differential amplifier.

Conventional OAs for single-supply operation (such as OPA 189, OPA 365 of Texas Instruments,, and others), which could be used as the OA 401 in the proposed apparatus, are unable to provide the voltage Ui of less than several tens of millivolts at the output 119 of the OA 101. However, Ui in the Fig. 5 embodiment of the proposed apparatus is always larger than Uout by the value of potential difference between the control terminal 121 of the transistor 103 and the third terminal 123 thereof connected to the first terminal 131 of the current generator 105. It is this potential difference that ensures the bias of the output voltage of the conventional OA 101 toward “near-zero” values at the output of the proposed apparatus, thus contributing to the substantial lowering of the distortion level upon transmitting low voltage signals in the single-supply operation and to widening the dynamic range of such apparatuses for signal transmission. The above is ensured where the gate-source voltage of the transistor 103 exceeds the minimal output voltage of the OA 101 (see U _min in Fig. 9e).

As the input voltages Ui _ni and Uj _n 2 increase up to units of volt (depending on the parameters of the conventional OA 101), the circuit operates the same way, ensuring that the relation (7) is met. As this takes place, the value of U _ou t is always less than Ui by the value of the potential difference between the control terminal 121 of the transistor 103 and the third terminal 123 thereof. The apparatus 200 made as a integral circuit (but with the difference that the FC 143 and current setter 155 can be external relative to the integral circuit ) operates similarly.

Apart from the embodiments of the proposed design shown in Figs. 3-5 and described in the above, feasible are also other embodiments of the apparatus differing in connecting various circuits to the inputs and output of the OA, as disclosed, for example, in the specification of the above-mentioned operational amplifier OPA 189.

Further, operation of the current stabilizer shown in Fig. 2a .is described. This structure can be used for all possible implementations of the claimed apparatus, specifically, but with no limitation thereby, for those shown in Figs. 3-5.

As the output voltage U _ou t is present at the terminals 135 and 127 of the proposed apparatus, it appears to be applied to the terminals 131 and 133 of the current stabilizer 105 and is distributed between the second transistor 153, i.e., between the terminals 181 and 193 thereof, and the resistor 157, i.e., between the terminals 187 and 189 thereof. The voltage from the terminal 187 of the resistor 157 comes to the first input 169 of the OA 151 and is compared with the voltage UQ at the second input 167 of the second OA 15 Ithat comes from the second terminal 173 of the output current setter 155 via the terminal 163 of the current stabilizer 105. If the voltage at the first input 169 of the second OA 151exceeds the voltage Uo at the second input 167 thereof, an unbalance signal is formed at the output 165 of the second OA 151. The unbalance signal, applied to the control terminal 181 of the second transistor 153 operating in a linear mode, slightly closes the transistor 153, a current therethrough decreases, and the voltage at the terminal 187 of the resistor 157 and, consequently, at the first input 169 of the second OA 151 becomes equal to the voltage Uo at the second input 167 thereof. Conversely, if the voltage at the first input 169 of the second OA 151 is lower than the voltage Uo at the second input 167 thereof, the level of the unbalance signal at the output 165 of the second OA 151 changes. The unbalance signal, coming to the control terminal 181 of the second transistor 153, slightly opens the second transistor 153, a current therethrough increases, and the voltage at the terminal 187 of the resistor 157 and, consequently, at the first input 169 of the second OA 151 again becomes equal to the voltage Uo at the second input 167 thereof.

In this manner, always met in the current stabilizer 105 made according to Fig. 2a is the relation

Io * R _m = Uo (9); where R _m is a rated value of resistance of the resistor 157 and Uo - voltage at the second terminal 173 of the output current setter 155.

In other words, always flowing through the current generator 105 is direct current

Io = U _o / R _m (10); whose value is set by voltage Uo at the output of the output current setter 155 (at the second terminal 173 thereof).

The voltage drop U _m in cs between the terminals 131 and 133 of the current stabilizer 105 corresponding to the beginning of the current stabilization mode is determined by the relation

U _{min cs} = Io * Res (11); where Io — direct current of the current stabilizer 105 and R _cs is resistance between the terminals 131 and 133 of the current stabilizer 105, and

Res = R _m + R _DS (on) (12); where R _m — the rated value of resistance of the resistor 157 and Ros(on) is static drain-to- source on-state resistance of the second transistor 153 in the open state thereof. Properly selecting the rated value R of resistance of the resistor 157 and choosing the second transistor 153 with the required RDS(OH), one can conveniently ensure fulfilling the aboveformulated relation, so as to provide that the voltage between the terminals 131 and 133 of the current stabilizer 105 corresponding to the beginning of the current stabilization mode be equal to, for example, 0.2 mV (or to another value ensuring non-distorted signal transmission).

To obtain U _{min cs} equal, for example, to 0.2 mV, the value of the drain-to-source channel resistance Ros(on) of the second transistor 153 in open state thereof must amount to several hundred milliohm. With that, parasitic capacitances drain-source and gate-drain of the second transistor 153 can each reach the value of several tens of picofarads, and this interferes with non-distorted transmission of wideband signals. In the claimed apparatus, however, the gatedrain capacitance is short-circuited by the output resistance of the second OA 151, whereas the effect of the drain-source capacitance is neutralized by the feedback circuit from the source terminal 193 of the second transistor 153 via the first input o 169 of the second OA 151 and the output 165 thereof to the gate terminal 181 of the second transistor 153. As a result, high growth rate of the output signals is achieved.

With the above in view, and unlike any other designs, the structure presented in Fig. 2a ensures substantial widening of the dynamic range of the signal transmission single-supply apparatuses, concurrently providing high growth rate of the output signal, thus achieving the claimed technical result.

Proceeding to the description of the output current setter 155 presented in a general way in Fig. 2a, it is understood that it can be implemented in a variety of fashions. The schematic of one of those possible implementations of the output current setter 155 for the current stabilizer 105 in the proposed apparatus is shown in Fig. 6. It operates as follows.

As power voltage E is applied to the first terminal 171 of the output current setter 155, a direct current starts flowing through connected in series resistors 605 and 613 of the output current setter 155, the value of the current being

I3 = E / (R&o5 + R ) (13); where R ₆ os and Rei3 - rated values of resistance of the first, 605, and second, 613, resistors of the output current setter 155, respectively.

At the second terminal 173 of the output current setter 155, as a consequence of that, voltage Uo appears which is equal in value to the voltage drop created by the current I3 across the second resistor 613 of the output current setter 155:

Uo = E * R613 / (R605 + R613) (14); Using the relation (10), it is obtained that flowing through the current stabilizer 105, with the output current setter 155 configured as shown in Fig. 6, will be stable direct current

Io = U _o / R _m = E * (R i3 / (Roos + R013)) / R - (15);

Selecting values E, Roos, Ro 13 and R _m as needed, the required value of Io can always be obtained. Accordingly, the output current setter 155 shown in Fig. 6 ensures performance of the current stabilizer of Fig. 2a and of the proposed apparatus altogether.

However, the dependence of the output voltage Uo on the value of the power voltage E, which may be unstable, appears a disadvantage of the schematic of Fig. 6.

The schematic of another possible implementation of the current setter 155 for the current stabilizer 105 in the proposed apparatus which possesses advanced stability of the voltage Uo is presented in Fig. 7. It operates in the following way.

When power voltage E is applied to the first terminal 171 of the output current setter 155, direct current I4 starts flowing through connected in series the FET 703 and the first, 707, and second, 713, setter resistors of the output current setter 155. In accordance with the FET properties, if drain-source voltage between the terminals 741 (drain terminal) and 743 (source terminal) of the FET 703 of the output current setter 155 exceeds the cut-off voltage (a characteristic parameter of a FET), then the current I4 between those terminals does not depend on the drain-source voltage and is determined only by properties of the FET and the gate-source voltage. The gate-source voltage between the terminals 731 and 743 of the FET 703 of the output current setter 155 is determined by a voltage drop across the first resistor 707 and equals to I4 *R?07- At the same time, the voltage drop,

Uo = I4 * R713 (16); is formed across the second resistor 713, where R707 and R713 are the rated values of resistance of the first and second resistors of the output current setter 155.

This voltage Uo, independent of the power voltage E, comes to the second terminal 173 of the output current setter 155. Using the relation (10), it is obtained that flowing through the current stabilizer 105, with the output current setter 155 configured as shown in Fig. 7, will be stable direct current

Io — Uo/ Rm — I4 * R713 / Rm (17);

Selecting the FET 703 and values of R71 and R _m as needed, the required value of Io can always be obtained. Hence, the output current setter 155 shown in Fig. 7 ensures operability of the current stabilizer 105 and of the proposed apparatus altogether, the stability of the voltage Uo and, accordingly, of the current I _o of the current stabilizer 105), being substantially higher than in the schematic in Fig. 6 because the current I3 of the FET 703 is much more stable than the power voltage E.

The schematic of the third possible embodiment of the output current setter 155 for the current stabilizer 105 in the proposed apparatus which possesses advanced stability of the voltage Uo is presented in Fig. 8 and operates in the following way.

When power voltage E is applied to the first terminal 171 of the output current setter 155, direct current starts flowing through connected in series resistors first, second and third 805, 807, and 813 of the output current setter 155. Flowing through the first setter resistor 805 is the direct current I ₅ equal to

15 = (E - Vd) / Rsos (18); where V _d is the voltage between the terminals 835 and 837 of the reference voltage source terminal 801 of the output current setter 155, and flowing through the second, 807, and third, 813, setter resistors is current

16 = V _d / (R ₈ 07 + R8 ₁₃ ). (19);

In response to that, voltage Uo appears at the first terminal 843 of the third resistor 813 and, accordingly, at the second terminal 173 of the output current setter 155. Uo does not depend on the power voltage E and is equal in value to the I3 -caused voltage drop across the third resistor 813 of the output current setter 155:

Uo = v _d * R ₈ i3 / (R ₈ 07 + RS ) (20);

Using the relation (10), it is obtained that flowing through the current stabilizer 105, with the output current setter 155 configured as shown in Fig. 8, will be direct current

Io = Uo / R _m = Vd * (R ₈ 13 / (R ₈₀ 7 + R813)) / Rm (21);

Selecting values of E, R ₈ I ₃ , R ₈₀ ? and R _m as needed, the required value of I _o can always be ensured. Hence, the output voltage setter 155 shown in Fig. 8 allows for the operability of the current stabilizer 105 and of the proposed apparatus altogether. The stability of the voltage Uo and, accordingly, of the current stabilizer 105 current Io, is substantially higher than that in the schematic in Fig. 6 because the voltage V _d between the terminals 835 and 837 of the reference voltage source 801 is much more stable than the power voltage E.

In view of the above, attaining the claimed technical result is illustrated by charts in Figs. 9a- 9f. Shown there are: the input undistorted signal 901 looking like a sinewave with the minimum value thereof at zero; the real amplitude response 902 of prior art designs which is substantially nonlinear at the initial area resulting in the distortion of “near-zero” signals; the amplitude response 903 of the proposed design, which is close to linear, thus contributing to decreasing distortion of “near-zero” signals; the output signal 904 in the prior art designs looking distorted due to the flattening of the sinewave in the range of small magnitudes; and the output signal 905 in the proposed design having substantially lower level of distortion in the range of small magnitudes, whereby the dynamic range of the single-supply signal transmission apparatuses can be broadened.

Also absent, due to using the class A amplification mode, are non-linear distortions which are specific for prior art, including the prototype, where the AB amplification mode is employed.

The above-discussed embodiments do not limit the scope of the proposed and claimed apparatus. It is understood that various embodiments relating to the hardware of the particular elements are feasible. For example, the above-discussed first voltage divider formed by the resistors 443 and 445, the second voltage divider formed by the resistors 549 and 547, the third voltage divider formed by the resistors 605 and 613, the fourth voltage divider formed by the resistors 707 and 713, the fifth voltage divider formed by the resistors 805, 807 and 813 - from Figs. 4, 5, 6, 7, and 8, respectively, as well as the sixth voltage divider formed by the resistors 443 and 545 (Fig. 5), can each be a resistance divider or can be made as a divider comprising transistors connected in series, or in any other fashion providing required voltage in a midpoint of the divider. Furthermore, any of the above-mentioned resistors can be made as an element having preferably active resistance. For example, a semiconductor layer isolated of other elements can represent a resistor in an integral circuit.

Similarly, OA IC s, such as OPA 189, OPA 365 and many others, can be used as the OA 101 and 151 (in Fig. 2a). Critical parameters of the IC s are: OPEN-LOOP GAIN (at the load of 10 kiloohm) of no less than 100 dB; gain-bandwidth product of no less than 1 MHz; acceptable minimal input signal must be lower than a neutral bus potential by, for example, 0.1 V, whereas the zero offset must be many- fold less than the minimal output voltage U _ou t- FET, such as BSS83, RU1C001UN, FDN028N20, and other FET, can be used as transistors 103, 153. In such a case, the first, control, electrode is the gate, the second electrode is the drain, and the third electrode is the source. Critical parameters of the transistor 103 are: drain current Io is no less than 100 mA, voltage gate-source must exceed the minimal output voltage of the OA 101. For the transistor 153, Ros(on) must be no more than several hundred milliohms. For both transistors, parasitic capacitances must be minimal. Also, other types of transistors, such as bipolar, can be used. In such a case, the first, control, electrode is base, the second electrode is collector, and the third one is emitter. In a function of the transistor 703 (in Fig. 7), only FET, such as BSS83, RU1C001UN, etc., can be used. The key factor when selecting a FET by its parameters is that the drain-source voltage must be larger than the cutoff voltage. In a function of the current setter 155 (in Fig. 2a), beside structures presented in Figs. 6-8, other schematics capable of creating stable voltage Uo, setting the direct current Io of the current stabilizer 105, can be used.

Portions of some elements discussed above can differ, overlap, or completely coincide with portions of other elements unless specifically mentioned otherwise. Also, unless specifically mentioned otherwise, portions of some elements can be situated in various portions of other elements. Where noted that an element is “connected” to/with another element, this is understood to mean that that the element can be “directly connected” with the other element or “electrically connected” with the other element via a third element. For example, a decoupling resistor or a matching stage can be put between the OA 101 and transistor 103. Same relates to the connection of the second OA 151 and second transistor 153 in the current stabilizer 105. Also, unless mentioned otherwise, “include” and derivatives thereof, such as “including”, are understood to mean the presence of the elements mentioned, rather than the absence of any other elements.

The claimed apparatus can be made as an integral circuit, or an integral circuit assembly, or a micro board with terminals 107, 109, 127, 135. Also, the claimed apparatus can be made as an integral circuit, or an integral circuit assembly, or a micro board with terminals 107, 109, 119, 127, 129, 135, 167, to which an integral circuit, or an integral circuit assembly, or a micro board with terminals 121, 123, 125, 171, 173, 177 is connected. As well, the claimed apparatus can be made as an OA integral circuit , or an integral circuit assembly, or a micro board with terminals 111, 113, 115, 117, 119, 131, 133, 167, to which an integral circuit, or a integral circuit assembly, or a micro board with terminals 121, 123, 125, 137, 139, 141, 171, 173, 177 is connected. Equally possible are other options of decomposing the apparatus, and the claimed apparatus can as well be a portion of other structures or other IC.

Experimental results

To corroborate the attainability of the claimed technical result, breadboarding of two versions of the apparatus according to the schematic of Fig. 2a (a voltage repeater mode) was carried out. In one of the breadboard circuits, integral circuit s OPA 2189 were used as the OAs 101 and 151. In the other - integral circuit s OPA 365. For both circuits, transistors RU1C001UN and NTNS3C68NZ were used as transistors 103 and 153, respectively. The below table illustrates the results of breadboarding.

It follows from the table that the technical result that the technical result achieved by the claimed invention is definitely lies in the substantial widening of the dynamic range of the apparatus with single supply, as compared with the prior art, with, at the same time, ensuring high growth rate of the output signal.

Shown in Fig. 10 are oscillograms of the input test voltage (chart 1001) and output voltage (chart 1002) for the breadboarding circuit 1. The saw-tooth shape of the input test voltage was chosen for better demonstrativeness. The input voltage Uj _n comes over channel K3 of the oscillograph, the scale being lOmV per square. The output voltage U _ou t was indicated at the channel K4 of the oscillograph, the scale being the same. It follows from the oscillograms that distortions of the minimal output signal (saw rounding) is less than 1 mV which corroborates that the claimed technical result was achieved.

The claimed apparatus made according to the above recommendations and drawings can be very well repeated.

The claimed invention has been described based on what is currently considered feasible implementation of various embodiments thereof. It should be noted, however, that it is not limited thereby. To the contrary, it is intended for operating in various modifications and equivalent implementations keeping with the ideas, spirit and scope of the below claims. For example, the apparatus with widened dynamic range and single-supply operation can be used as a signal buffer for high-sensitive high-impedance sensor, in input stages of ADC and output stages of DAC (including integral circuit versions thereof), small signal detectors, and in many other applications. Accordingly, the description and drawings are illustrative only and do not limit implementability of the invention.

The claimed technical design is defined by the below claims.