Title:
SLC CACHE ALLOCATION
Document Type and Number:
WIPO Patent Application WO/2020/087211
Kind Code:
A1
Abstract:
Disclosed in some examples are memory devices which feature intelligent adjustments to SLC cache configurations that balances memory cell lifetime with performance. The size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device. In some examples, the size of the SLC cache can be adjusted during usage of the memory device based upon a write amplification (WA) metric of the memory device and a memory device logical saturation metric (percentage of valid user data written in the device of the total user size).
Inventors:
WANG GUANZHONG (CN)
ZHANG XU (CN)
YUEN ERIC KWOK FUNG (US)
DUAN XINGHUI (CN)
ZHANG XU (CN)
YUEN ERIC KWOK FUNG (US)
DUAN XINGHUI (CN)
Application Number:
PCT/CN2018/112452
Publication Date:
May 07, 2020
Filing Date:
October 29, 2018
Export Citation:
Assignee:
MICRON TECHNOLOGY INC (US)
International Classes:
G06F12/08
Foreign References:
| US20160098350A1 | 2016-04-07 | |||
| CN102591807A | 2012-07-18 | |||
| CN103688246A | 2014-03-26 |
Attorney, Agent or Firm:
LEE AND LI - LEAVEN IPR AGENCY LTD. (CN)
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