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Patent Searching and Data


Title:
SOFT ERROR HARD ELECTRONICS LAYOUT ARRANGEMENT AND LOGIC CELLS
Document Type and Number:
WIPO Patent Application WO/2013/082611
Kind Code:
A3
Abstract:
A method is disclosed for creating a logic integrated circuit cell from an original logic integrated circuit gate. The method includes combining the original logic integrated circuit cell with a second circuit which takes as input a complement of inputs of the original logic integrated circuit cell and provides as output complements of the output of the original logic integrated circuit cell. The method further includes connecting the combined logic integrated circuit cells, where the outputs of the combined integrated circuit cells provide the inputs for other combined circuit cells such that, when the output of the original logic integrated circuit from a first combined logic integrated circuit cell is connected as input to a second combined logic integrated circuit cell, then the output of the second circuit in the first combined logic integrated circuit cell is always also connected to the second combined logic integrated circuit cell serving as the inverse of the input signals that come from the original logic integrated circuit cell.

Inventors:
LILJA, Klas, Olof (7901 Stoneridge Drive, Suite 226Pleasanton, CA, 94588, US)
Application Number:
US2012/067628
Publication Date:
December 19, 2013
Filing Date:
December 03, 2012
Export Citation:
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Assignee:
ROBUST CHIP INC. (7901 Stoneridge Drive, Suite 226Pleasanton, CA, 94588, US)
LILJA, Klas, Olof (7901 Stoneridge Drive, Suite 226Pleasanton, CA, 94588, US)
International Classes:
H03K21/10
Foreign References:
US20100264953A12010-10-21
US20090184733A12009-07-23
US20050127971A12005-06-16
Attorney, Agent or Firm:
CAPRIOTTI, Roberto et al. (K&L Gates LLP, K&L Gates Center210 Sixth Avenu, Pittsburgh PA, 15222-2613, US)
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