The present disclosure relates generally to soft detection of received signals in a wireless communication system and, more particularly, to soft detection of a multiple input, multiple output (MIMO) signals.

BACKGROUND

MIMO is an advanced multi-antenna transmission and reception technique to improve the spectral efficiency of a wireless communication system and thereby boost the overall system capacity. MIMO systems employ multiple antennas at the transmitter and receiver to transmit and receive information. The receiver can exploit the spatial dimensions of the signal at the receiver to achieve higher spectral efficiency and higher data rates without increasing bandwidth.

While use of MIMO techniques can significantly increase the data carrying capacity of wireless systems, the complexity of the detector increases exponentially with the number of transmit antennas or/and the number of bits per constellation point. The optimal detector for MIMO is a maximum-likelihood (ML) or Maximum a posteriori Probability (MAP) detector, which performs an exhaustive search. However, the complexity of the ML or MAP detector grows exponentially with the number of transmit antennas and number of bits in a symbol. Therefore, it is not practical to implement a MIMO detector in scenarios having a large number of antennas and higher order modulation.

Several suboptimal detector structures have been proposed in literature for reducing the complexity of the MIMO detector. These can be classified into linear and nonlinear detectors. Linear detectors include zero-forcing (ZF) and minimum meansquare error (MMSE) detectors, and the nonlinear receivers include decision feedback, nulling-cancelling and variants relying on successive interference cancellation. These suboptimal detectors are easy to implement but their bit error rate (BER) or frame error rate (FER) performance is significantly inferior to that of the optimum MIMO detector.

Existing work aims to solve hard MIMO ML detection problem using quantum annealing and quantum approximate optimization techniques which gives optimal symbol s which minimizes the symbol error. Once this is done, the value of each bit is set. However soft values, showing how likely it is that a given bit in a symbol vector is a one or zero, are to be passed to the channel decoder to achieve near-capacity on multiple-antenna system. SUMMARY

In the present disclosure, quantum computing is used to solve the soft MIMO detection problem. The soft MIMO detection problem is mapped to an Ising spin glass formulation, i.e. , an Ising Hamiltonian. This Ising Hamiltonian may equivalently be represented as a Quantum Unconstrained Binary Optimization (QUBO) problem as the two are interchangeable. The soft-MIMO detection problem can be expressed as two separate hard-MIMO detection problems, which need to be solved for each bit in a received symbol. The two separate hard-MIMO detection problems differ by some penalty term A, depending on the subspace (B_0 or B_1) in which the minimization process is performed. For a symbol consisting of n bits, a total of 2n Hard-MIMO problems need to be solved.

Hard-MIMO detection can be expressed as an optimization problem, which can be solved using Quantum Annealing (QA). In one embodiment, all 2n hard-MIMO problems are combined into a single larger optimization problem that can be solved using quantum annealing methods. The detection problems are combined using a direct sum in order to concatenate two (or more) QUBO matrices into a single larger dimensional QUBO matrix. Once the solution to the larger optimization problem is obtained, it can be split up into its constituent hard-MIMO solutions because each separate optimization problem is not dependent on the others.

A first aspect of the disclosure comprise a method implemented by a soft- decision MIMO detector. The method comprises generating a quadratic unconstrained binary optimization (QUBO) matrix for a combined minimization problem comprising, for each bit in a received symbol vector, two individual minimization problems associated with respective subspaces of a symbol space. Each individual minimization problem is based on an assumption that the corresponding bit has a particular value associated with the subspace. Additionally, each individual minimization problem includes a penalty term to penalize solutions outside of the subspace. The method further comprises finding a ground state of the combined minimization problem by quantum annealing to obtain, for each bit in the received symbol, two error values based on the two minimization problems. The method further comprises computing, for each bit in the received symbol, a log-likelihood ratio (LLR) based on the associated error values found by quantum annealing.

A second aspect of the disclosure comprises a soft-decision MIMO detector/receiver. The soft-decision MIMO detector is configured to generate a quadratic unconstrained binary optimization (QUBO) matrix for a combined minimization problem comprising, for each bit in a received symbol vector, two individual minimization problems associated with respective subspaces of a symbol space. Each individual minimization problem is based on an assumption that the corresponding bit has a particular value associated with the subspace. Additionally, each individual minimization problem includes a penalty term to penalize solutions outside of the subspace. The soft- decision MIMO detector is further configured to find a ground state of the combined minimization problem by quantum annealing to obtain, for each bit in the received symbol, two error values based on the two minimization problems. The soft-decision MIMO detector is further configured to compute, for each bit in the received symbol, a log-likelihood ratio (LLR) based on the associated error values found by quantum annealing.

A third aspect of the disclosure comprises a receiver configured to perform by a soft-decision MIMO detection. The receiver comprises communication circuitry configured to receive MIMO signals and processing circuitry configured to generate a quadratic unconstrained binary optimization (QUBO) matrix for a combined minimization problem comprising, for each bit in a received symbol vector, two individual minimization problems associated with respective subspaces of a symbol space. Each individual minimization problem is based on an assumption that the corresponding bit has a particular value associated with the subspace. Additionally, each individual minimization problem includes a penalty term to penalize solutions outside of the subspace. The processing circuitry is further configured to find a ground state of the combined minimization problem by quantum annealing to obtain, for each bit in the received symbol, two error values based on the two minimization problems. The processing circuitry is further configured to compute, for each bit in the received symbol, a loglikelihood ratio (LLR) based on the associated error values found by quantum annealing.

A fourth aspect of the disclosure comprises a computer program comprising executable instructions that, when executed by a processing circuit in a detector/receiver, causes the detector/receiver to perform the method according to the first aspect.

A fifth aspect of the disclosure comprises a carrier containing a computer program according to the fourth aspect wherein the carrier is one of an electronic signal, optical signal, radio signal, or computer readable storage medium. BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates a MIMO channel.

Figure 2 illustrates a MIMO transmitter.

Figure 3 illustrates a MIMO receiver.

Figure 4 illustrates an exemplary method 300 of soft-decision MIMO detection according to one embodiment.

Figure 5 illustrates an exemplary method 300 of soft-decision MIMO detection according to one embodiment.

Figure 6 illustrates an exemplary method 300 of soft-decision MIMO detection according to one embodiment.

Figure 7 illustrates an exemplary method of generating a combined MIMO detection problem.

Figure 8 illustrates a method implemented by a soft-decision MIMO detector.

Figure 9 illustrates a soft-decision MIMO detector.

Figure 10 illustrates a MIMO receiver configured to implement soft-decision MIMO detection.

Figure 11 illustrates a 32 x 32 QU BO matrix for a 2 x 2 QPSK sOft-detection decision.

Figure 12 illustrates a time to access the quantum annealer for various MIMO configurations.

Figure 13 is a schematic block diagram illustrating an example wireless network, according to particular embodiments of the present disclosure.

Figure 14 is a schematic block diagram illustrating an example of a user equipment, according to particular embodiments of the present disclosure.

Figure 15 is a schematic block diagram illustrating an example of a virtualization environment, according to particular embodiments of the present disclosure.

Figure 16 is a schematic illustrating an example telecommunication network, according to particular embodiments of the present disclosure.

Figure 17 is a schematic block diagram illustrating an example communication system, according to particular embodiments of the present disclosure.

Figures 18-21 are flow diagrams, each of which illustrates an example method implemented in a communication system, according to particular embodiments of the present disclosure. DETAILED DESCRIPTION

Figure 1 illustrates a linear MIMO channel with N _t transmit antennas at the input and N _r receive antennas at the output. For the sake of simplicity, a single transmitter 100 and receiver 200 are assumed, but the linear MIMO channel also applies to systems with more than one transmitter and/or receiver. The transmitter simultaneously transmits N _t symbols, i’ 2, • • -’ ^S N. , from a finite symbol constellation to a receiver with N _r antennas over a linear MIMO channel. At the receiver, N _r symbols, y _l y ₂ ,...,y _Nr , are received, each comprising a linear combination of the N _t input symbols plus additive noise.

Figure 2 illustrates a transmitter 100 in a MIMO communication system with N _t transmit antennas. A transport block formatter 105 outputs ^transport blocks, where N _c <N _t . ORC bits are added to each transport block and passed to the channel encoder 110. The channel encoder 110 adds parity bits to protect the data. The resulting bitstream is passed through an interleaver 115, which interleaves the bits to increase robustness to burst errors. An adaptive controller 150 adaptively controls the interleaver size by puncturing to increase the data rate. The adaptation is done by using the information from the feedback channel, for example channel state information (CSI) sent by the receiver 200. The interleaved data is passed through a symbol mapper (modulator) 120 that maps the coded bits in the bitstream to corresponding modulation symbols depending on the modulation scheme. The symbol mapper 120 is also controlled by the adaptive controller 150. After modulation, the modulation symbols are passed through a layer mapper 125 and precoder 130. The resultant streams are then passed through an Inverse Fast Fourier Transform (IFFT) 135. The IFFT is necessary for some communication systems that implement Orthogonal Frequency Division Multiple access (OFDMA) as the access technology, such as 5G, Long Term Evolution (LTE), and LTE-Advanced (LTE-A). In other systems, the IFFT block may not be required depending on the multiple access system. The encoded stream is then transmitted through the respective antenna. Figure 3 illustrates a receiver 200 in a MIMO communication system with N _r receive antennas N _r . The received signal is converted to frequency domain by the Fast Fourier Transform (FFT) block 205. A MIMO detector 210 is used to reduce the multi antenna interference and detect the received signals. The de-mapper 215 computes the log-likelihood ratios for the bits in the received symbols output by the MIMO detector. The bit stream is then de-interleaved in a de-interleaver 220 and passed to the channel decoder 225. A ORC check 230 is performed on the output of the channel decoder 225. If the ORC is passed, the transport block is passed and an ACK is sent back to the transmitter 100 via a feedback channel. If the ORC fails, a NACK is sent back to the transmitter 100 using the feedback channel.

For soft MIMO detection using MAP algorithm, demapper 215 is integrated with MIMO detector as the soft MIMO gives the bit log-likelihood ratio. In the case of a MMSE-type detector, a separate demapper 215 that takes the MMSE output .which is in the symbol domain, to compute the bit loglikelihood ratio.

In the Multiple Input Multiple Output (MIMO) system, the received signal at the receiver can be modelled according to: y = Hs + n (1) where y e C ^Nr , H e c ^Nr ® ^Nt , s e § ^Wt and n ~ CN(0, N _o ). N _o is the noise variance. The vector s belongs to subspace § ^Wt which is the search space of possible symbol vectors s given the signal constellation. This space varies based on the number of transmit antennas N _t and dependent on the choice of modulation scheme such as Binary Phase Shift Keying (BPSK), Quadrature Phase Shift Keying (QPSK), and 16 Quadrature Amplitude Modulation (QAM).

The challenge for the detector at the receiver 200 is how to estimate the input symbol vector s, given the received symbol vector y, and known channel matrix H. The channel matrix is given by:

The optimal detector for a linear MIMO channel is a maximum likelihood (ML) detector or maximum a posteriori (MAP) detector that conducts an exhaustive search of the subspace § ^Wt for the symbol vector s that minimizes the symbol errors. In MIMO hard detection, the estimate s of the symbol vector that minimizes the symbol error is given by: s = argmin ||y-Hs|| ² (3) se§ ^N t where the term ||y - Hs|| ² is the measure of the error.

Once estimate s is obtained, the value of each bit in the transmitted symbol s is set and can be determined by mapping each symbol S in the symbol vector s to the corresponding bits represented by the symbol. The received codeword comprising a sequence of received symbols s is then input to the decoder 225 at the receiver 200 to recover the original data that was sent from the transmitter 100 to the receiver 200.

There are two main types of detectors for MIMO: hard decision detectors which decide whether a bit is zero or one (referred to herein as a hard bit), and soft decision detectors which decide how likely it is that a bit is zero or one (referred to herein as a soft bit or soft value). The soft value is typically expressed as a log-likelihood ratio.

Equation (3) represents the hard MIMO maximum likelihood detection problem and its solution provides hard bit values for decoding. To achieve near-capacity on multiple-antenna system, it is preferable to provide soft values to the decoder.

One approach to soft MIMO maximum likelihood detection is described below. For simplicity, it is assumed that each symbol s in the symbol vector s is a binary value, e. g., 0 or 1. Based on this assumption, the symbol vector s is given by:

The symbol vector s can be viewed as a bitstring. In soft-bit detection, each soft bit can be defined as the a posteriori log-likelihood ratio: ^ly) = iog [g™] (5) = l|y) is the probability that the received bit is a 1 given y, and = 1 |y) is the probability that the received bit is a 0 given y. Equation (5) can be interpreted as the log-likelihood ratio of the ith bit being equal to one or zero given y. Equation (5) can be expanded to obtain: ^ily) = log The notation S& _i ( _s )=i denotes the sum over all possible vectors s in which the ith bit is equal to 1. It is noted that b^s) = 1 and bi s) = 0 are both subspaces of § ^Wt . It is also noted that the two subspaces are disjoint. For simplicity, the subspace Cs) = 0 is denoted as B _o and bi s') = 1 is denoted as Bj.

Using the max-log approximation, Equation (6) can be re-written as:

Equation (7) includes two separate hard MIMO detection problems where two separate searches are performed for the two optimal symbol vectors in the disjoint subspaces

= 1 and bi s) = 0. Each respective minimum can be computed once the optimal symbol vectors are found.

One difficulty with soft MIMO detection derives from the fact that for each bit b _t in a symbol vector, two separate hard detection problems must be solved. The complexity of a hard MIMO maximum likelihood detector increases exponentially with the number of transmit/receive antennas and the number of bits in a symbol. Thus, for larger MIMO problems with many transmit antennas and/or higher order modulation schemes, such as 16- or 64-QAM, the soft MIMO maximum likelihood detection problem becomes exponentially difficult to determine. Due to the complexity, soft MIMO maximum likelihood detection is not practical with classical computing methods.

Existing work in the field aims to solve the hard MIMO maximum likelihood detection problem using quantum annealing and quantum approximate optimization techniques which give the optimal symbol vector s that minimizes the symbol error. Even with these relatively new quantum computing techniques, two separate minimizations need to be performed for each transmitted bit using the max-log approximation. For a symbol consisting of n bits, a total of 2n Hard-MIMO problems need to be solved.

One aspect of the present disclosure is to use quantum computing methods to generate the soft bit information for decoding by solving a single hard MIMO maximum likelihood detection problem using the quantum computer.

In one approach, the soft MIMO detection problem is mapped to an Ising spin glass formulation, i.e. , an Ising Hamiltonian. This Ising Hamiltonian may equivalently be represented as a Quantum Unconstrained Binary Optimization (QUBO) problem as the two are interchangeable. The soft-MIMO detection problem can be expressed as two separate hard-MIMO detection problems, which need to be solved for each bit in a received symbol. The two separate hard-MIMO detection problems differ by some penalty term A, depending on the subspace (B _o or in which the minimization process is performed.

Hard-MIMO detection can be expressed as an optimization problem, which can be solved using Quantum Annealing (QA). In one embodiment, all 2n hard-MIMO problems are combined into a single larger optimization problem that can be solved using quantum annealing methods. The detection problems are combined using a direct sum in order to concatenate two (or more) QUBO matrices into a single larger dimensional QUBO matrix. Once the solution to the larger optimization problem is obtained, it can be split up into its constituent hard-MIMO solutions because each separate optimization problem is not dependent on the others. Using this method of parallelization, the Time-To-Solution (TTS) is reduced or minimized by solving all optimization problems at one time instead of individually. As the number of anneal cycles in quantum annealing translates into the TTS, the larger problem can be solved using a smaller number of anneal cycles than is required when the problems are solved individually.

The results from the quantum annealer are passed to the decoder 225 for decoding. The ORC check on the decoder output yields whether the quality of result from quantum annealing is acceptable. If not, the optimization problems corresponding to bits with LLRs below the user-defined threshold, which may be dependent on the signal-to-noise ratio (SNR) for example, are combined together and solved using quantum annealing with an increased number of anneal cycles. This is done to ensure that questionable bits can be correctly classified with a larger number of anneal cycles. In this manner, the number of anneal cycles are progressively increased while successively decreasing the size of optimization problem to accelerate the TTS. Figure 12 illustrates an estimated time to access the quantum annealer for various MIMO configurations.

One advantage of the disclosed technique is that the larger soft-MIMO detection problem is solved with constant TTS due to the advantage that quantum annealing brings compared to classical computing. Furthermore, by parallelizing the subproblems of each bit into a single larger optimization problem, it is ensured that the soft-MIMO maximum likelihood detection problem may be solved in a reasonable time frame.

One aspect of the disclosure comprises techniques for combining the two disjoint hard-MIMO detection problems given by Equation (7) into a single minimization problem that is represented in matrix form, i.e. , a QUBO matrix. The soft-detection problem for a bit in a symbol can be expressed as a 2x2 QUBO matrix where each diagonal element represents a separate minimization problem for a respective subspace. The separate 2x2 matrices for each bit in each symbol s in the symbol vector b can be combined by applying a direct sum to the separate QUBO problems. This minimization problem can be expressed as a QUBO or an Ising chain. This larger minimization problem comprising multiple disjoint problems can be solved using quantum annealing, which finds the ground state energy of the larger QUBO or Ising chain. The corresponding ground state can then be used to determine the individual minima | |y - Hs| | for each bit’s two subproblems.

In order to illustrate the technique, a simple example is presented for 2 x 2 QPSK. In this example, there are two antennas at the transmitter 100 and two antennas at the receiver 200. Each symbol is complex and represents two bits. Thus, the received symbol vector s represents four bits. The problem for the detector 225 is to find the two transmitted symbols each comprising two bits; S _o = [ ₀ ] and ^,s i

The max-log approximation given by Equation (7) is used to compute the soft value for each bit. The max-log approximation can be represented as two disjoint minimization subproblems to find the minima in respective subspaces. When converting the subproblem into a QUBO formulation, the resulting subproblem for each bit will be a 4 x 4 QUBO problem since each bit requires its own problem variable. The real and imaginary parts of each symbol are not coupled to each other and can thus be seen as separate problems. If there is no coupling between QUBO variables, the variables can be considered to be independent from each other. By applying this reasoning, the independent subproblems for each bit can be combined into a single QUBO problem, where the subproblems have no coupling to each other.

In order to create the soft-MIMO subproblems min ||y-Hs|| and min ||y-Hs|| , penalty terms, penalty terms are introduced that punish solutions outside of B _o and respectively. For example, when calculating the LLR for the first bit in a symbol, a penalty term is introduced on the first qubit, which changes the Ising Hamiltonian for the case l ₀ to: and for the case to:

It can be seen that the penalty terms simply correspond to adding or subtracting some user-defined constant A to or from the relevant qubit. In the QUBO formulation, this corresponds to adding A to the corresponding diagonal terms.

In order to combine the two separate sub-problems for B ₀ and B _b into a larger optimization problem, a direct sum of the two separate problems is used. The direct sum of square matrices is a block diagonal matrix. Thus, in the 2 x 2 QPSK problem, each subproblem can be represented by a 4 x 4 QUBO matrix or Ising Hamiltonian. When the two subproblems are combined using the direct sum, the hard-MIMO detection problem for a given bit i, can be written as where Q _{i 0} is a 4x4 matrix representing the subproblem for space B _o and Q _i:1 is a 4x4 matrix representing the subproblem for space Bj.

Thus, for a single bit, the two separate hard-MIMO detection problems are combined into a single larger 8 x 8 QUBO problem given by Equation (10). By further generalizing this idea to each bit, the Qi for each bit in a symbol can be combined into a larger QUBO. For the 2 x 2 QPSK case, there are 4 bits. Combining each Qi into a single into a larger QUBO problem results in a 32 x 32 QUBO given by Equation (11).

An example of a complete QUBO where 8 different 4 x 4 hard-MIMO detection problems are encoded is shown in Figure 11 . Note that most of the off diagonal elements are zero, due to the fact that each sub-problem is independent of the others.

The full QUBO problem can be efficiently minimized using a quantum annealer in which the objective function (the QUBO matrix) is mapped onto a set of qubits, which then undergoes an annealing process to find some minimum energy ground state. This minimum energy ground state corresponds to the combination of symbols that minimize each of the subproblems that have been encoded into the larger QUBO. The minimum energy state in this case is returned as a 32 -dimensional vector that can be split it up into 8 separate 4 dimensional vectors, each of which correspond to the symbol vector s that minimizes that specific hard-MIMO detection problem. An example of this is given in Table 1 below for the 2 x 2 QPSK case. Due to the mapping of the hard-MIMO detection problem, the QUBO variables = 0 correspond to the given bit being equal to one.

Table 1

The resulting 4-dimensional hard-MIMO vectors can be used in order to calculate the norm | |y - Hs\ | to obtain the minimum value for each case. Finally using the minimum values, the LLR for each bit can be calculated classically, thus solving the soft- decision MIMO detection problem. The final LLR values are shown in Table 2 below.

Table 2

In some embodiments, a quality threshold is applied to the soft-MIMO LLR values so that if the magnitude of some LLR value falls below a user-defined threshold, the soft-decision detection can be repeated for bits that do not meet the threshold with an increased number of anneal cycles in order to ensure that the real minima is found. After the soft-decision detection process is repeated, the LLR values can be recalculated. If the same LLR is found, it can be assumed to be the correct solution, otherwise the new LLR replaces the previous one.

Figure 4 illustrates an exemplary method 300 of iterative soft-decision MIMO detection using a quality threshold. Based on the number of qubits available on the quantum annealer and their connectivity, the soft MIMO detection problem is converted to QUBO/lsing form and the combined QUBO matrix is generated by applying a direct sum on subproblems so that the combined QUBO is embeddable on the quantum annealer (block 305). The full QUBO matrix is solved by quantum annealing with a default number of anneal cycles and other parameters, such as the anneal time per sample and delay per sample (block 310). A procedure 600 for solving the full QUBO matrix is shown in Figure 7. Based on solutions from the quantum annealer, the loglikelihood ratio for each bit is computed (block 315). The LLR for each bit is compared to a predefined quality threshold to find those bits whose LLR is below threshold (block 320). If all bits meet the threshold, the process ends (block 325).

If one or more bits fail to meet the quality threshold, soft-decision MIMO detection is repeated for selected bits that fail to meet the threshold (block 330 - 345). The detector identifies selected bits whose LLR is below the threshold (block 330) and generate a reduced QUBO matrix for the bits whose LLR is below threshold (block 335). The full QUBO matrix is solved by quantum annealing with an increased number of anneal cycles (block 340). The additional number of anneal cycles may be predetermined or determined by some selected criteria. After the quantum annealing, the log-likelihood ratios for the selected bits are recomputed (block 345).

The additional soft-decision detection cycles (blocks 330-345) are repeated until the LLR for each bit in the transport block is above the threshold, or some predetermined condition is met, and the soft-ML detection values are passed to the decoder.

One example of the proposed method can be seen using 4x4 QPSK with the symbol vector [1 + Ij, -1 + Ij, 1 + Ij, -1 - lj] ^T . In this example, it can be seen that the 3rd, 7th and 8th bits are negative, meaning the LLR of these bits should be positive, and negative for the remaining bits. After combining all of the soft-MIMO detection subproblems into a single larger 128x128 QUBO problem, the resulting full QUBO matrix is solved using 50 anneal cycles yielding a total sampling time of 7788 ps. Using the solutions output by the quantum annealer, the LLR for each bit is computed. An example of the computed LLRs is given in Table 3.

Table 3

In this example, it can be seen that most bits are correctly classified, however bit

7 is incorrect and the magnitude of bit 8’s LLR is very small. A quality threshold can be set such that any bit with a LLR less than 1 should be recomputed. This can be achieved by creating the specific QUBO subproblems for those specific bits and combining them into a reduced (compared to the full QUBO matrix) QUBO matrix. This reduced QUBO matrix is then solved using an increased number of anneal cycles. For a threshold

| l(bi |y)| < 1, a separate QUBO problem is created for bits 7 and 8 and the reduced QUBO matrix is solved using 100 anneal cycles with a total sampling time of 12304 ps. The resulting soft-MIMO LLRs for bits 7 and 8 is given in Table 4. In this case, bits 7 and

8 are now correctly classified and the total sampling time was 20092 ps, compared to 23826 ps if the full QUBO matrix was solved using 150 annealing cycles.

Table 3

Figure 5 illustrates another exemplary method 400 of soft-decision MIMO detection according to one embodiment. Based on the number of qubits available on quantum annealer and their connectivity, the soft MIMO detection problem is converted to QUBO/lsing form and the combined QUBO matrix is generated by applying a direct sum on subproblems so that the combined QUBO is embeddable on the quantum annealer (block 405). The full QUBO matrix is solved by quantum annealing with a default number of anneal cycles and other parameters such as the anneal time per sample and delay per sample (block 410). A procedure 600 for solving the full QUBO matrix is shown in Figure 7. Based on solutions from the quantum annealer, the loglikelihood ratio LLR for each bit is computed (block 415). The computed LLRs are passed to a decoder for soft-decoding and a Cyclic Redundancy Check (CRC) is performed on the decoded signal (420). If the decoded signal passes the CRC check (block 425), the process ends (block 430). If the ORC check fails, one or more additional soft decision detection cycles (blocks 435 - 450) are performed until some stopping criteria is met. The number of anneal cycles is updated/increased for each additional soft-decision detection cycle (block 435) and the full QUBO matrix is solved by quantum annealing with an increased number of anneal cycles (block 440). The additional number of anneal cycles may be predetermined or determined by some selected criteria. After the quantum annealing, the log-likelihood ratios for the selected bits are recomputed (block 445). After each repeated soft-decision cycle, a stopping criteria is checked and the process repeats unit the stopping criteria is met (e.g., a predetermined number of cycles, diminishing returns) (block 450). When the stopping criteria is met, the procedure ends (block 430).

Figure 6 illustrates an exemplary method 500 of soft-decision MIMO detection that combines the methods 300 and 400. Based on the number of qubits available on quantum annealer and their connectivity, the soft MIMO detection problem is converted to QUBO/lsing form and the combined QUBO matrix is generated by applying direct sum on subproblems so that the combined QUBO is embeddable on the quantum annealer (block 505). The full QUBO matrix is solved by quantum annealing with default number of anneal cycles and other parameters such as the anneal time per sample and delay per sample (block 510). A procedure 600 for solving the full QUBO matrix is shown in Figure 7. Based on solutions from the quantum annealer, the log-likelihood ratio LLR l(bi\y) for each bit is computed (block 515). The LLR for each bit is compared to a predefined quality threshold to find those bits whose LLR is below threshold (block 520). If all bits meet the threshold (block 520), the soft bits are passed to the decoder (block 325).

If one or more bits fail to meet the quality threshold, soft-decision MIMO detection is repeated for selected bits that fail to meet the threshold (blocks 530 - 545). The detector identifies selected bits whose LLR is below the threshold (block 530) and generates a reduced QUBO matrix for the bits whose LLR is below threshold (block 535). The reduced QUBO matrix is solved by quantum annealing with an increased number of anneal cycles (block 540). The additional number of anneal cycles may be predetermined or determined by some selected criteria. After the quantum annealing, the log-likelihood ratios for the selected bits are recomputed (block 545). The additional soft-decision detection cycles (blocks 530-545) are repeated until the LLR for each bit in the transport block is above the threshold, or some predetermined condition is met, and the soft-ML detection values are passed to the decoder 225.

The decoder 225 decodes the soft symbol sequences and performs a CRC check (block 550). If the CRC check succeeds, the process ends (block 575). If not, the process controller determines whether a stopping criteria is met (block 565). If so, the process ends (block 575), If not, the quality threshold is updated (e.g., reduced) and processing returns to block 520. The soft-decision detection is repeated using the updated threshold (block 520-545).

Figure 7 illustrates the procedure 600 for quantum annealing the full QUBO matrix (blocks 310, 410 and 510 in Figures 4 - 6 respectively). The detector creates two subproblems, also referred to herein as individual minimization problems, for each bit in the transmitted symbol (block 610) and creates a combined minimization problem by concatenates the subproblems into a larger QUBO matrix using direct sum (block 620), The combined minimization problem is then solved by quantum annealing to obtain error values used to compute the log-likelihood ratios (block 630). Thee error values are passed back to the main routine and the process ends (block 640).

Figure 8 illustrates a method 700 implemented by a soft-decision MIMO detector. The detector generates a quadratic unconstrained binary optimization (QUBO) matrix for a combined minimization problem (block 710). The combined problem comprises, for each bit in a received symbol, two individual minimization problems associated with respective subspaces of a symbol space. Each minimization problem is based on an assumption that the corresponding bit has a particular value associated with the subspace. Additionally, each minimization problem includes a penalty term to penalize solutions outside of the subspace. The detector finds a ground state of the of the combined minimization problem by quantum annealing to obtain, for each bit in the received symbol, two error values based on the two individual minimization problems (block 720). The detector computes, for each bit in the received symbol, a log-likelihood ratio (LLR) based on the associated error values found by quantum annealing (block 730).

In some embodiments of the method 700, generating the combined QUBO matrix comprises applying a direct sum to QUBO submatrices for each individual minimization problem. In some embodiments of the method 700, each individual minimization problem comprises is an Ising Hamiltonian. In one example, the Ising Hamiltonian for a first subspace for each bit is in the form: and the Ising Hamiltonian for a first subspace for each bit is in the form:

In some embodiments of the method 700, finding the ground state of the combined minimization problem comprises performing quantum annealing over a predetermined number of anneal cycles and/or annealing time.

Some embodiments of the method 700 further comprising comparing the LLR for each bit to a quality threshold, and iteratively recomputing LLRs for selected bits that fail to meet the threshold.

In some embodiments of the method 700, iteratively recomputing the LLRs for selected bits that fail to meet the quality threshold comprises, for each iteration generating a reduced QUBO matrix representing a combined minimization problem for selected bits whose LLR is below the threshold, finding a ground state of the reduced minimization problem for the selected bits by quantum annealing, and re-computing LLRs for the selected bits based on new error values found by the quantum annealing.

Some embodiments of the method 700 further comprise updating annealing parameters used for the quantum annealing for each iteration. In one embodiment, updating the annealing parameters comprises increasing a number of anneal cycles and/or annealing time for quantum annealing for each successive iteration.

In some embodiments of the method 700, the iterative recomputing is performed until a predetermined condition is met. In one embodiment, the predetermined condition is when the LLRs for all bits in the received symbol meet the threshold and/or when a maximum number of annealing cycles is reached.

Some embodiments of the method 700 further comprise soft-decoding the LLRs to obtain a decoded signal.

Some embodiments of the method 700 further comprise performing a parity check of the decoded signal, and when the parity check fails, iteratively recomputing and decoding LLRs for selected until a predetermined condition is met. In some embodiments of the method 700, iteratively recomputing and decoding LLRs for selected bits comprises, for each iteration, updating annealing parameters used for quantum annealing, and re-computing LLRs for the selected bits based on new error values found by the quantum annealing. In one embodiment, the updated annealing parameters comprises a number of anneal cycles and/or annealing time for quantum annealing.

In some embodiments of the method 700, iteratively recomputing LLRs for selected bits comprises iteratively re-computing LLRs for selected bits in the received symbol vector that fail to meet the quality threshold. In some embodiments, the quality threshold is updated for each iteration.

In some embodiments of the method 700, iteratively recomputing LLRs for selected bits comprises iteratively re-computing LLRs for all bits in the received symbol vector.

In some embodiments of the method 700, the iterative recomputing and decoding is performed until the parity check succeeds or a predetermined stopping condition is met.

Figure 9 illustrates the main functional components of a soft-decision MIMO detector 800 according to an exemplary embodiment. The soft-decision MIMO detector 800 generally comprises a matrix generator 810, a quantum annealer 820 and a soft information generator 830. The various functional components of the detector 500 may be implemented by hardware and/or by software code that is executed by one or more processors or processing circuits. The various components may be embodied in proprietary hardware, or implemented in a virtual machine or container. The matrix generator 810 is configured to generate a QUBO matrix for a combined minimization problem comprising, for each bit in a received symbol, two individual minimization problems associated with respective subspaces of a symbol space. Each individual minimization problem is based on an assumption that the corresponding bit has a particular value associated with the subspace. Additionally, each individual minimization problem includes a penalty term to penalize solutions outside of the subspace. The quantum annealer 820 is configured to find a ground state of the combined minimization problem by quantum annealing to obtain, for each bit in the received symbol, two error values based on the two individual minimization problems. The soft information generator 830 is configured to compute, for each bit in the received symbol, a loglikelihood ratio (LLR) based on the associated error values found by quantum annealing. Figure 10 illustrates a receiver 900 configured to perform soft-decision MIMO detection as herein described. The receiver comprises communication circuitry 920, a processing circuitry 930, and memory 940.

The communication circuitry 920 includes connects to one or more antennas 510 shown) and comprises the radio frequency (RF) circuitry for transmitting and receiving signals over a wireless communication channel. The communication circuitry 920 may, for example, comprise a transmitter and receiver configured to operate according to the 5G/NR standard.

The processing circuitry 930 controls the overall operation of the receiver 900 and processes the signals transmitted to or received by the RECEIVER 900. The processing circuitry 930 is configured to perform soft-decision MIMO detection as herein described. The processing circuitry 930 may comprise one or more microprocessors, microcontrollers, central processing unit (CPUs), digital signal processors, application specific integrated circuits (ASICs), field programmable gate arrays (FPGA), hardware, firmware, or a combination thereof. In one exemplary embodiment, the processing circuitry is configured generate a probability distribution of states associated with different candidate symbol vectors given a received signal y and channel matrix H of the MIMO channel and obtain a received signal estimate based on the probability distribution of states. The received signal estimate comprises a plurality of bit estimates. The processing circuit is further configured to compute, for each of one or more bit estimates in the received signal estimate, soft bit information based on the probability distribution of states.

Memory 940 comprises both volatile and non-volatile memory for storing computer program code and data needed by the processing circuitry 930 for operation. Memory 940 may comprise any tangible, non-transitory computer-readable storage medium for storing data including electronic, magnetic, optical, electromagnetic, or semiconductor data storage. Memory 940 stores a computer program 950 comprising executable instructions that configure the processing circuitry 930 to implement the methods and processes as herein described including the methods 300 - 700 shown in Figures 4 - 8, respectively. A computer program in this regard may comprise one or more code modules corresponding to the means or units described above. In general, computer program instructions and configuration information are stored in a non-volatile memory, such as a ROM, erasable programmable read only memory (EPROM) or flash memory. Temporary data generated during operation may be stored in a volatile memory, such as a random access memory (RAM). In some embodiments, computer program 950 for configuring the processing circuitry 930 as herein described may be stored in a removable memory, such as a portable compact disc, portable digital video disc, or other removable media. The computer program 950 may also be embodied in a carrier such as an electronic signal, optical signal, radio signal, or computer readable storage medium.

Those skilled in the art will also appreciate that embodiments herein further include corresponding computer programs. A computer program comprises instructions that, when executed on at least one processor of an apparatus, cause the apparatus to carry out any of the respective processing described above. A computer program in this regard may comprise one or more code modules corresponding to the means or units described above.

Embodiments further include a carrier containing such a computer program. This carrier may comprise one of an electronic signal, optical signal, radio signal, or computer readable storage medium.

In this regard, embodiments herein also include a computer program product stored on a non-transitory computer readable (storage or recording) medium and comprising instructions that, when executed by a processor of an apparatus, cause the apparatus to perform as described above.

Embodiments further include a computer program product comprising program code portions for performing the steps of any of the embodiments herein when the computer program product is executed by a computing device. This computer program product may be stored on a computer readable recording medium.

Although the subject matter described herein may be implemented in any appropriate type of system using any suitable components, the embodiments disclosed herein are described in relation to a wireless network, such as the example wireless network illustrated in Figure 13. For simplicity, the wireless network of Figure 13 only depicts network 1106, network nodes 1160 and 1160b, and WDs 1110, 1110b, and 1110c. In practice, a wireless network may further include any additional elements suitable to support communication between wireless devices or between a wireless device and another communication device, such as a landline telephone, a service provider, or any other network node or end device. Of the illustrated components, network node 1160 and wireless device (WD) 1110 are depicted with additional detail. The wireless network may provide communication and other types of services to one or more wireless devices to facilitate the wireless devices’ access to and/or use of the services provided by, or via, the wireless network.

The wireless network may comprise and/or interface with any type of communication, telecommunication, data, cellular, and/or radio network or other similar type of system. In some embodiments, the wireless network may be configured to operate according to specific standards or other types of predefined rules or procedures. Thus, particular embodiments of the wireless network may implement communication standards, such as Global System for Mobile Communications (GSM), Universal Mobile Telecommunications System (UMTS), Long Term Evolution (LTE), Narrowband Internet of Things (NB-loT), and/or other suitable 2G, 3G, 4G, or 5G standards; wireless local area network (WLAN) standards, such as the IEEE 802.11 standards; and/or any other appropriate wireless communication standard, such as the Worldwide Interoperability for Microwave Access (WiMax), Bluetooth, Z-Wave and/or ZigBee standards.

Network 1106 may comprise one or more backhaul networks, core networks, IP networks, public switched telephone networks (PSTNs), packet data networks, optical networks, wide-area networks (WANs), local area networks (LANs), wireless local area networks (WLANs), wired networks, wireless networks, metropolitan area networks, and other networks to enable communication between devices.

Network node 1160 and WD 1110 comprise various components described in more detail below. These components work together in order to provide network node and/or wireless device functionality, such as providing wireless connections in a wireless network. In different embodiments, the wireless network may comprise any number of wired or wireless networks, network nodes, base stations, controllers, wireless devices, relay stations, and/or any other components or systems that may facilitate or participate in the communication of data and/or signals whether via wired or wireless connections.

As used herein, network node refers to equipment capable, configured, arranged and/or operable to communicate directly or indirectly with a wireless device and/or with other network nodes or equipment in the wireless network to enable and/or provide wireless access to the wireless device and/or to perform other functions (e.g., administration) in the wireless network. Examples of network nodes include, but are not limited to, access points (APs) (e.g., radio access points), base stations (BSs) (e.g., radio base stations, Node Bs, evolved Node Bs (eNBs) and NR NodeBs (gNBs)). Base stations may be categorized based on the amount of coverage they provide (or, stated differently, their transmit power level) and may then also be referred to as femto base stations, pico base stations, micro base stations, or macro base stations. A base station may be a relay node or a relay donor node controlling a relay. A network node may also include one or more (or all) parts of a distributed radio base station such as centralized digital units and/or remote radio units (RRUs), sometimes referred to as Remote Radio Heads (RRHs). Such remote radio units may or may not be integrated with an antenna as an antenna integrated radio. Parts of a distributed radio base station may also be referred to as nodes in a distributed antenna system (DAS). Yet further examples of network nodes include multi-standard radio (MSR) equipment such as MSR BSs, network controllers such as radio network controllers (RNCs) or base station controllers (BSCs), base transceiver stations (BTSs), transmission points, transmission nodes, multi-cell/multicast coordination entities (MCEs), core network nodes (e.g., MSCs, MMEs), O&M nodes, OSS nodes, SON nodes, positioning nodes (e.g., E-SMLCs), and/or MDTs. As another example, a network node may be a virtual network node as described in more detail below. More generally, however, network nodes may represent any suitable device (or group of devices) capable, configured, arranged, and/or operable to enable and/or provide a wireless device with access to the wireless network or to provide some service to a wireless device that has accessed the wireless network.

In Figure 13, network node 1160 includes processing circuitry 1170, device readable medium 1180, interface 1190, auxiliary equipment 1184, power source 1186, power circuitry 1187, and antenna 1162. Although network node 1160 illustrated in the example wireless network of Figure 13 may represent a device that includes the illustrated combination of hardware components, other embodiments may comprise network nodes with different combinations of components. It is to be understood that a network node comprises any suitable combination of hardware and/or software needed to perform the tasks, features, functions and methods disclosed herein. Moreover, while the components of network node 1160 are depicted as single boxes located within a larger box, or nested within multiple boxes, in practice, a network node may comprise multiple different physical components that make up a single illustrated component (e.g., device readable medium 1180 may comprise multiple separate hard drives as well as multiple RAM modules).

Similarly, network node 1160 may be composed of multiple physically separate components (e.g., a NodeB component and a RNC component, or a BTS component and a BSC component, etc.), which may each have their own respective components. In certain scenarios in which network node 1160 comprises multiple separate components (e.g., BTS and BSC components), one or more of the separate components may be shared among several network nodes. For example, a single RNC may control multiple NodeB’s. In such a scenario, each unique NodeB and RNC pair, may in some instances be considered a single separate network node. In some embodiments, network node 1160 may be configured to support multiple radio access technologies (RATs). In such embodiments, some components may be duplicated (e.g., separate device readable medium 1180 for the different RATs) and some components may be reused (e.g., the same antenna 1162 may be shared by the RATs). Network node 1160 may also include multiple sets of the various illustrated components for different wireless technologies integrated into network node 1160, such as, for example, GSM, WCDMA, LTE, NR, WiFi, or Bluetooth wireless technologies. These wireless technologies may be integrated into the same or different chip or set of chips and other components within network node 1160.

Processing circuitry 1170 is configured to perform any determining, calculating, or similar operations (e.g., certain obtaining operations) described herein as being provided by a network node. These operations performed by processing circuitry 1170 may include processing information obtained by processing circuitry 1170 by, for example, converting the obtained information into other information, comparing the obtained information or converted information to information stored in the network node, and/or performing one or more operations based on the obtained information or converted information, and as a result of said processing making a determination.

Processing circuitry 1170 may comprise a combination of one or more of a microprocessor, controller, microcontroller, central processing unit, digital signal processor, application-specific integrated circuit, field programmable gate array, or any other suitable computing device, resource, or combination of hardware, software and/or encoded logic operable to provide, either alone or in conjunction with other network node 1160 components, such as device readable medium 1180, network node 1160 functionality. For example, processing circuitry 1170 may execute instructions stored in device readable medium 1180 or in memory within processing circuitry 1170. Such functionality may include providing any of the various wireless features, functions, or benefits discussed herein. In some embodiments, processing circuitry 1170 may include a system on a chip (SOO).

In some embodiments, processing circuitry 1170 may include one or more of radio frequency (RF) transceiver circuitry 1172 and baseband processing circuitry 1174. In some embodiments, radio frequency (RF) transceiver circuitry 1172 and baseband processing circuitry 1174 may be on separate chips (or sets of chips), boards, or units, such as radio units and digital units. In alternative embodiments, part or all of RF transceiver circuitry 1172 and baseband processing circuitry 1174 may be on the same chip or set of chips, boards, or units

In certain embodiments, some or all of the functionality described herein as being provided by a network node, base station, eNB or other such network device may be performed by processing circuitry 1170 executing instructions stored on device readable medium 1180 or memory within processing circuitry 1170. In alternative embodiments, some or all of the functionality may be provided by processing circuitry 1170 without executing instructions stored on a separate or discrete device readable medium, such as in a hard-wired manner. In any of those embodiments, whether executing instructions stored on a device readable storage medium or not, processing circuitry 1170 can be configured to perform the described functionality. The benefits provided by such functionality are not limited to processing circuitry 1170 alone or to other components of network node 1160, but are enjoyed by network node 1160 as a whole, and/or by end users and the wireless network generally.

Device readable medium 1180 may comprise any form of volatile or non-volatile computer readable memory including, without limitation, persistent storage, solid-state memory, remotely mounted memory, magnetic media, optical media, random access memory (RAM), read-only memory (ROM), mass storage media (for example, a hard disk), removable storage media (for example, a flash drive, a Compact Disk (CD) or a Digital Video Disk (DVD)), and/or any other volatile or non-volatile, non-transitory device readable and/or computer-executable memory devices that store information, data, and/or instructions that may be used by processing circuitry 1170. Device readable medium 1180 may store any suitable instructions, data or information, including a computer program, software, an application including one or more of logic, rules, code, tables, etc. and/or other instructions capable of being executed by processing circuitry 1170 and, utilized by network node 1160. Device readable medium 1180 may be used to store any calculations made by processing circuitry 1170 and/or any data received via interface 1190. In some embodiments, processing circuitry 1170 and device readable medium 1180 may be considered to be integrated.

Interface 1190 is used in the wired or wireless communication of signalling and/or data between network node 1160, network 1106, and/or WDs 1110. As illustrated, interface 1190 comprises port(s)/terminal(s) 1194 to send and receive data, for example to and from network 1106 over a wired connection. Interface 1190 also includes radio front end circuitry 1192 that may be coupled to, or in certain embodiments a part of, antenna 1162. Radio front end circuitry 1192 comprises filters 1198 and amplifiers 1196. Radio front end circuitry 1192 may be connected to antenna 1162 and processing circuitry 1170. Radio front end circuitry may be configured to condition signals communicated between antenna 1162 and processing circuitry 1170. Radio front end circuitry 1192 may receive digital data that is to be sent out to other network nodes or WDs via a wireless connection. Radio front end circuitry 1192 may convert the digital data into a radio signal having the appropriate channel and bandwidth parameters using a combination of filters 1198 and/or amplifiers 1196. The radio signal may then be transmitted via antenna 1162. Similarly, when receiving data, antenna 1162 may collect radio signals which are then converted into digital data by radio front end circuitry 1192. The digital data may be passed to processing circuitry 1170. In other embodiments, the interface may comprise different components and/or different combinations of components.

In certain alternative embodiments, network node 1160 may not include separate radio front end circuitry 1192, instead, processing circuitry 1170 may comprise radio front end circuitry and may be connected to antenna 1162 without separate radio front end circuitry 1192. Similarly, in some embodiments, all or some of RF transceiver circuitry 1172 may be considered a part of interface 1190. In still other embodiments, interface 1190 may include one or more ports or terminals 1194, radio front end circuitry 1192, and RF transceiver circuitry 1172, as part of a radio unit (not shown), and interface 1190 may communicate with baseband processing circuitry 1174, which is part of a digital unit (not shown).

Antenna 1162 may include one or more antennas, or antenna arrays, configured to send and/or receive wireless signals. Antenna 1162 may be coupled to radio front end circuitry 1190 and may be any type of antenna capable of transmitting and receiving data and/or signals wirelessly. In some embodiments, antenna 1162 may comprise one or more omni-directional, sector or panel antennas operable to transmit/receive radio signals between, for example, 2 GHz and 66 GHz. An omni-directional antenna may be used to transmit/receive radio signals in any direction, a sector antenna may be used to transmit/receive radio signals from devices within a particular area, and a panel antenna may be a line of sight antenna used to transmit/receive radio signals in a relatively straight line. In some instances, the use of more than one antenna may be referred to as MIMO. In certain embodiments, antenna 1162 may be separate from network node 1160 and may be connectable to network node 1160 through an interface or port.

Antenna 1162, interface 1190, and/or processing circuitry 1170 may be configured to perform any receiving operations and/or certain obtaining operations described herein as being performed by a network node. Any information, data and/or signals may be received from a wireless device, another network node and/or any other network equipment. Similarly, antenna 1162, interface 1190, and/or processing circuitry 1170 may be configured to perform any transmitting operations described herein as being performed by a network node. Any information, data and/or signals may be transmitted to a wireless device, another network node and/or any other network equipment.

Power circuitry 1187 may comprise, or be coupled to, power management circuitry and is configured to supply the components of network node 1160 with power for performing the functionality described herein. Power circuitry 1187 may receive power from power source 1186. Power source 1186 and/or power circuitry 1187 may be configured to provide power to the various components of network node 1160 in a form suitable for the respective components (e.g., at a voltage and current level needed for each respective component). Power source 1186 may either be included in, or external to, power circuitry 1187 and/or network node 1160. For example, network node 1160 may be connectable to an external power source (e.g., an electricity outlet) via an input circuitry or interface such as an electrical cable, whereby the external power source supplies power to power circuitry 1187. As a further example, power source 1186 may comprise a source of power in the form of a battery or battery pack which is connected to, or integrated in, power circuitry 1187. The battery may provide backup power should the external power source fail. Other types of power sources, such as photovoltaic devices, may also be used.

Alternative embodiments of network node 1160 may include additional components beyond those shown in Figure 13 that may be responsible for providing certain aspects of the network node’s functionality, including any of the functionality described herein and/or any functionality necessary to support the subject matter described herein. For example, network node 1160 may include user interface equipment to allow input of information into network node 1160 and to allow output of information from network node 1160. This may allow a user to perform diagnostic, maintenance, repair, and other administrative functions for network node 1160.

As used herein, wireless device (WD) refers to a device capable, configured, arranged and/or operable to communicate wirelessly with network nodes and/or other wireless devices. Unless otherwise noted, the term WD may be used interchangeably herein with user equipment (UE). Communicating wirelessly may involve transmitting and/or receiving wireless signals using electromagnetic waves, radio waves, infrared waves, and/or other types of signals suitable for conveying information through air. In some embodiments, a WD may be configured to transmit and/or receive information without direct human interaction. For instance, a WD may be designed to transmit information to a network on a predetermined schedule, when triggered by an internal or external event, or in response to requests from the network. Examples of a WD include, but are not limited to, a smart phone, a mobile phone, a cell phone, a voice over IP (VoIP) phone, a wireless local loop phone, a desktop computer, a personal digital assistant (PDA), a wireless cameras, a gaming console or device, a music storage device, a playback appliance, a wearable terminal device, a wireless endpoint, a mobile station, a tablet, a laptop, a laptop-embedded equipment (LEE), a laptop-mounted equipment (LME), a smart device, a wireless customer-premise equipment (CPE), a vehicle-mounted wireless terminal device, etc. A WD may support device-to-device (D2D) communication, for example by implementing a 3GPP standard for sidelink communication, vehicle-to-vehicle (V2V), vehicle-to-infrastructure (V2I), vehicle-to- everything (V2X) and may in this case be referred to as a D2D communication device. As yet another specific example, in an Internet of Things (loT) scenario, a WD may represent a machine or other device that performs monitoring and/or measurements, and transmits the results of such monitoring and/or measurements to another WD and/or a network node. The WD may in this case be a machine-to-machine (M2M) device, which may in a 3GPP context be referred to as an MTC device. As one particular example, the WD may be a UE implementing the 3GPP narrow band internet of things (NB-loT) standard. Particular examples of such machines or devices are sensors, metering devices such as power meters, industrial machinery, or home or personal appliances (e.g. refrigerators, televisions, etc.) personal wearables (e.g., watches, fitness trackers, etc.). In other scenarios, a WD may represent a vehicle or other equipment that is capable of monitoring and/or reporting on its operational status or other functions associated with its operation. A WD as described above may represent the endpoint of a wireless connection, in which case the device may be referred to as a wireless terminal. Furthermore, a WD as described above may be mobile, in which case it may also be referred to as a mobile device or a mobile terminal.

As illustrated, wireless device 1110 includes antenna 1111 , interface 1114, processing circuitry 1120, device readable medium 1130, user interface equipment 1132, auxiliary equipment 1134, power source 1136 and power circuitry 1137. WD 1110 may include multiple sets of one or more of the illustrated components for different wireless technologies supported by WD 1110, such as, for example, GSM, WCDMA, LTE, NR, WiFi, WiMAX, NB-loT, or Bluetooth wireless technologies, just to mention a few. These wireless technologies may be integrated into the same or different chips or set of chips as other components within WD 1110.

Antenna 1111 may include one or more antennas or antenna arrays, configured to send and/or receive wireless signals, and is connected to interface 1114. In certain alternative embodiments, antenna 1111 may be separate from WD 1110 and be connectable to WD 1110 through an interface or port. Antenna 1111 , interface 1114, and/or processing circuitry 1120 may be configured to perform any receiving or transmitting operations described herein as being performed by a WD. Any information, data and/or signals may be received from a network node and/or another WD. In some embodiments, radio front end circuitry and/or antenna 1111 may be considered an interface.

As illustrated, interface 1114 comprises radio front end circuitry 1112 and antenna 1111. Radio front end circuitry 1112 comprise one or more filters 1118 and amplifiers 1116. Radio front end circuitry 1114 is connected to antenna 1111 and processing circuitry 1120, and is configured to condition signals communicated between antenna 1111 and processing circuitry 1120. Radio front end circuitry 1112 may be coupled to or a part of antenna 1111. In some embodiments, WD 1110 may not include separate radio front end circuitry 1112; rather, processing circuitry 1120 may comprise radio front end circuitry and may be connected to antenna 1111. Similarly, in some embodiments, some or all of RF transceiver circuitry 1122 may be considered a part of interface 1114. Radio front end circuitry 1112 may receive digital data that is to be sent out to other network nodes or WDs via a wireless connection. Radio front end circuitry 1112 may convert the digital data into a radio signal having the appropriate channel and bandwidth parameters using a combination of filters 1118 and/or amplifiers 1116. The radio signal may then be transmitted via antenna 1111. Similarly, when receiving data, antenna 1111 may collect radio signals which are then converted into digital data by radio front end circuitry 1112. The digital data may be passed to processing circuitry 1120. In other embodiments, the interface may comprise different components and/or different combinations of components.

Processing circuitry 1120 may comprise a combination of one or more of a microprocessor, controller, microcontroller, central processing unit, digital signal processor, application-specific integrated circuit, field programmable gate array, or any other suitable computing device, resource, or combination of hardware, software, and/or encoded logic operable to provide, either alone or in conjunction with other WD 1110 components, such as device readable medium 1130, WD 1110 functionality. Such functionality may include providing any of the various wireless features or benefits discussed herein. For example, processing circuitry 1120 may execute instructions stored in device readable medium 1130 or in memory within processing circuitry 1120 to provide the functionality disclosed herein.

As illustrated, processing circuitry 1120 includes one or more of RF transceiver circuitry 1122, baseband processing circuitry 1124, and application processing circuitry 1126. In other embodiments, the processing circuitry may comprise different components and/or different combinations of components. In certain embodiments processing circuitry 1120 of WD 1110 may comprise a SOC. In some embodiments, RF transceiver circuitry 1122, baseband processing circuitry 1124, and application processing circuitry 1126 may be on separate chips or sets of chips. In alternative embodiments, part or all of baseband processing circuitry 1124 and application processing circuitry 1126 may be combined into one chip or set of chips, and RF transceiver circuitry 1122 may be on a separate chip or set of chips. In still alternative embodiments, part or all of RF transceiver circuitry 1122 and baseband processing circuitry 1124 may be on the same chip or set of chips, and application processing circuitry 1126 may be on a separate chip or set of chips. In yet other alternative embodiments, part or all of RF transceiver circuitry 1122, baseband processing circuitry 1124, and application processing circuitry 1126 may be combined in the same chip or set of chips. In some embodiments, RF transceiver circuitry 1122 may be a part of interface 1114. RF transceiver circuitry 1122 may condition RF signals for processing circuitry 1120.

In certain embodiments, some or all of the functionality described herein as being performed by a WD may be provided by processing circuitry 1120 executing instructions stored on device readable medium 1130, which in certain embodiments may be a computer-readable storage medium. In alternative embodiments, some or all of the functionality may be provided by processing circuitry 1120 without executing instructions stored on a separate or discrete device readable storage medium, such as in a hardwired manner. In any of those particular embodiments, whether executing instructions stored on a device readable storage medium or not, processing circuitry 1120 can be configured to perform the described functionality. The benefits provided by such functionality are not limited to processing circuitry 1120 alone or to other components of WD 1110, but are enjoyed by WD 1110 as a whole, and/or by end users and the wireless network generally.

Processing circuitry 1120 may be configured to perform any determining, calculating, or similar operations (e.g., certain obtaining operations) described herein as being performed by a WD. These operations, as performed by processing circuitry 1120, may include processing information obtained by processing circuitry 1120 by, for example, converting the obtained information into other information, comparing the obtained information or converted information to information stored by WD 1110, and/or performing one or more operations based on the obtained information or converted information, and as a result of said processing making a determination.

Device readable medium 1130 may be operable to store a computer program, software, an application including one or more of logic, rules, code, tables, etc. and/or other instructions capable of being executed by processing circuitry 1120. Device readable medium 1130 may include computer memory (e.g., Random Access Memory (RAM) or Read Only Memory (ROM)), mass storage media (e.g., a hard disk), removable storage media (e.g., a Compact Disk (CD) or a Digital Video Disk (DVD)), and/or any other volatile or non-volatile, non-transitory device readable and/or computer executable memory devices that store information, data, and/or instructions that may be used by processing circuitry 1120. In some embodiments, processing circuitry 1120 and device readable medium 1130 may be considered to be integrated.

User interface equipment 1132 may provide components that allow for a human user to interact with WD 1110. Such interaction may be of many forms, such as visual, audial, tactile, etc. User interface equipment 1132 may be operable to produce output to the user and to allow the user to provide input to WD 1110. The type of interaction may vary depending on the type of user interface equipment 1132 installed in WD 1110. For example, if WD 1110 is a smart phone, the interaction may be via a touch screen; if WD 1110 is a smart meter, the interaction may be through a screen that provides usage (e.g., the number of gallons used) or a speaker that provides an audible alert (e.g., if smoke is detected). User interface equipment 1132 may include input interfaces, devices and circuits, and output interfaces, devices and circuits. User interface equipment 1132 is configured to allow input of information into WD 1110, and is connected to processing circuitry 1120 to allow processing circuitry 1120 to process the input information. User interface equipment 1132 may include, for example, a microphone, a proximity or other sensor, keys/buttons, a touch display, one or more cameras, a USB port, or other input circuitry. User interface equipment 1132 is also configured to allow output of information from WD 1110, and to allow processing circuitry 1120 to output information from WD 1110. User interface equipment 1132 may include, for example, a speaker, a display, vibrating circuitry, a USB port, a headphone interface, or other output circuitry. Using one or more input and output interfaces, devices, and circuits, of user interface equipment 1132, WD 1110 may communicate with end users and/or the wireless network, and allow them to benefit from the functionality described herein.

Auxiliary equipment 1134 is operable to provide more specific functionality which may not be generally performed by WDs. This may comprise specialized sensors for doing measurements for various purposes, interfaces for additional types of communication such as wired communications etc. The inclusion and type of components of auxiliary equipment 1134 may vary depending on the embodiment and/or scenario.

Power source 1136 may, in some embodiments, be in the form of a battery or battery pack. Other types of power sources, such as an external power source (e.g., an electricity outlet), photovoltaic devices or power cells, may also be used. WD 1110 may further comprise power circuitry 1137 for delivering power from power source 1136 to the various parts of WD 1110 which need power from power source 1136 to carry out any functionality described or indicated herein. Power circuitry 1137 may in certain embodiments comprise power management circuitry. Power circuitry 1137 may additionally or alternatively be operable to receive power from an external power source; in which case WD 1110 may be connectable to the external power source (such as an electricity outlet) via input circuitry or an interface such as an electrical power cable. Power circuitry 1137 may also in certain embodiments be operable to deliver power from an external power source to power source 1136. This may be, for example, for the charging of power source 1136. Power circuitry 1137 may perform any formatting, converting, or other modification to the power from power source 1136 to make the power suitable for the respective components of WD 1110 to which power is supplied.

Figure 14 illustrates one embodiment of a UE in accordance with various aspects described herein. As used herein, a user equipment or UE may not necessarily have a user in the sense of a human user who owns and/or operates the relevant device. Instead, a UE may represent a device that is intended for sale to, or operation by, a human user but which may not, or which may not initially, be associated with a specific human user (e.g., a smart sprinkler controller). Alternatively, a UE may represent a device that is not intended for sale to, or operation by, an end user but which may be associated with or operated for the benefit of a user (e.g., a smart power meter). UE 12200 may be any UE identified by the 3rd Generation Partnership Project (3GPP), including a NB-loT UE, a machine type communication (MTC) UE, and/or an enhanced MTC (eMTC) UE. UE 1200, as illustrated in Figure 14, is one example of a WD configured for communication in accordance with one or more communication standards promulgated by the 3rd Generation Partnership Project (3GPP), such as 3GPP’s GSM, UMTS, LTE, and/or 5G standards. As mentioned previously, the term WD and UE may be used interchangeable. Accordingly, although Figure 14 is a UE, the components discussed herein are equally applicable to a WD, and vice-versa.

In Figure 14, UE 1200 includes processing circuitry 1201 that is operatively coupled to input/output interface 1205, radio frequency (RF) interface 1209, network connection interface 1211 , memory 1215 including random access memory (RAM) 1217, read-only memory (ROM) 1219, and storage medium 1221 or the like, communication subsystem 1231 , power source 1233, and/or any other component, or any combination thereof. Storage medium 1221 includes operating system 1223, application program 1225, and data 1227. In other embodiments, storage medium 1221 may include other similar types of information. Certain UEs may utilize all of the components shown in Figure 14, or only a subset of the components. The level of integration between the components may vary from one UE to another UE. Further, certain UEs may contain multiple instances of a component, such as multiple processors, memories, transceivers, transmitters, receivers, etc.

In Figure 14, processing circuitry 1201 may be configured to process computer instructions and data. Processing circuitry 1201 may be configured to implement any sequential state machine operative to execute machine instructions stored as machine- readable computer programs in the memory, such as one or more hardware- implemented state machines (e.g., in discrete logic, FPGA, ASIC, etc.); programmable logic together with appropriate firmware; one or more stored program, general-purpose processors, such as a microprocessor or Digital Signal Processor (DSP), together with appropriate software; or any combination of the above. For example, the processing circuitry 1201 may include two central processing units (CPUs). Data may be information in a form suitable for use by a computer.

In the depicted embodiment, input/output interface 1205 may be configured to provide a communication interface to an input device, output device, or input and output device. UE 1200 may be configured to use an output device via input/output interface 1205. An output device may use the same type of interface port as an input device. For example, a USB port may be used to provide input to and output from UE 1200. The output device may be a speaker, a sound card, a video card, a display, a monitor, a printer, an actuator, an emitter, a smartcard, another output device, or any combination thereof. UE 1200 may be configured to use an input device via input/output interface 1205 to allow a user to capture information into UE 1200. The input device may include a touch-sensitive or presence-sensitive display, a camera (e.g., a digital camera, a digital video camera, a web camera, etc.), a microphone, a sensor, a mouse, a trackball, a directional pad, a trackpad, a scroll wheel, a smartcard, and the like. The presencesensitive display may include a capacitive or resistive touch sensor to sense input from a user. A sensor may be, for instance, an accelerometer, a gyroscope, a tilt sensor, a force sensor, a magnetometer, an optical sensor, a proximity sensor, another like sensor, or any combination thereof. For example, the input device may be an accelerometer, a magnetometer, a digital camera, a microphone, and an optical sensor.

In Figure 14, RF interface 1209 may be configured to provide a communication interface to RF components such as a transmitter, a receiver, and an antenna. Network connection interface 1211 may be configured to provide a communication interface to network 1243a. Network 1243a may encompass wired and/or wireless networks such as a local-area network (LAN), a wide-area network (WAN), a computer network, a wireless network, a telecommunications network, another like network or any combination thereof. For example, network 1243a may comprise a Wi-Fi network. Network connection interface 1211 may be configured to include a receiver and a transmitter interface used to communicate with one or more other devices over a communication network according to one or more communication protocols, such as Ethernet, TCP/IP, SONET, ATM, or the like. Network connection interface 1211 may implement receiver and transmitter functionality appropriate to the communication network links (e.g., optical, electrical, and the like). The transmitter and receiver functions may share circuit components, software or firmware, or alternatively may be implemented separately.

RAM 1217 may be configured to interface via bus 1202 to processing circuitry 1201 to provide storage or caching of data or computer instructions during the execution of software programs such as the operating system, application programs, and device drivers. ROM 1219 may be configured to provide computer instructions or data to processing circuitry 1201. For example, ROM 1219 may be configured to store invariant low-level system code or data for basic system functions such as basic input and output (I/O), startup, or reception of keystrokes from a keyboard that are stored in a non-volatile memory. Storage medium 1221 may be configured to include memory such as RAM, ROM, programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), magnetic disks, optical disks, floppy disks, hard disks, removable cartridges, or flash drives. In one example, storage medium 1221 may be configured to include operating system 1223, application program 1225 such as a web browser application, a widget or gadget engine or another application, and data file 1227. Storage medium 1221 may store, for use by UE 1200, any of a variety of various operating systems or combinations of operating systems.

Storage medium 1221 may be configured to include a number of physical drive units, such as redundant array of independent disks (RAID), floppy disk drive, flash memory, USB flash drive, external hard disk drive, thumb drive, pen drive, key drive, high-density digital versatile disc (HD-DVD) optical disc drive, internal hard disk drive, Blu-Ray optical disc drive, holographic digital data storage (HDDS) optical disc drive, external mini-dual in-line memory module (DIMM), synchronous dynamic random access memory (SDRAM), external micro-DIMM SDRAM, smartcard memory such as a subscriber identity module or a removable user identity (SIM/RUIM) module, other memory, or any combination thereof. Storage medium 1221 may allow UE 1200 to access computer-executable instructions, application programs or the like, stored on transitory or non-transitory memory media, to off-load data, or to upload data. An article of manufacture, such as one utilizing a communication system may be tangibly embodied in storage medium 1221 , which may comprise a device readable medium. In Figure 14, processing circuitry 1201 may be configured to communicate with network 1243b using communication subsystem 1231. Network 1243a and network 1243b may be the same network or networks or different network or networks. Communication subsystem 1231 may be configured to include one or more transceivers used to communicate with network 1243b. For example, communication subsystem 1231 may be configured to include one or more transceivers used to communicate with one or more remote transceivers of another device capable of wireless communication such as another WD, UE, or base station of a radio access network (RAN) according to one or more communication protocols, such as IEEE 802.13, CDMA, WCDMA, GSM, LTE, UTRAN, WiMax, or the like. Each transceiver may include transmitter 1233 and/or receiver 1235 to implement transmitter or receiver functionality, respectively, appropriate to the RAN links (e.g., frequency allocations and the like). Further, transmitter 1233 and receiver 1235 of each transceiver may share circuit components, software or firmware, or alternatively may be implemented separately.

In the illustrated embodiment, the communication functions of communication subsystem 1231 may include data communication, voice communication, multimedia communication, short-range communications such as Bluetooth, near-field communication, location-based communication such as the use of the global positioning system (GPS) to determine a location, another like communication function, or any combination thereof. For example, communication subsystem 1231 may include cellular communication, Wi-Fi communication, Bluetooth communication, and GPS communication. Network 1243b may encompass wired and/or wireless networks such as a local-area network (LAN), a wide-area network (WAN), a computer network, a wireless network, a telecommunications network, another like network or any combination thereof. For example, network 1243b may be a cellular network, a Wi-Fi network, and/or a near-field network. Power source 1213 may be configured to provide alternating current (AC) or direct current (DC) power to components of UE 1200.

The features, benefits and/or functions described herein may be implemented in one of the components of UE 1200 or partitioned across multiple components of UE 1200. Further, the features, benefits, and/or functions described herein may be implemented in any combination of hardware, software or firmware. In one example, communication subsystem 1231 may be configured to include any of the components described herein. Further, processing circuitry 1201 may be configured to communicate with any of such components over bus 1202. In another example, any of such components may be represented by program instructions stored in memory that when executed by processing circuitry 1201 perform the corresponding functions described herein. In another example, the functionality of any of such components may be partitioned between processing circuitry 1201 and communication subsystem 1231. In another example, the non-computationally intensive functions of any of such components may be implemented in software or firmware and the computationally intensive functions may be implemented in hardware.

Figure 15 is a schematic block diagram illustrating a virtualization environment 1300 in which functions implemented by some embodiments may be virtualized. In the present context, virtualizing means creating virtual versions of apparatuses or devices which may include virtualizing hardware platforms, storage devices and networking resources. As used herein, virtualization can be applied to a node (e.g., a virtualized base station or a virtualized radio access node) or to a device (e.g., a UE, a wireless device or any other type of communication device) or components thereof and relates to an implementation in which at least a portion of the functionality is implemented as one or more virtual components (e.g., via one or more applications, components, functions, virtual machines or containers executing on one or more physical processing nodes in one or more networks).

In some embodiments, some or all of the functions described herein may be implemented as virtual components executed by one or more virtual machines implemented in one or more virtual environments 1300 hosted by one or more of hardware nodes 1330. Further, in embodiments in which the virtual node is not a radio access node or does not require radio connectivity (e.g., a core network node), then the network node may be entirely virtualized.

The functions may be implemented by one or more applications 1320 (which may alternatively be called software instances, virtual appliances, network functions, virtual nodes, virtual network functions, etc.) operative to implement some of the features, functions, and/or benefits of some of the embodiments disclosed herein. Applications 1320 are run in virtualization environment 1300 which provides hardware 1330 comprising processing circuitry 1360 and memory 1390. Memory 1390 contains instructions 1395 executable by processing circuitry 1360 whereby application 1320 is operative to provide one or more of the features, benefits, and/or functions disclosed herein. Virtualization environment 1300, comprises general-purpose or special-purpose network hardware devices 1330 comprising a set of one or more processors or processing circuitry 1360, which may be commercial off-the-shelf (COTS) processors, dedicated Application Specific Integrated Circuits (ASICs), or any other type of processing circuitry including digital or analog hardware components or special purpose processors. Each hardware device may comprise memory 1390-1 which may be non- persistent memory for temporarily storing instructions 1395 or software executed by processing circuitry 1360. Each hardware device may comprise one or more network interface controllers (NICs) 1370, also known as network interface cards, which include physical network interface 1380. Each hardware device may also include non-transitory, persistent, machine-readable storage media 1390-2 having stored therein software 1395 and/or instructions executable by processing circuitry 1360. Software 1395 may include any type of software including software for instantiating one or more virtualization layers 1350 (also referred to as hypervisors), software to execute virtual machines 1340 as well as software allowing it to execute functions, features and/or benefits described in relation with some embodiments described herein.

Virtual machines 1340, comprise virtual processing, virtual memory, virtual networking or interface and virtual storage, and may be run by a corresponding virtualization layer 1350 or hypervisor. Different embodiments of the instance of virtual appliance 1320 may be implemented on one or more of virtual machines 1340, and the implementations may be made in different ways.

During operation, processing circuitry 1360 executes software 1395 to instantiate the hypervisor or virtualization layer 1350, which may sometimes be referred to as a virtual machine monitor (VMM). Virtualization layer 1350 may present a virtual operating platform that appears like networking hardware to virtual machine 1340.

As shown in Figure 15, hardware 1330 may be a standalone network node with generic or specific components. Hardware 1330 may comprise antenna 13225 and may implement some functions via virtualization. Alternatively, hardware 1330 may be part of a larger cluster of hardware (e.g. such as in a data center or customer premise equipment (CPE)) where many hardware nodes work together and are managed via management and orchestration (MANO) 13100, which, among others, oversees lifecycle management of applications 1320.

Virtualization of the hardware is in some contexts referred to as network function virtualization (NFV). NFV may be used to consolidate many network equipment types onto industry standard high volume server hardware, physical switches, and physical storage, which can be located in data centers, and customer premise equipment.

In the context of NFV, virtual machine 1340 may be a software implementation of a physical machine that runs programs as if they were executing on a physical, nonvirtualized machine. Each of virtual machines 1340, and that part of hardware 1330 that executes that virtual machine, be it hardware dedicated to that virtual machine and/or hardware shared by that virtual machine with others of the virtual machines 1340, forms a separate virtual network elements (VNE).

Still in the context of NFV, Virtual Network Function (VNF) is responsible for handling specific network functions that run in one or more virtual machines 1340 on top of hardware networking infrastructure 1330 and corresponds to application 1320 in Figure 15.

In some embodiments, one or more radio units 13200 that each include one or more transmitters 13220 and one or more receivers 13210 may be coupled to one or more antennas 13225. Radio units 13200 may communicate directly with hardware nodes 1330 via one or more appropriate network interfaces and may be used in combination with the virtual components to provide a virtual node with radio capabilities, such as a radio access node or a base station.

In some embodiments, some signalling can be effected with the use of control system 13230 which may alternatively be used for communication between the hardware nodes 1330 and radio units 13200.

Figure 16 illustrates a telecommunication network connected via an intermediate network to a host computer in accordance with some embodiments. In particular, with reference to Figure 16, in accordance with an embodiment, a communication system includes telecommunication network 1410, such as a 3GPP-type cellular network, which comprises access network 1411 , such as a radio access network, and core network 1414. Access network 1411 comprises a plurality of base stations 1412a, 1412b, 1412c, such as NBs, eNBs, gNBs or other types of wireless access points, each defining a corresponding coverage area 1413a, 1413b, 1413c. Each base station 1412a, 1412b, 1412c is connectable to core network 1414 over a wired or wireless connection 1415. A first UE 1491 located in coverage area 1413c is configured to wirelessly connect to, or be paged by, the corresponding base station 1412c. A second UE 1492 in coverage area 1413a is wirelessly connectable to the corresponding base station 1412a. While a plurality of UEs 1491 , 1492 are illustrated in this example, the disclosed embodiments are equally applicable to a situation where a sole UE is in the coverage area or where a sole UE is connecting to the corresponding base station 1412.

Telecommunication network 1410 is itself connected to host computer 1430, which may be embodied in the hardware and/or software of a standalone server, a cloud-implemented server, a distributed server or as processing resources in a server farm. Host computer 1430 may be under the ownership or control of a service provider, or may be operated by the service provider or on behalf of the service provider. Connections 1421 and 1422 between telecommunication network 1410 and host computer 1430 may extend directly from core network 1414 to host computer 1430 or may go via an optional intermediate network 1420. Intermediate network 1420 may be one of, or a combination of more than one of, a public, private or hosted network; intermediate network 1420, if any, may be a backbone network or the Internet; in particular, intermediate network 1420 may comprise two or more sub-networks (not shown).

The communication system of Figure 16 as a whole enables connectivity between the connected UEs 1491 , 1492 and host computer 1430. The connectivity may be described as an over-the-top (OTT) connection 1450. Host computer 1430 and the connected UEs 1491 , 1492 are configured to communicate data and/or signaling via OTT connection 1450, using access network 1411 , core network 1414, any intermediate network 1420 and possible further infrastructure (not shown) as intermediaries. OTT connection 1450 may be transparent in the sense that the participating communication devices through which OTT connection 1450 passes are unaware of routing of uplink and downlink communications. For example, base station 1412 may not or need not be informed about the past routing of an incoming downlink communication with data originating from host computer 1430 to be forwarded (e.g., handed over) to a connected UE 1491. Similarly, base station 1412 need not be aware of the future routing of an outgoing uplink communication originating from the UE 1491 towards the host computer 1430.

Example implementations, in accordance with an embodiment, of the UE, base station and host computer discussed in the preceding paragraphs will now be described with reference to Figure 17. Figure 17 illustrates host computer communicating via a base station with a user equipment over a partially wireless connection in accordance with some embodiments In communication system 1500, host computer 1510 comprises hardware 1515 including communication interface 1516 configured to set up and maintain a wired or wireless connection with an interface of a different communication device of communication system 1500. Host computer 1510 further comprises processing circuitry 1518, which may have storage and/or processing capabilities. In particular, processing circuitry 1518 may comprise one or more programmable processors, application-specific integrated circuits, field programmable gate arrays or combinations of these (not shown) adapted to execute instructions. Host computer 1510 further comprises software 1511 , which is stored in or accessible by host computer 1510 and executable by processing circuitry 1518. Software 1511 includes host application 1512. Host application 1512 may be operable to provide a service to a remote user, such as UE 1530 connecting via OTT connection 1550 terminating at UE 1530 and host computer 1510. In providing the service to the remote user, host application 1512 may provide user data which is transmitted using OTT connection 1550.

Communication system 1500 further includes base station 1520 provided in a telecommunication system and comprising hardware 1525 enabling it to communicate with host computer 1510 and with UE 1530. Hardware 1525 may include communication interface 1526 for setting up and maintaining a wired or wireless connection with an interface of a different communication device of communication system 1500, as well as radio interface 1527 for setting up and maintaining at least wireless connection 1570 with UE 1530 located in a coverage area (not shown in Figure 17) served by base station 1520. Communication interface 1526 may be configured to facilitate connection 1560 to host computer 1510. Connection 1560 may be direct or it may pass through a core network (not shown in Figure 17) of the telecommunication system and/or through one or more intermediate networks outside the telecommunication system. In the embodiment shown, hardware 1525 of base station 1520 further includes processing circuitry 1528, which may comprise one or more programmable processors, applicationspecific integrated circuits, field programmable gate arrays or combinations of these (not shown) adapted to execute instructions. Base station 1520 further has software 1521 stored internally or accessible via an external connection.

Communication system 1500 further includes UE 1530 already referred to. Its hardware 1535 may include radio interface 1537 configured to set up and maintain wireless connection 1570 with a base station serving a coverage area in which UE 1530 is currently located. Hardware 1535 of UE 1530 further includes processing circuitry 1538, which may comprise one or more programmable processors, application-specific integrated circuits, field programmable gate arrays or combinations of these (not shown) adapted to execute instructions. UE 1530 further comprises software 1531 , which is stored in or accessible by UE 1530 and executable by processing circuitry 1538.

Software 1531 includes client application 1532. Client application 1532 may be operable to provide a service to a human or non-human user via UE 1530, with the support of host computer 1510. In host computer 1510, an executing host application 1512 may communicate with the executing client application 1532 via OTT connection 1550 terminating at UE 1530 and host computer 1510. In providing the service to the user, client application 1532 may receive request data from host application 1512 and provide user data in response to the request data. OTT connection 1550 may transfer both the request data and the user data. Client application 1532 may interact with the user to generate the user data that it provides.

It is noted that host computer 1510, base station 1520 and UE 1530 illustrated in Figure 17 may be similar or identical to host computer 1430, one of base stations 1412a, 1412b, 1412c and one of UEs 1491 , 1492 of Figure 16, respectively. This is to say, the inner workings of these entities may be as shown in Figure 17 and independently, the surrounding network topology may be that of Figure 16.

In Figure 17, OTT connection 1550 has been drawn abstractly to illustrate the communication between host computer 1510 and UE 1530 via base station 1520, without explicit reference to any intermediary devices and the precise routing of messages via these devices. Network infrastructure may determine the routing, which it may be configured to hide from UE 1530 or from the service provider operating host computer 1510, or both. While OTT connection 1550 is active, the network infrastructure may further take decisions by which it dynamically changes the routing (e.g., on the basis of load balancing consideration or reconfiguration of the network).

Wireless connection 1570 between UE 1530 and base station 1520 is in accordance with the teachings of the embodiments described throughout this disclosure. One or more of the various embodiments improve the performance of OTT services provided to UE 1530 using OTT connection 1550, in which wireless connection 1570 forms the last segment. More precisely, the teachings of these embodiments may improve the NAS security and latency and thereby provide benefits such as improved user experience and robustness of user communications.

A measurement procedure may be provided for the purpose of monitoring data rate, latency and other factors on which the one or more embodiments improve. There may further be an optional network functionality for reconfiguring OTT connection 1550 between host computer 1510 and UE 1530, in response to variations in the measurement results. The measurement procedure and/or the network functionality for reconfiguring OTT connection 1550 may be implemented in software 1511 and hardware 1515 of host computer 1510 or in software 1531 and hardware 1535 of UE 1530, or both. In embodiments, sensors (not shown) may be deployed in or in association with communication devices through which OTT connection 1550 passes; the sensors may participate in the measurement procedure by supplying values of the monitored quantities exemplified above, or supplying values of other physical quantities from which software 1511 , 1531 may compute or estimate the monitored quantities. The reconfiguring of OTT connection 1550 may include message format, retransmission settings, preferred routing etc.; the reconfiguring need not affect base station 1520, and it may be unknown or imperceptible to base station 1520. Such procedures and functionalities may be known and practiced in the art. In certain embodiments, measurements may involve proprietary UE signaling facilitating host computer 1510’s measurements of throughput, propagation times, latency and the like. The measurements may be implemented in that software 1511 and 1531 causes messages to be transmitted, in particular empty or ‘dummy’ messages, using OTT connection 1550 while it monitors propagation times, errors etc.

Figure 18 is a flowchart illustrating a method implemented in a communication system, in accordance with one embodiment. The communication system includes a host computer, a base station and a UE which may be those described with reference to Figures 16 and 17. For simplicity of the present disclosure, only drawing references to Figure 18 will be included in this section. In step 1610, the host computer provides user data. In substep 1611 (which may be optional) of step 1610, the host computer provides the user data by executing a host application. In step 1620, the host computer initiates a transmission carrying the user data to the UE. In step 1630 (which may be optional), the base station transmits to the UE the user data which was carried in the transmission that the host computer initiated, in accordance with the teachings of the embodiments described throughout this disclosure. In step 1640 (which may also be optional), the UE executes a client application associated with the host application executed by the host computer.

Figure 19 is a flowchart illustrating a method implemented in a communication system, in accordance with one embodiment. The communication system includes a host computer, a base station and a UE which may be those described with reference to Figures 16 and 17. For simplicity of the present disclosure, only drawing references to Figure 19 will be included in this section. In step 1710 of the method, the host computer provides user data. In an optional substep (not shown) the host computer provides the user data by executing a host application. In step 1720, the host computer initiates a transmission carrying the user data to the UE. The transmission may pass via the base station, in accordance with the teachings of the embodiments described throughout this disclosure. In step 1730 (which may be optional), the UE receives the user data carried in the transmission.

Figure 20 is a flowchart illustrating a method implemented in a communication system, in accordance with one embodiment. The communication system includes a host computer, a base station and a UE which may be those described with reference to Figures 16 and 17. For simplicity of the present disclosure, only drawing references to Figure 20 will be included in this section. In step 1810 (which may be optional), the UE receives input data provided by the host computer. Additionally or alternatively, in step 1820, the UE provides user data. In substep 1821 (which may be optional) of step 1820, the UE provides the user data by executing a client application. In substep 1811 (which may be optional) of step 1810, the UE executes a client application which provides the user data in reaction to the received input data provided by the host computer. In providing the user data, the executed client application may further consider user input received from the user. Regardless of the specific manner in which the user data was provided, the UE initiates, in substep 1830 (which may be optional), transmission of the user data to the host computer. In step 1840 of the method, the host computer receives the user data transmitted from the UE, in accordance with the teachings of the embodiments described throughout this disclosure.

Figure 21 is a flowchart illustrating a method implemented in a communication system, in accordance with one embodiment. The communication system includes a host computer, a base station and a UE which may be those described with reference to Figures 16 and 17. For simplicity of the present disclosure, only drawing references to Figure 21 will be included in this section. In step 1910 (which may be optional), in accordance with the teachings of the embodiments described throughout this disclosure, the base station receives user data from the UE. In step 1920 (which may be optional), the base station initiates transmission of the received user data to the host computer. In step 1930 (which may be optional), the host computer receives the user data carried in the transmission initiated by the base station.

Any appropriate steps, methods, features, functions, or benefits disclosed herein may be performed through one or more functional units or modules of one or more virtual apparatuses. Each virtual apparatus may comprise a number of these functional units. These functional units may be implemented via processing circuitry, which may include one or more microprocessor or microcontrollers, as well as other digital hardware, which may include digital signal processors (DSPs), special-purpose digital logic, and the like. The processing circuitry may be configured to execute program code stored in memory, which may include one or several types of memory such as read-only memory (ROM), random-access memory (RAM), cache memory, flash memory devices, optical storage devices, etc. Program code stored in memory includes program instructions for executing one or more telecommunications and/or data communications protocols as well as instructions for carrying out one or more of the techniques described herein. In some implementations, the processing circuitry may be used to cause the respective functional unit to perform corresponding functions according one or more embodiments of the present disclosure.

Generally, all terms used herein are to be interpreted according to their ordinary meaning in the relevant technical field, unless a different meaning is clearly given and/or is implied from the context in which it is used. All references to a/an/the element, apparatus, component, means, step, etc. are to be interpreted openly as referring to at least one instance of the element, apparatus, component, means, step, etc., unless explicitly stated otherwise. The steps of any methods disclosed herein do not have to be performed in the exact order disclosed, unless a step is explicitly described as following or preceding another step and/or where it is implicit that a step must follow or precede another step. Any feature of any of the embodiments disclosed herein may be applied to any other embodiment, wherever appropriate. Likewise, any advantage of any of the embodiments may apply to any other embodiments, and vice versa. Other objectives, features and advantages of the enclosed embodiments will be apparent from the description.

The term unit may have conventional meaning in the field of electronics, electrical devices and/or electronic devices and may include, for example, electrical and/or electronic circuitry, devices, modules, processors, memories, logic solid state and/or discrete devices, computer programs or instructions for carrying out respective tasks, procedures, computations, outputs, and/or displaying functions, and so on, as such as those that are described herein.

Some of the embodiments contemplated herein are described more fully with reference to the accompanying drawings. Other embodiments, however, are contained within the scope of the subject matter disclosed herein. The disclosed subject matter should not be construed as limited to only the embodiments set forth herein; rather, these embodiments are provided by way of example to convey the scope of the subject matter to those skilled in the art.