Title:
SOFT MUTE CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2001/052409
Kind Code:
A1
Abstract:
A soft mute circuit includes a programmable amplifier (41) controlled by a register (42). Data is stored in the register from an adder (43) that combines the current data in the register with a second number for increasing or decreasing the gain of the amplifier. A summation circuit includes a plurality of inputs coupled by gates to a summation node and the summation node is coupled to an input of the programmable amplifier. The gates are controlled by suitable logic for selecting input signals in any combination. A control loop maintains the gain of the amplifier at a predetermined level.
More Like This:
| JPS58164329 | FM MUTING CIRCUIT |
Inventors:
THOMASSON SAMUEL L
RUBACHA RAYMOND
RUBACHA RAYMOND
Application Number:
PCT/US2000/033932
Publication Date:
July 19, 2001
Filing Date:
December 15, 2000
Export Citation:
Assignee:
ACOUSTIC TECH INC (US)
International Classes:
H03G3/34; H04M1/60; (IPC1-7): H03G3/00; H04M1/00
Foreign References:
| US6154548A | 2000-11-28 | |||
| US5915030A | 1999-06-22 | |||
| US5187734A | 1993-02-16 | |||
| US4352958A | 1982-10-05 | |||
| US5606625A | 1997-02-25 |
Other References:
See also references of EP 1249070A4
Attorney, Agent or Firm:
Wille, Paul F. (AZ, US)
Download PDF:
Claims:
What is claimed as the invention is:
| 1. | A circuit for unobtrusively masking transient signals in an electronic device, said circuit comprising: an amplifier having a gain control input for receiving digital data and a signal input; a register having an output coupled to said gain control input; an adder coupled to said register for storing data in said register and having a pair of inputs, said adder having a control input for adding or subtracting data on the inputs of the adder; wherein said adder adjusts the gain of said amplifier in accordance with the signal on said control input. |
| 2. | The circuit as set forth in claim 1 and further including a control loop coupled to said adder for holding the gain of said amplifier at a predetermined value. |
| 3. | The circuit as set forth in claim 1 and further including a summation circuit coupled to said signal input, wherein said summation circuit includes several inputs. |
| 4. | The circuit as set forth in claim 3 wherein said summation circuit further includes logic for selecting one, all, or combinations of signals from the several inputs for summation. |
| 5. | A method for muting a signal, said method comprising the steps of: increasingly attenuating the signal at a first rate until a maximum level of attenuation is reached, holding the signal at the maximum level of attenuation for a controlled period ; and decreasingly attenuating the signal at a second rate. |
| 6. | The method as set forth in claim 5 wherein the first rate is substantially the same as the second rate. |
| 7. | The method as set forth in claim 5 wherein said step of increasingly attenuating the signal includes the steps of; applying the signal to an amplifier having an input for digital gain control ; and applying a series of decreasing numbers to the input. |
| 8. | The method as set forth in claim 5 wherein said step of decreasingly attenuating the signal includes the steps of; applying the signal to an amplifier having an input for digital gain control ; and applying a series of increasing numbers to the input. |
| 9. | The method as set forth in claim 8 wherein said step of applying a series of increasing numbers to the input is terminated when a predetermined number is reached in the series. |
| 10. | The method as set forth in claim 9 wherein the numbers are consecutive. |
| 11. | The method as set forth in claim 7 wherein the numbers are consecutive. |
| 12. | In a telephone having at least one internal switch, the improvement comprising a soft mute circuit for masking transients in the telephone. |
| 13. | The telephone as set forth in claim 12 wherein said soft mute circuit includes : an amplifier having a gain control input for receiving digital data and a signal input; a register having an output coupled to said gain control input; an adder coupled to said register for storing data in said register and having a pair of inputs, said adder having a control input for adding or subtracting data on the inputs of the adder; wherein said adder adjusts the gain of said amplifier in accordance with the signal on said control input. |
| 14. | The telephone as set forth in claim 13 wherein said telephone includes a summation node and said summation node is coupled to said signal input. |