Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
SOI STRUCTURE SINGLE EVENT TOLERANCE INVERTER, NAND ELEMENT, NOR ELEMENT, SEMICONDUCTOR MEMORY ELEMENT, AND DATA LATCH CIRCUIT
Document Type and Number:
WIPO Patent Application WO/2005/076479
Kind Code:
A1
Abstract:
An inverter having high single event tolerance, an NAND element, an NOR element, a memory element, and a data latch circuit. The single event tolerance inverter (3I) has a double structure (3P1, 3P2, 3N1, 3N2) where a p-channel MOS transistor and an n-channel MOS transistor constituting the inverter are respectively further connected in series with transistors of the same conductivity type, respectively, and a node (A) between two p-channel MOS transistors is connected with a node (B) between two n-channel MOS transistors through a connecting line. A single event tolerance memory element and a data latch circuit (4) comprise such a single event tolerance inverter (3I).

More Like This:
JPH07122990OUTPUT CONTROL CIRCUIT
JPH01258509LOGIC GATE
JP2023042331SEMICONDUCTOR DEVICE
Inventors:
KUBOYAMA SATOSHI (JP)
SHINDOU HIROYUKI (JP)
IIDE YOSHIYA (JP)
MAKIHARA AKIKO (JP)
Application Number:
PCT/JP2005/001675
Publication Date:
August 18, 2005
Filing Date:
February 04, 2005
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
JAPAN AEROSPACE EXPLORATION (JP)
HIGH RELIABILITY COMPONENTS CO (JP)
KUBOYAMA SATOSHI (JP)
SHINDOU HIROYUKI (JP)
IIDE YOSHIYA (JP)
MAKIHARA AKIKO (JP)
International Classes:
H03K19/003; H03K19/094; (IPC1-7): H03K19/094
Foreign References:
JP2004048170A2004-02-12
JPS61206998A1986-09-13
JP2000101420A2000-04-07
Other References:
None
See also references of EP 1720257A4
Attorney, Agent or Firm:
Kumakura, Yoshio (Shin-Tokyo Bldg. 3-1, Marunouchi 3-chom, Chiyoda-ku Tokyo 55, JP)
Download PDF:
View/Download PDF      PDF Help



 
Previous Patent: SYSTEM AND METHOD FOR IMPLEMENTING A KEYBOARD

Next Patent: A METHOD OF, AND RECEIVER FOR, CANCELLING INTERFERING SIGNALS