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Title:
SOLID ELECTROLYTIC CAPACITOR
Document Type and Number:
WIPO Patent Application WO/2024/009637
Kind Code:
A1
Abstract:
A solid electrolytic capacitor (10, 10A, 10B) comprises a valve metal substrate (11), a conductive paste layer (14), an insulating layer (15), and an external electrode layer (16). The valve metal substrate (11) has a dielectric layer (113) on both surfaces in the thickness direction thereof. The conductive paste layer (14) is positioned on both sides of the valve metal substrate (11) in the thickness direction thereof. The conductive paste layer (14) includes a conductive filler (141). The insulating layer (15) is layered on the conductive paste layer (14), on the opposite side from the valve metal substrate (11). The insulating layer (15) has a via hole (151). The external electrode layer (16) is layered on the insulating layer (15). The external electrode layer (16) is electrically connected to the conductive paste layer (14) via the via hole (151). Among the conductive filler (141) that is included in the conductive paste layer (14), the external electrode layer (16) is in direct contact with the conductive filler (141) that is located within the via hole (151), as viewed along the layering direction of the conductive paste layer (14), the insulating layer (15), and the external electrode layer (16).

Inventors:
YOSHINO SACHIKO (JP)
FURUKAWA TAKESHI (JP)
Application Number:
PCT/JP2023/019426
Publication Date:
January 11, 2024
Filing Date:
May 25, 2023
Export Citation:
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Assignee:
MURATA MANUFACTURING CO (JP)
International Classes:
H01G9/042; H01G9/048; H01G9/055; H01G9/15
Domestic Patent References:
WO2021039053A12021-03-04
WO2021172272A12021-09-02
Foreign References:
JP2006344936A2006-12-21
JP2008028137A2008-02-07
JPS62216311A1987-09-22
JP2015084435A2015-04-30
Attorney, Agent or Firm:
ASCEND IP LAW FIRM (JP)
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