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Title:
SOLID IMAGING DEVICE
Document Type and Number:
WIPO Patent Application WO/2010/113760
Kind Code:
A1
Abstract:
In a solid imaging device (1), an overflow gate (5) has a predetermined electrical resistance, and voltage-applying units (161 - 165) are electrically connected to the overflow gate (5) at connection points (171 - 175). As a result, by adjusting the voltages (V1 - V5) applied to the connection points (171 - 175) by the voltage-applying units (161 - 165), it is possible to raise the voltage arising at the front stage of the overflow gate (5) and lower the voltage arising at the back stage of the overflow gate (5). As a result, the barrier level (potential) at the front stage of the overflow gate (5) is lowered, and the barrier level at the back stage of the overflow gate (5) is raised, and so all of the load arising at the front stage of a photoelectric conversion unit (2) flows to an overflow drain (4), and only the load arising at the back stage of the photoelectric conversion unit (2) is time delay and integration (TDI) transmitted.

Inventors:
SUZUKI HISANORI (JP)
YONETA YASUHITO (JP)
MAETA KENTARO (JP)
MURAMATSU MASAHARU (JP)
Application Number:
PCT/JP2010/055239
Publication Date:
October 07, 2010
Filing Date:
March 25, 2010
Export Citation:
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Assignee:
HAMAMATSU PHOTONICS KK (JP)
SUZUKI HISANORI (JP)
YONETA YASUHITO (JP)
MAETA KENTARO (JP)
MURAMATSU MASAHARU (JP)
International Classes:
H01L27/148; H01L27/146; H04N5/335; H04N5/369; H04N5/372
Foreign References:
JP2002231914A2002-08-16
JP2003521837A2003-07-15
JP2002064197A2002-02-28
JP2003521837A2003-07-15
JPH11298805A1999-10-29
Other References:
See also references of EP 2416362A4
Attorney, Agent or Firm:
HASEGAWA Yoshiki et al. (JP)
Yoshiki Hasegawa (JP)
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