SOLID-STATE IMAGING DEVICE

WIPO Patent Application WO/2012/098777

A1

A vertical shift register (40a, 40b) has M logic circuits (LO1-LOM) which output a row selection control signal to each of M row selection wires (LV,1-LV,M), and a shift register circuit (43) arranged for each two row selection wires (LV). When a binning control signal (Vbin1 or Vbin2) and the output signal of a shift register circuit (43) are significant values, the M logic circuits (LO1-LOM) output row selection control signals (Vsel) such that a readout switch (SW1) is closed. By controlling the timing at which the binning control signals (Vbin1 and Vbin2) assume significant values, the vertical shift registers (40a, 40b) realize a normal operation mode for sequentially selecting the aforementioned two row selection wires (LV), and a binning operation mode for simultaneously selecting the aforementioned two row selection wires (LV). By this means, the vertical binning operations are achieved by means of a small vertical shift register.

KYUSHIMA RYUJI (JP)
FUJITA KAZUKI (JP)
MORI HARUMICHI (JP)

PCT/JP2011/078324

July 26, 2012

December 07, 2011

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HAMAMATSU PHOTONICS KK (JP)
KYUSHIMA RYUJI (JP)
FUJITA KAZUKI (JP)
MORI HARUMICHI (JP)

H04N5/347; H01L27/146; H04N5/376

JP2007050053A	2007-03-01
JP2007173950A	2007-07-05
JPH11308531A	1999-11-05
JP2000165747A	2000-06-16
JPH10275906A	1998-10-13
JP2005223890A	2005-08-18
JP2001189891A	2001-07-10

See also references of EP 2667589A4

HASEGAWA Yoshiki et al. (JP)
Yoshiki Hasegawa (JP)

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