Title:
SOLID-STATE IMAGING ELEMENT, AND IMAGING DEVICE
Document Type and Number:
WIPO Patent Application WO/2022/038885
Kind Code:
A1
Abstract:
The present invention increases the degree of freedom of design in a solid-state imaging element having a logic gate in a comparator. A comparison circuit compares an input potential that has been input with a predetermined reference potential and outputs one of a pair of output potentials as a comparison result. A level shift circuit, on the basis of the comparison result, outputs one of a pair of shift potentials that has a potential difference greater than the pair of output potentials, as an output signal. A logic gate determines whether the output signal is higher than a predetermined threshold value between the pair of shift potentials, and outputs a determination result. A counter counts a counter value over a period until the determination result is inverted.
Inventors:
NAKAGAWA DAISUKE (JP)
UENO YOSUKE (JP)
MATSUURA KOUJI (JP)
UENO YOSUKE (JP)
MATSUURA KOUJI (JP)
Application Number:
PCT/JP2021/023354
Publication Date:
February 24, 2022
Filing Date:
June 21, 2021
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H03M1/56; H03K5/08; H03K19/0185; H04N5/3745; H04N5/378
Domestic Patent References:
| WO2019017092A1 | 2019-01-24 | |||
| WO2018037902A1 | 2018-03-01 |
Foreign References:
| JP2019047383A | 2019-03-22 | |||
| JP2015152699A | 2015-08-24 | |||
| JP2012147339A | 2012-08-02 |
Attorney, Agent or Firm:
MARUSHIMA, Toshikazu (JP)
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