Title:
SOLID-STATE IMAGING ELEMENT, MANUFACTURING METHOD, AND ELECTRONIC DEVICE
Document Type and Number:
WIPO Patent Application WO/2018/088284
Kind Code:
A1
Abstract:
The present disclosure relates to a solid-state imaging element, a manufacturing method, and an electronic device which enable a wafer process and chip size package (CSP) process flow even without a cover glass. A CIS wafer and a logic wafer having a logic circuit or a memory circuit are stacked and adhered. Next, the CIS wafer and the logic wafer are electrically connected via a through-electrode. After formation of a lens on the light-receiving face of the CIS wafer, a wafer support system material is adhered upon the lens. An external electrode for external output is formed using a TSV formed from the back face-side of the logic wafer, which has been thinned. After formation of the external electrode, the wafer support system material is peeled away from the light-receiving face. The present disclosure can be applied to a laminated, back illumination-type solid-state imaging element, for example.
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Inventors:
WAKIYAMA SATORU (JP)
Application Number:
PCT/JP2017/039471
Publication Date:
May 17, 2018
Filing Date:
November 01, 2017
Export Citation:
Assignee:
SONY SEMICONDUCTOR SOLUTIONS CORP (JP)
International Classes:
H01L27/146; A61B1/04; H01L21/3205; H01L21/768; H01L23/522; H01L27/00; H04N5/369; H04N5/374
Foreign References:
| JP2015135938A | 2015-07-27 | |||
| JP2016171297A | 2016-09-23 | |||
| JPH08130227A | 1996-05-21 | |||
| JP2011193007A | 2011-09-29 | |||
| JP2015088666A | 2015-05-07 | |||
| JP2003101001A | 2003-04-04 | |||
| JP2011057964A | 2011-03-24 | |||
| JP2013084880A | 2013-05-09 |
Attorney, Agent or Firm:
NISHIKAWA Takashi et al. (JP)
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