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Patent Searching and Data


Title:
SOUND DATA PROCESSING DEVICE AND SOUND DATA PROCESSING METHOD
Document Type and Number:
WIPO Patent Application WO/2018/012576
Kind Code:
A1
Abstract:
[Solution] A PLL unit (207-x) generates a sampling clock (Sd-x) on the basis of a word clock (W-x) (x = 0-n), and a PLL unit (207-y) generates a sampling clock (Sd-y) on the basis of a word clock (W-y) (x = 0-n, y≠x). When having the clock to be outputted switched to the sampling clock (Sd-y) by a selector (220) while the sampling clock (Sd-x) is selected and being outputted, a control unit (205) adjusts the phase of the sampling clock (Sd-y) by a delay unit (206-y) to make the phse of the sampling clock (Sd-y) match the phase of the sampling clock (Sd-x) and then performs the switching. The sample of a sound signal received by each digital sound signal reception unit (200) is buffered in a FIFO (204) and outputted synchronously with the selected sampling clock.

Inventors:
AISO Masaru (10-1 Nakazawa-cho, Naka-ku, Hamamatsu-sh, Shizuoka 50, 〒4308650, JP)
Application Number:
JP2017/025503
Publication Date:
January 18, 2018
Filing Date:
July 13, 2017
Export Citation:
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Assignee:
YAMAHA CORPORATION (10-1, Nakazawa-cho Naka-ku, Hamamatsu-sh, Shizuoka 50, 〒4308650, JP)
International Classes:
H04L7/00; H03L7/00; H03L7/08; H04R3/00
Foreign References:
JPH099399A1997-01-10
JP2013183403A2013-09-12
JPH11289590A1999-10-19
Attorney, Agent or Firm:
OSAWA Yutaka et al. (4th Floor, Stork Minami Otsuka 33-1, Minami Otsuka 2-chome, Toshima-k, Tokyo 05, 〒1700005, JP)
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