Title:
SOUND VOLUME CONTROL CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT, AND SOUND SOURCE DEVICE
Document Type and Number:
WIPO Patent Application WO/2005/099304
Kind Code:
A1
Abstract:
In a sound volume control circuit (100) shown in Fig. 2, an attenuation coefficient setting register (28) holds an attenuation coefficient “b”. When a stop instruction STOP becomes active, an output signal “a” from a first multiplexer (14), i.e., a processing object signal “in” is multiplied by the attenuation coefficient “b” by a multiplier (16), and the output signal “c” is outputted via a second multiplexer (18), a first flip-flop (20), and a third multiplexer (22). A multiplication master counter (38) holds the number of times the processing object signal “in” acquired by one sampling is multiplied by “b”. The multiplication master counter (38) counts up by using a timer (36). A multiplication temporary counter (32) loads the output signal from the multiplication master counter (38) at the assert of an acquisition timing signal “L”. The process from the first multiplexer (14) to the first flip-flop (20) is repeated by the number of times of the multiplication temporary counter (32).
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Inventors:
KURIHARA NAOKI (JP)
Application Number:
PCT/JP2005/006620
Publication Date:
October 20, 2005
Filing Date:
April 04, 2005
Export Citation:
Assignee:
ROHM CO LTD (JP)
KURIHARA NAOKI (JP)
KURIHARA NAOKI (JP)
International Classes:
H03G3/00; H03G3/02; H04R3/00; H04R29/00; (IPC1-7): H04R3/00; H03G3/00; H03G3/02
Foreign References:
| JPH0742101U | 1995-07-21 | |||
| JP2000315925A | 2000-11-14 | |||
| JP2001257548A | 2001-09-21 | |||
| JP2002353757A | 2002-12-06 | |||
| JP2000013157A | 2000-01-14 | |||
| JP2000102088A | 2000-04-07 | |||
| JP2003173612A | 2003-06-20 |
Attorney, Agent or Firm:
Morishita, Sakaki (Ebisu-Nishi Shibuya-ku Tokyo, 21, JP)
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