TECHNICAL FIELD

The present disclosure relates to magnetic random access memory (MRAM).

BACKGROUND

Magnetic random access memory (MRAM) stores data using magnetic storage elements rather than electric charges or current flows. A magnetic tunnel junction (MTJ) may be used as a magnetic storage element. An MTJ is formed sandwiching a thin, insulating, layer between two ferromagnetic plates, each of which holds a separate magnetization. One of the plates in an MTJ (the fixed magnetic layer) is a permanent magnet that is set to a particular polarity, the magnetic field produced by the second plate in the MTJ (the free magnetic layer) may be altered such that the polarity of the second plate matches the polarity of the first plate (parallel) or such that the polarity of the second plate opposes the polarity of the first plate (anti-parallel). The magnetic tunnel effect through the tunnel layer separating the free and fixed magnetic layers causes the resistance of the MTJ to change due to the relative orientation of the magnetic fields produced by the free and fixed magnetic plates.

A typical MTJ device used in such an STT-MRAM bitcell includes an MTJ coupled in series with a control device such as a transistor (i.e. , a 1T- 1MTJ bitcell). The series MTJ and transistor is connected between a bit line and a source line. The read path and write paths for such an STT-MRAM device are identical necessitating design compromises. Such compromises are evidenced by the resistance of the MTJ - generally, a higher resistance during read operations and a lower resistance during write operations (reducing the current draw required to change the state of the bitcell) is preferable. However, since both read and write operations share a common path, such differences in resistance between read and write operations are discouraged.

The 1T- 1MTJ bitcell therefore has several notable disadvantages. First, a large write current (e.g., in excess of 100 microamps, μΑ) and a higher voltage (e.g., in excess of 0.7 volts, V) may be required to change the alignment of the free magnet layer in the MTJ and thus successfully complete a WRITE operation to the MTJ device. Many MTJs are unable to handle such large currents on a routine basis and therefore WRITE currents may be limited to a lower value that provides a satisfactory service lifetime for the MTJ. However, the need to limit current during WRITE operations may lead to unacceptably high error rates and/or low speed switching (e.g., greater than 20 nanoseconds) in MTJ-based MRAM. Further, even at low current values, the presence of a tunneling path within the MTJ may lead to reliability issues in MTJs.

BRIEF DESCRIPTION OF THE DRAWINGS

Features and advantages of various embodiments of the claimed subject matter will become apparent as the following Detailed Description proceeds, and upon reference to the Drawings, wherein like numerals designate like parts, and in which:

FIG. 1 is a sectional view of an illustrative two transistor (2T) STT-MRAM bitcell employing the spin Hall effect (SHE) electrode to change the resistance of a magnetic tunnel junction (MTJ), in accordance with at least one embodiment of the present disclosure;

FIG. 2 is a perspective view of an illustrative magnetic tunnel junction (MTJ) device having a free magnetic layer disposed proximate a spin Hall effect (SHE) electrode, in accordance with at least one embodiment of the present disclosure.

FIG. 3 is a plan view of an illustrative magnetic tunnel junction (MTJ) device having a free magnetic layer disposed proximate a spin Hall effect (SHE) electrode, in accordance with at least one embodiment of the present disclosure;

FIG. 4 is a magnified cross section of an illustrative spin Hall effect (SHE) electrode in which a passage of current has created various up-spin patterns and down-spin patterns within the SHE electrode, in accordance with at least one embodiments of the present disclosure;

FIG. 5 is a schematic of an illustrative two transistor (2T), spin Hall effect (SHE), Spin Transfer Torque (STT) magnetic random access memory (MRAM) depicted during a READ operation, in accordance with at least one embodiment of the present disclosure;

FIG. 6 is a schematic of an illustrative two transistor (2T), spin transfer torque (STT), spin Hall effect (SHE), magnetic random access memory (MRAM) (2T- 1MTJ-STT-SHE-

MRAM) depicted during a WRITE operation, in accordance with at least one embodiment of the present disclosure;

FIG. 7 is a plan view of an illustrative 4x4 array that includes sixteen 2T-1MTJ-STT- SHE-MRAM bitcells, in accordance with at least one embodiment of the present disclosure; FIG. 8 is a layout of an illustrative 2x2 2T-1MTJ-STT-SHE-MRAM bitcell array, in accordance with at least one embodiment of the present disclosure;

FIG. 9 is a plot depicting write energy against write delay for an illustrative 2T- 1MTJ-STT-SHE-MRAM bitcell and for various traditional MTJ devices, in accordance with at least one embodiment of the present disclosure;

FIG. 10 is a plot depicting reliable write times against magnetic thermal barrier for an illustrative 2T-1MTJ-STT-SHE-MRAM bitcell and a traditional MTJ, in accordance with at least one embodiment of the present disclosure;

FIG. 11 is a high-level flow diagram of a method of providing for an illustrative 2T- 1MTJ-STT-SHE-MRAM bitcell, in accordance with at least one embodiment of the present disclosure;

FIG. 12 is a high-level flow diagram of a method of storing digital data in an illustrative 2T-1MTJ-STT-SHE-MRAM bitcell, in accordance with at least one embodiment of the present disclosure; and

FIG. 13 is a block diagram of an illustrative processor-based device in which at least a portion of the non-transitory data storage is provided using illustrative 2T-1MTJ-STT-SHE- MRAM bitcells, in accordance with at least one embodiment of the present disclosure.

Although the following Detailed Description will proceed with reference being made to illustrative embodiments, many alternatives, modifications and variations thereof will be apparent to those skilled in the art.

DETAILED DESCRIPTION

Spin transfer torque (STT) uses spin-aligned electrons in a spin Hall effect material proximate the free magnetic layer of the MTJ to alter the magnetic orientation or alignment of the free magnetic layer. For example, a current passed through a metallic layer with a large spin-orbit coupling may generate a spin current through the MTJ (via the giant spin Hall effect) sufficient to induce realignment or reorientation of the free magnetic field in the MTJ device. The spin Hall effect is a phenomenon that occurs in metals having large atomic weight in which electrons with different spins are deflected in different sideways directions. Consequently, an applied charge current generates a flow of spin angular momentum transverse to the charge flow. In addition, the direction of current flow through the spin Hall effect material alters the spin direction of the electrons in the material - thus, a spin Hall effect electrode positioned proximate an MTJ may change or alter the resistance of the MTJ based simply on the direction of current flow through the spin Hall effect material.

A two transistor (2T), one magnetic tunnel junction (1MTJ), spin torque transfer (STT), spin Hall effect (SHE), magnetic random access memory (MRAM) bitcell (hereinafter referred to by the shorthand designation: 2T-1MTJ-STT-SHE MRAM) includes an MTJ device having a free magnetic layer disposed proximate a SHE electrode. The polarity or magnetic orientation of the MTJ free magnetic layer may be changed by passing a directional current through the SHE electrode. When a current passes through the SHE electrode in a first direction, the MTJ free magnetic layer may align in a parallel configuration with the MTJ fixed magnetic layer, providing a relatively high resistance path through the MTJ.

When the current passes through the SHE electrode in a second direction that is opposite the first, the MTJ free magnetic layer may align in an anti-parallel configuration with the MTJ fixed magnetic layer, providing a relatively low resistance path through the MTJ. The resistance presented by the MTJ permits the non-volatile storage of binary data (e.g. , a low resistance may indicate a first logical state, and a high resistance may indicate a second logical state). Beneficially, the orientation of the MTJ free magnetic layer may be changed by passing a current through the SHE electrode rather than through the MTJ itself due to the synergistic coupling of the SHE electrode to the MTJ free magnetic layer. Such may allow for the use of significantly higher write currents which advantageously provide more rapid cycling or clocking of the MRAM bitcell while at the same time beneficially reducing error rates within the MRAM bitcell.

The 2T- 1MTJ-STT-SHE MRAM bitcell leverages the Giant Spin Hall effect (GSHE) to provide a high spin injection efficiency and provide a relatively robust and reliable, yet compact, random access memory. The GSHE enables the use of low programming voltages or, alternatively, enables the use of higher currents for identical voltages since the WRITE current does not pass through the MTJ and instead passes through the SHE electrode. The 2T-1MTJ-STT-SHE MRAM bitcell features low error rates at a relatively fast (e.g. , < 10 nanosecond) write speed. The read and write paths within the 2T- 1MTJ-STT-SHE MRAM bitcell are beneficially decoupled, thereby improving read latencies. The 2T- 1MTJ-STT- SHE MRAM bitcell further features a low resistance WRITE operation, this allows for greater WRITE currents and enables the MTJ to rapidly change states. Further the separate read and write paths within the 2T- 1 MTJ-STT-SHE MRAM bitcell permit the use of lower read currents (e.g. , 10 μΑ read current versus 100 μΑ write current) that improves the performance and reliability of the MTJ device. A two transistor, one magnetic tunnel junction (2T-1MTJ) spin torque transfer (STT) Spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) apparatus is provided. The 2T-1MTJ-STT-SHE MRAM bitcell may include a Spin Hall effect (SHE) electrode. The 2T-1MTJ-STT-SHE MRAM bitcell may also include a first transistor conductively coupled between the SHE electrode and a data line, the first transistor controlled by a write enable line and a second transistor conductively coupled between the SHE electrode and a source line, the second transistor controlled by a word line. The 2T-1MTJ-STT-SHE MRAM bitcell may also include a magnetic tunnel junction (MTJ) device having a free magnetic layer conductively coupled to the SHE electrode at a location between the conductive coupling to the first transistor and the conductive coupling to the second transistor.

A two transistor, one magnetic tunnel junction (2T-1MTJ) spin torque transfer (STT) spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) method is provided. The method may include forming a first transistor having a first diffusion region, a second diffusion region, and a gate region and forming a second transistor having a first diffusion region, a second diffusion region, and a gate region. The method may further include forming a source line in a first metal layer and conductively coupling the first diffusion region of the second transistor to the source line. The method may also include e forming a SHE electrode and conductively coupling the second diffusion region of the first transistor to the SHE electrode and the second diffusion region of the second transistor to the SHE electrode. The method may additionally include forming an MTJ device that includes a free magnetic layer and a fixed magnetic layer and conductively coupling a free magnetic layer of the MTJ device to the SHE electrode. The method may further include forming a data line and a bit line in a second metal layer, with at least one intervening metal layer between the first metal layer and the second metal layer, conductively coupling a fixed magnetic layer of the MTJ device to the bit line; and conductively coupling the first diffusion region of the first transistor to the data line.

A two transistor, one magnetic tunnel junction (2T-1MTJ) spin torque transfer (STT) spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) method is also provided. The method may include selectively writing a binary value to a MRAM cell that includes a MTJ coupled to a SHE electrode by causing a write current to flow through the SHE electrode in either of: a first direction that places a resistance value of an MTJ device magnetically coupled to the SHE electrode in a first state; or a second direction that places the resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state that differs from the first state. A two transistor, one magnetic tunnel junction (2T- 1MTJ) spin torque transfer (STT), spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) system is provided. The 2T-1MTJ-STT-SHE MRAM bitcell system may include a means for selectively writing a binary value to a MRAM cell that includes a MTJ coupled to a SHE electrode by causing a write current to flow through the SHE electrode in either of a first direction that places a resistance value of an MTJ device magnetically coupled to the SHE electrode in a first state; or a second direction that places the resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state that differs from the first state.

As used herein, the term "transistor" and the plural term "transistors" may refer to any type of metal oxide semiconductor (MOS) transistor having a drain terminal, a source terminal, a gate terminal, and a bulk terminal. The term "transistor" and the plural term "transistors" may also refer to any other type of current or future developed transistor or transistor- like (i.e. , switching) devices including, without limitation, FinFET transistors, Tri- Gate transistors, Gate-All-Around cylindrical transistors, carbon nanotube devices, and spintronic devices. As described herein, the terms "source" and "drain" refer to transistor terminals and may therefore be freely substituted for each other. The term "transistor" and the plural term "transistors" may also refer to bipolar junction transistors (BJT or BJTs).

FIG. 1 is a block diagram of an illustrative two transistor, one magnetic tunnel junction, spin torque transfer, spin Hall effect, magnetic random access memory bitcell 100 (hereinafter "2T- 1MTJ-STT-SHE MRAM bitcell 100" or "bitcell 100"), in accordance with at least one embodiment of the present disclosure. The 2T-1MTJ-STT-SHE MRAM bitcell 100 includes a magnetic tunnel junction (MTJ) device 1 10, a spin Hall effect (SHE) electrode 130, a first transistor 150, and a second transistor 160.

A number of conductive structures 154, such as one or more pillar vias, may conductively couple a first diffusion region 152 (e.g. , a source region) of the first transistor 150 to a data line 144. A number of conductive structures 158, such as one or more pillar vias, may conductively couple a second diffusion region 156 (e.g. , a drain region) of the first transistor 150 to a first end 132 of the SHE electrode 130. A write-enable line 148 may couple to the gate 155 of the first transistor 150 and may control the operation and/or state of the first transistor 150.

A number of conductive structures 164, such as one or more pillar vias, may conductively couple a first diffusion region 162 (e.g. , a source region) of the second transistor 160 to a source line 140. A number of conductive structures 158, such as a number of pillar vias, may conductively couple a second diffusion region 166 (e.g. , a drain region) of the second transistor 160 to a second end 134 of the SHE electrode 130. A word line 146 may couple to the gate 165 of the second transistor 160 and may control the operation and/or state of the second transistor 160.

A free magnet layer 112 of the MTJ device 110 may be conductively coupled to the SHE electrode 130 and a fixed magnet layer 114 of the MTJ device 110 may be conductively coupled to a bit line 142. In some implementations a synthetic anti-ferromagnetic (SAF) layer that includes a ruthenium layer 122 and a cobalt/iron layer 124 may be disposed proximate the fixed magnetic layer 114 of the MTJ device 110, between the fixed magnetic layer 114 and the bit line 142. In some implementations an anti-ferromagnetic device (AFM) device 126 may be disposed between the cobalt/iron layer 124 and the fixed magnet layer 114 of the MTJ device 110. In embodiments, the 2T-1MTJ-STT-SHE MRAM bitcell 100 provides a five terminal device (i.e., separate connection for each of: the source line 140, the bit line 142, the data line 144, the word line 146, and the write enable line 148).

In embodiments, a spin polarized write current may pass between the source line 140 and the data line 144 to perform a WRITE operation. The potential differential between the source line 140 and the data line 144 determines whether the write current flows from the source line 140 to the data line 144 or vice versa. The direction of flow through the SHE electrode 130 may determine the magnetic orientation of the free magnetic layer 112 in the MTJ device 110, and consequently the resistance (and logical state) of the MTJ device 110. In embodiments, a write current passing through the SHE electrode 130 in a first direction causes the free magnetic layer 112 in the MTJ device 110 to assume a magnetic orientation that is generally parallel to the magnetic orientation of the fixed magnetic layer 114.

Arranging the magnetic fields of the free magnetic layer 112 and the fixed magnetic layer 114 in a generally parallel configuration places the MTJ device 110 in a relatively high tunnel current flow/low resistance state. Conversely, a write current passing through the SHE electrode 130 in a second direction may cause the free magnetic layer 112 in the MTJ devicel lO to assume a magnetic orientation that is generally anti-parallel to the magnetic orientation of the fixed magnetic layer 114. Arranging the magnetic fields of the free magnetic layer 112 and the fixed magnetic layer 114 in a generally anti-parallel configuration places the MTJ device 110 in a relatively low tunnel current flow/high resistance state.

In embodiments, the potential difference between the source line 140 and the data line 144 may be used to assign and store a binary value in the MTJ device 110 by controlling the direction of write current flow through and consequently write current spin polarization in the SHE electrode 130. In embodiments, the write current can be about 30 μΑ or greater; about 50 μΑ or greater; about 70 μΑ or greater; about 100 μΑ or greater; about 150 μΑ or greater; or about 200 μΑ or greater. Beneficially, the relatively high write current does not pass through the MTJ device 110 and instead only passes through the SHE electrode 130. Further, the ability to use a relatively high write current may improve write speeds and data reliability while not compromising the long term reliability and performance of the MTJ device 110 used in the 2T- 1 MTJ-STT-SHE MRAM bitcell 100.

In embodiments, a read current is passed from the bit line 142 through the MTJ device 110 to perform a READ operation. The resistance of the MTJ device 110 determines the logical value returned by the READ operation. The read current can be about 30 μΑ or less; about 25 μΑ or less; about 20 μΑ or less; about 15 μΑ or less; about 10 μΑ or less; or about 5 μΑ or less. Beneficially, the MTJ device 110 sees only the relatively low read current and not the substantially higher write current. Such a reduction in read current through the MTJ device 110 beneficially improves the long term reliability and performance of the 2T-1 MTJ- STT-SHE MRAM bitcell 100.

The MTJ device 110 includes a free magnetic layer 112 disposed proximate or in contact with the SHE electrode 130. In embodiments, the MTJ device 110 may include any current or future developed MTJ device 110 including, but not limited to, perpendicular magnetized MTJ devices 110 and in-plane magnetized MTJ devices 110. In embodiments, the free magnetic layer 112 and/or the fixed magnetic layer 114 of the MTJ device 110 may include any current or future developed magnetic material. In at least some embodiments, the free magnetic layer 112 and/or the fixed magnetic layer 114 of the MTJ device 110 may include one or more materials having a relatively high spin polarization, such as cobalt (Co), iron (Fe), or a cobalt/iron/boron alloy (Co _a FefcB _c - where a, b, and c are integer values). In one implementation, each of the free magnetic layer 112 and the fixed magnetic layer 114 may include a CoFeB layer that is about 80% CoFe and about 20% B ((CoFe)soB2o) sputtered as an amorphous film layer.

One or more tunnel barrier layers 116 separate the free magnetic layer 112 from the fixed magnetic layer 114. In embodiments, the one or more tunnel barrier layers 116 may include one or more metal oxides. Examples of such metal oxides include, but are not limited to, titanium oxides (TiO^), magnesium oxides (MgO^), aluminum oxides (AIO^), or combinations thereof. The tunnel barrier layer 116 may be several Angstroms to several nanometers in thickness.

The MTJ device 110 may include or otherwise incorporate either or both a synthetic anti-ferromagnetic (SAF) layer and/or an anti-ferromagnetic (AFM) layer. The synthetic anti-ferromagnetic (SAF) layer may include a ruthenium (Ru) layer 122 deposited proximate the fixed magnetic layer 114 and a cobalt/iron (CoFe) layer 124 deposited proximate the ruthenium layer 122. In embodiments, the SAF/AFM layer(s) may couple to the fixed magnetic layer 114 through exchange bias and may cause at least a portion of the atoms in the fixed magnetic layer 114 to align with at least a portion of the atoms in the SAF/AFM layer(s), thereby "pinning" or fixing the magnetic field orientation of the fixed magnetic layer 114. Although described as including a ruthenium layer 122 and a cobalt/iron layer 124, the SAF layer may include additional or alternative materials capable of pinning or fixing the orientation of the fixed magnetic layer 114 magnetic field. The MTJ device 1 10 may conductively couple to the bit line 142 through the SAF/AFM layer(s). A conductive structure 120, such as a via, may conductively couple the MTJ device 110 to the bit line 142.

The SHE electrode 130 may include a giant spin Hall effect (GSHE) metal that includes, but is not limited to, β-tantalum (β-Ta), β-tungsten (β-W), platinum (Pt), gold (Au), silver (Ag), copper (Cu), or combinations or alloys thereof. In some implementations, the SHE electrode 130 may include one or more dopants, such as iridium (Ir), bismuth (Bi), any of the elements from groups 3d, 4d, 5d, 4f, or 5, or combinations or alloys thereof.

The MTJ device 110 may be positioned on the SHE electrode 130 having a dimension and thickness that is optimized to achieve high spin injection. The SHE electrode 130 within each bitcell 100 may be disposed above the source line 140 which, in some embodiments, may be patterned into the zero metal (M0) layer. One or more conductive structures 158, such as one or more pillar vias, may conductively couple a first end 132 of the SHE electrode 130 within each bitcell 100 to the second diffusion region 156 of first transistor 150. One or more conductive structures 168, such as one or more pillar vias, may conductively couple a second end 134 of the SHE electrode 130 within each bitcell 100 to the second diffusion region 166 of the second transistor 160.

The first transistor 150 may include any combination or number of devices or systems capable of controlling the write current flow between the first end 132 of the SHE electrode 130 and the data line 144. In at least some implementations, one or more conductive structures 154, such as one or more pillar vias, one or more SHE metals 157, and one or more thru-MTJ vias 159, may communicably couple the first diffusion region 152 (e.g. , the source) of the first transistor 150 to the data line 144. In embodiments, one or more conductive structures 158, such as one or more pillar vias, may conductively couple the second diffusion region 152 (e.g. , the drain) of the first transistor 150 to the first end 132 of the SHE electrode 130. In embodiments, the write-enable line 148 may conductively couple to the gate 155 of the first transistor 150 to control the operation of the first transistor 150. In at least some embodiments, the through-MTJ via 159 may be located between adjacent MTJ devices 1 10 and may be processed after the formation of the respective MTJ devices 1 10.

The second transistor 160 may include any number or combination of devices and/or systems capable of controlling the write current flow between the second end 134 of the SHE electrode 130 and the source line 140. In embodiments, one or more conductive structures 164, such as one or more pillar vias, may conductively couple the first diffusion region 162 (e.g., the source) of the second transistor 160 to the source line 140. In embodiments, one or more conductive structures, such as one or more pillar vias 168, may conductively couple the second diffusion region 164 (e.g. , the drain) of the second transistor 160 to the second end 134 of the SHE electrode 130. In embodiments, the word line 146 may conductively couple to the gate 165 of the second transistor 160 to control the operation of the second transistor 160.

FIG. 2 depicts an illustrative MTJ device 1 10 that includes a SAF layer and an AFM layer disposed on an illustrative SHE electrode 130, in accordance with at least one embodiment of the present disclosure. The free magnet layer 122 of the MTJ device 110 may be disposed proximate a central portion 202 of the SHE electrode 130 that includes or is fabricated using one or more giant Spin Hall effect (GSHE) materials. Non-limiting examples of such GSHE materials include β-tantalum (β-Ta), β-tungsten (β-W), platinum (Pt), gold (Au), silver (Ag), copper (Cu), or combinations or alloys thereof. In some implementations, the central portion 202 of the SHE electrode 130 may include one or more dopants, such as iridium (Ir), bismuth (Bi), any of the elements from groups 3d, 4d, 5d, 4f, or 5, or combinations or alloys thereof. In some implementations the first end 132 of the SHE electrode 130 may include or be fabricated using one or more electrically conductive materials such as copper, copper alloys, aluminum, aluminum alloys, gold, gold alloys, silver, silver alloys, platinum, platinum alloys, or combinations thereof. In some implementations the second end 134 of the SHE electrode 130 may include or be fabricated using one or more electrically conductive materials such as copper, copper alloys, aluminum, aluminum alloys, gold, gold alloys, silver, silver alloys, platinum, platinum alloys, or combinations thereof. Fabricating either or both the first end 132 and the second end 134 of the SHE electrode 130 from a highly electrically conductive material beneficially reduces the resistance of the SHE electrode 130 and potentially permits the use of a lower write current level.

A spin polarized write current 220 may pass along the SHE electrode 130 in either the first direction or the second direction as represented by the double-headed arrow shown in FIG. 2. Beneficially, the write current 220 does not pass through the MTJ device 1 10, thereby permitting the use of a relatively high write current (e.g. , 100 μΑ) to provide a rapid and reliable write to the MTJ device 1 10 in the MRAM bitcell. In contrast to the write current 220, a read current 230 may pass from a bit line 142 and through the MTJ device 1 10 as represented by the single-headed arrow shown in FIG. 2. Since the write current and the read current travel through the 2T-1MTJ-STT-SHE MRAM bitcell 100 along different paths, both the read current and the write current may advantageously selected for their respective function. A relatively high write current beneficially provides for a rapid and reliable write to the 2T- 1MTJ-STT-SHE MRAM bitcell 100, a relatively low read current (e.g. , 10 μΑ) beneficially improves the long term reliability of the 2T- 1MTJ-STT-SHE MRAM bitcell 100.

FIG. 3 depicts an illustrative MTJ device 1 10 geometry, in accordance with at least one embodiment of the present disclosure. The MTJ device 110 may have any shape, size, or configuration. In at least one embodiment, the MTJ device 1 10 may have a generally elliptical footprint. In such embodiments, the MTJ device 110 may have an elliptical geometry characterized by a major axis, or length, 302 and a minor axis, or width, 304. In at least some implementations, the MTJ device 110 may be oriented along the width of the SHE electrode 130 for appropriate spin injection. Binary data may be written to the MTJ device 110 by applying a spin polarized write current 220 in either the first direction or the second direction along the SHE electrode 130. The direction of the magnetic writing may be determined by the direction of the applied write current. For example, positive currents (along the +y axis) produce a spin injection current with transport direction (along the +z axis) and spins directed in the +x direction.

FIG. 4 depicts a cross section of the GSHE material showing the direction of the up spin currents 402, the direction of the down spin currents 404 and charge currents 410, 412 resulting from the Spin Hall effect in GSHE materials in the absence of an externally applied magnetic field. The injected spin current produces spin torque to align the magnet in a +x or -x direction. The transverse spin current I _s = 7 _† — I _x with spin direction σ for a charge current (l _c ) in the write electrode may be expressed as: / = PsHE (w, t, _sf , e _SHE ) (a x / _c ) (1)

Where P _SHE = / _† — 7j,)/( / _† + /j,) is the spin Hall injection efficiency (the ratio of magnitude of transverse spin current to lateral charge current), w is the width of the magnet, t is the thickness of the GSHE metal electrode, _S f is the spin flip length in the GSE metal, Q _S HE is the spin Hall angle for the GSHE- metal to FM1 interface. The injected spin angular momentum responsible for spin torque is given by:

FIG. 5 depicts an illustrative READ operation on an example 2T-1MTJ-STT-SHE MRAM bitcell 100, in accordance with at least one embodiment of the present disclosure. During the READ operation, a read current 502 passes from the bit line 142, through the MTJ 110, and through the SHE electrode 130 to the source line 140. In embodiments, bit line 142 and the source line 140 may be conductively coupled to a sense amplifier (not shown in FIG. 5). The resistance of the MTJ device 110 determines whether a "LOW" logical value or a "HIGH" logical value is read. In embodiments, the read current 502 may be about 30 μΑ or less; about 25 μΑ or less; about 20 μΑ or less; about 15 μΑ or less; about 10 μΑ or less; or about 5 μΑ or less.

FIG. 6 depicts an illustrative WRITE operation 600 on an example 2T-1MTJ-STT- SHE MRAM bitcell 100, in accordance with at least one embodiment of the present disclosure. The direction of the write current flow through the SHE electrode 130 may determine the spin polarization of the write current and consequently the orientation of the magnetic field of the free magnetic layer 112. To write a "LOW" logical value or state to the MTJ device 110, the write current may pass through the SHE electrode 130 in a first direction. To write a "HIGH" logical value or state to the MTJ device 110, the write current may pass through the SHE electrode 130 in a second direction that is opposite the first direction. In embodiments, the relative potential difference between the source line 140 and the data line 144 determines the direction of write current flow through the SHE electrode 130.

In the left 2T- 1 MTJ-STT-SHE MRAM bitcell 100A (bitcell "A") depicted in FIG. 6, the source line 140 is maintained at a higher potential than the data line 144. In such an instance, a write current 610 flows through the first transistor 150, through the SHE electrode 130 in a first direction 612, and through the second transistor 160. In the right 2T-1MTJ- STT-SHE MRAM bitcell 100B shown in FIG. 6, the data line 144 is maintained at a higher potential than the source line 140. In such an instance, a write current 620 flows through the second transistor 160, through the SHE electrode 130 in a second direction 622, and through the first transistor 150. FIG. 7 depicts an illustrative array 700 that includes sixteen (16) 2T-1MTJ-STT-SHE MRAM bitcells 100A-100P, in accordance with at least one embodiment of the present disclosure. Although depicted as an illustrative 4 x 4 array of 2T-1MTJ-STT-SHE MRAM bitcells 100, such arrays 700 may have any number or configuration of 2T-1MTJ-STT-SHE MRAM bitcells 100. Each 2T-1MTJ-STT-SHE MRAM bitcell 100A-100P includes a SHE electrode 130 and an MTJ device 110 that, when combined, provide a three terminal device. In addition, each 2T-1MTJ-STT-SHE MRAM bitcell includes two transistors 150, 160 per bitcell 100. The MTJ device 110 may be connected to the bit line 142 that may be included in the second metal (M2) layer. The SHE electrode 130 may be formed using one or more spin Hall materials that include, but are not limited to: beta- tantalum, beta- tungsten, platinum, or bismuth selenide. The MTJ device 110 may be sized, shaped, and positioned on the SHE electrode 130 with the correct orientation to allow spin injection.

Write operation of each bitcell 100 may occur by enabling the word line 146 and write enable line 148 to enable both the first transistor 150 and the second transistor 160 in a single bitcell 100. A spin Hall write current 612, 622 flows through the respective bitcell 100 as depicted and described in FIG. 6, above. Adjacent bitcells 100 in the respective row may remain undisturbed due to the presence of the select-transistors and separation of spin-hall metal in each bit cell. The potential of the data line 144 coupled to the respective bitcell 100 is adjusted by selectively coupling the respective data line 144 to either a ground (low potential) or V _cc (high potential) depending on the input data (i.e. , whether a logical "1" or a logical "0" is being written to the bitcell). The direction of the write current 612, 622 through the bitcell 100 allows appropriate spin injection into the MTJ device 110. To perform a READ operation, the second transistor 160 may be enabled and the first transistor 150 may be maintained in an OFF logical state such that a read current 502 is able to pass from the source line 140 through the second transistor 160 and through the MTJ device 110 to detect the resistance of the MTJ device 110.

The array 700 includes a respective source line 140A-140D, a respective bit line 142A-142D, and a respective data linel44A-144D for each "row" of 2T-1MTJ-STT-SHE MRAM bitcells 100. The array 700 also includes a respective word line 146A-146D for each "column" of 2T-1MTJ-STT-SHE MRAM bitcells 100. The write enable lines 148A-148B are shared between two adjacent columns of 2T-1MTJ-STT-SHE MRAM bitcells 100.

FIG. 8 depicts a top view layout of an illustrative layout 800 of four 2T-1MTJ-STT- SHE MRAM bitcells 100, in accordance with at least one embodiment of the present invention. In such implementations, the interconnectivity demonstrates two 2T-1MTJ-STT- SHE MRAM bitcells 100A and 100B share a common data line 144 A, a common bit line 142A, and a common source line 140 A. The interconnect! vity further demonstrates 2T- 1MTJ-STT-SHE MRAM bitcells 100A and lOOC share a common word line 146A and a common write enable line 148 A. Similarly, the interconnect! vity demonstrates two 2T- IMTJ-STT-SHE MRAM bitcells lOOC and 100D share a common data line 144B, a common bit line 142B, and a common source line 140B. The interconnect! vity further demonstrates 2T- IMTJ-STT-SHE MRAM bitcells 100B and 100D share a common word line 146B and a common write enable line 148 A. In such implementations, each 2T- IMTJ-STT-SHE MRAM bitcell 100 includes a dedicated SHE electrode 130 that is not shared by any other 2T- IMTJ-STT-SHE MRAM bitcell 100. Each cell has a dimension of three (3) times the gate spacing or six (6) times the half gate spacing (6F) by two (2) times the pitch of the source line 140 or four (4) times the half source line pitch.

FIG. 9 depicts a plot 900 of write energy delay conditions for a 2T- IMTJ-STT-SHE MRAM bitcell 100 compared to traditional MTJ devices, in accordance with at least one embodiment of the present invention. Table 1 (below) compares various parameters such as resistivity, spin Hall angle, damping, write resistance and polarization for tantalum spin Hall effect electrode, a tungsten spin Hall effect electrode, and a conventional MTJ-MRAM:

Table 1.) Write Resistance and Spin Polarization of 2T- IMTJ-STT-SHE MRAM bitcell

From Table 1 , the write resistance of the SHE electrode based MRAM bitcells is significantly reduced (by a factor of about 10) over the write resistance of the MTJ-MRAM bitcell. Such reductions in resistance permit reduced write currents, reduced heat generation, and allows a more compact die layout.

In plot 900 the x-axis is energy (fj/write) and the y-axis is delay in nanoseconds. Plot

900 shows five (5) waveforms that compare the energy-delay trajectory of GSHE and MTJ (GSHE-MTJ) devices for in-plane magnet switching as applied write voltage is varied. The energy-delay trajectory (for in-plane switching) may be written as:

Where R _write is the write resistance of the device (RGSHE or RMTJ-P, RMTJ-AP), P is the spin current polarization (PGSHE of PMTJ), μ ₀ is the permeability of a vacuum, e is the electron charge. From equation (4), the energy at a given delay is directly proportional to the square of the Gilbert damping. In addition:

To = (5)

varies as the spin polarization varies for various GSHE metal electrodes. The combined effect of spin Hall polarization, damping, and resistivity of the spin Hall electrodes as captured in equation (4) and plotted in plot 900.

All of the cases considered in plot 900 assume a 30 nm x 60 nm magnet with 40 kT thermal energy barrier and 3.5 nm GSHE electrode thickness. The energy-density trajectories of the devices are obtained assuming a voltage sweep from 0 to 0.7V in accordance with the voltage restrictions of a complementary metal oxide semiconductor (CMOS) device. The energy-delay trajectories of the GSHE-MTJ devices broadly define two operating regions. Region 1 where the energy delay product is approximately constant, which may be expressed as:

^ ^M sVe .„

Region 2, where the energy is proportional to the delay, may be expressed as:

M _s Ve Region 1 and region 2 are separated by an energy minima where minimum switching energy is obtained for the spin torque devices that occurs at:

The energy-delay trajectory of the STT-MTJ devices 908, 910 is limited with a minimum delay of 1 nanosecond for in-plane devices at 0.7 volts maximum applied voltage, the switching energy for P-AP and AP-P are in the range of 1 pico- Joule per write (pj/write). In contrast, the energy delay trajectory of GSHE-MTJ (in-plane anisotropy) devices 902, 904, and 906 can enable switching times as low as 20 pico-seconds ( ?-W with 0.7 V, 20 femto- Joules per bit, fj/bit) or switching energy as small as 2 fj ( ?-W with 0.1 V, 1.5 nano-second switching time). Plot 900 demonstrates that a 2T-1MTJ-STT-SHE device with the same energy exhibits lower write operation delay. FIG. 10 depicts a plot 1000 of reliable write times for 2T- 1MTJ-STT-SHE MRAM bitcell 100 and conventional MTJs, in accordance with at least one embodiment of the present disclosure. Plot 1000 demonstrates write time of the 2T-SHE devices using bit-cell circuit simulations coupled with Landau-Lifshitz-Gilbert nanomagnet dynamics. The Spin Hall MTJ 1002 demonstrates a marked write time improvement compared to in-plane MTJs 1006 and perpendicular magnetic anisotropic MTJs 1004.

FIG. 1 1 delicts a high-level illustrative method of forming a 2T- 1MTJ-STT-SHE MRAM bitcell 100, in accordance with at least one embodiment of the present disclosure. The method 1100 commences at 1102.

At 1104, the first transistor 150 may be formed in, on, or about a substrate. The first transistor 150 may include a first diffusion region 152 (e.g. , a source region), a gate region 155 and a second diffusion region 156 (e.g., a drain region). The first transistor 150 may include a metal oxide semiconductor (MOS) transistor, a Tri-Gate transistor, a finned field- effect transistor (FinFET), a gate all-around cylindrical transistor, or any other current or future developed devices, systems, or combination of systems and devices that provide transistor-like functionality (e.g., carbon nanotubes, spintronic devices, and similar).

At 1106, the second transistor 160 may be formed in, on, or about the substrate. The second transistor 160 may include a first diffusion region 162 (e.g. , a source region), a gate region 165 and a second diffusion region 166 (e.g., a drain region). The second transistor 160 may include a metal oxide semiconductor (MOS) transistor, a Tri-Gate transistor, a finned field-effect transistor (FinFET), a gate all-around cylindrical transistor, or any other current or future developed devices, systems, or combination of systems and devices that provide transistor-like functionality (e.g., carbon nanotubes, spintronic devices, and similar).

At 1108, the source line 140 may be deposited or otherwise patterned in a first metal layer. In at least some implementations, the first metal layer may include a zero metal (M0) layer, for example as depicted in FIG. 1. The first metal layer may be deposited or patterned using any combination of current or future developed deposition, removal, and/or patterning technologies. In various embodiments, example deposition technologies may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD). In various embodiments, example removal technologies may include, but are not limited to wet etch removal, dry etch removal, and chemical-mechanical

planarization. In various embodiments, example patterning technologies may include, but are not limited to, photolithography. At 11 10, a first diffusion region 162 (e.g. , the source region) of the second transistor 160 may be conductively coupled to the source line 140. In some implementations, the first diffusion region 162 may be conductively coupled to the source line 140 using one or more conductive structures 164, for example one or more pillar vias.

At 11 12, the SHE electrode 130 may be deposited. Although depicted as a solid rectangular member in the figures, the shape and/or three-dimensional geometry of the SHE electrode 130 is not limited to a solid rectangular member. Other SHE electrode shapes, sizes, and configurations may be substituted. In some implementations, the SHE electrode 130 may include a heterogeneous member. In such implementations, a central portion of the SHE electrode 130 disposed proximate the MTJ device 110 may be formed from any current or future developed GSHE metal such as beta-tantalum, beta-tungsten, platinum, bismuth selenide, or similar. In such implementations, at least a portion of one or more peripheral regions of the SHE electrode 130 may be fabricated from a material providing low electrical resistance or having a high electrical conductivity, for example, copper, silver, or gold. In some implementations, the SHE electrode 130 may be beneficially doped with one or more materials that include, but are not limited to: iridium, bismuth, any of the elements of the 3d, 4d, 5d, 4f, and 5f periodic groups, gold, silver, platinum, copper, or similar.

At 11 14, the second diffusion region 156 (e.g. , the drain) of the first transistor 150 may be conductively coupled to the SHE electrode 130. In some implementations, the second diffusion region 156 may be conductively coupled to the SHE electrode 130 using one or more conductive structures 158, for example one or more pillar vias.

At 11 16, the second diffusion region 166 (e. g. , the drain) of the second transistor 160 may be conductively coupled to the SHE electrode 130. In some implementations, the second diffusion region 166 may be conductively coupled to the SHE electrode 130 using one or more conductive structures 168, for example one or more pillar vias.

At 11 18, the MTJ device 1 10 may be formed on at least a portion of the SHE electrode 130. In at least some implementations, the MTJ device 110 may be formed at an intermediate point of the SHE electrode 130, at a location between the conductive coupling to the second diffusion region 156 of the first transistor 150 and the second diffusion region 166 of the second transistor 160. In some implementations, the MTJ device stack may include a free magnetic layer 112, a tunneling oxide layer 116, and a fixed magnetic layer 114. In some implementations, the MTJ device stack may additionally include a synthetic anti- ferromagnetic (SAF) layer that assists in fixing the magnetic field of the fixed magnetic layer 114. At times, the SAF layer may include a ruthenium layer 122 and a cobalt/iron layer 126. In some implementations, the MTJ device stack may additionally include an anti- ferromagnetic layer (AFM).

At 1120, the free magnetic layer 112 of the MTJ device 110 is coupled to the SHE electrode 130.

At 1122, the bit line 142 and the data line 144 may be deposited or otherwise patterned in a second metal layer. In at least some implementations, the second metal layer may include a physical second metal (M2) layer, for example as depicted in FIG. 1. The second metal layer may be deposited or patterned using any combination of current or future developed deposition, removal, and/or patterning technologies. In various embodiments, example deposition technologies may include, but are not limited to, physical vapor deposition (PVD), chemical vapor deposition (CVD), electrochemical deposition (ECD), molecular beam epitaxy (MBE), and atomic layer deposition (ALD). In various

embodiments, example removal technologies may include, but are not limited to wet etch removal, dry etch removal, and chemical-mechanical planarization. In various embodiments, example patterning technologies may include, but are not limited to, photolithography.

At 1124, the MTJ device 110 may be conductively coupled to the bit line 142. In some implementations, one or more conductive structures, for example one or more vias 120, may conductively couple the AFM layer 126 of the MTJ device 110 to the bit line 142.

At 1126, the first diffusion region 152 of the first transistor 150 may be conductively coupled to the data line 144. In some instances, one or more conductive structures, such as one or more pillar vias 154, SHE metal layers 157, and one or more thru-MTJ vias 159, may be used to conductively couple the first diffusion region 152 of the first transistor 150 to the data line 144. The method 1100 concludes at 1128.

FIG. 12 depicts a high-level flow diagram 1200 of an illustrative WRITE operation to a 2T-1MTJ-STT-SHE MRAM bitcell 100, in accordance with at least one embodiment of the present disclosure. The method 1200 commences at 1202.

At 1204, a write current 612, 622 is passed through the SHE electrode 130 to place the magnetic field produced by the free magnetic layer 112 in the MTJ device 110 to one of two defined orientations. The direction of write current flow through the SHE electrode 130 may determine the spin polarization of the write current 612, 622 and consequently the magnetic orientation of the free magnetic layer 112 in the bitcell 100. In embodiments, a first magnetic orientation may correspond to a "LOW" logical state or value and a second magnetic orientation may correspond to a "HIGH" logical state or value. Since the write current does not pass through the MTJ device 110 itself, higher write currents are possible than in conventional MTJ designs where the write current passes through the MTJ device 110. The use of higher currents beneficially permits faster write cycles while maintaining acceptable error levels.

In some instances, to write a first logical value to the MTJ device 1 10, the potential of the data line 144 may be maintained at a higher level than the potential of the source line 140. In such instances, the write current 612 may flow from the data line 144, through the first transistor 150, through the SHE electrode 130 in a first direction (e.g. , from the first end 132 to the second end 134 of the SHE electrode 130), and through the second transistor 160 to the source line 140.

In some instances, to write a second logical value to the MTJ device 110, the potential of the source line 140 may be maintained at a higher level than the potential of the data line 144. In such instances, the write current 622 may flow from the source line 140, through the second transistor 160, through the SHE electrode 130 in a second direction (e.g. , from the second end 134 to the first end 132 of the SHE electrode 130), and through the first transistor 150 to the data line 144. The method concludes at 1206.

Figure 13 depicts a processor-based environment 1300 in which at least a portion of the non-volatile storage may include 2T-1MTJ-STT-SHE MRAM bitcells 100, in accordance with at least one embodiment of the present disclosure. The processor-based environment 1300 includes one or more processor-based devices 1302 communicably coupled to one or more nontransitory processor-readable storage devices 1304. The associated nontransitory processor-readable storage medium 1304 is communicatively coupled to the one or more processor-based devices 1302 via one or more communications channels, for example one or more parallel cables, serial cables, or wireless channels capable of high speed

communications, for instance via BLUETOOTH ^® , universal serial bus (USB), FIREWIRE ^® , or similar.

The one or more processor-based devices 1302 may be communicably coupled to one or more external devices using one or more wireless or wired network interfaces 1360.

Example wireless network interfaces 1360 may include, but are not limited to,

BLUETOOTH ^® , near field communications (NFC), ZigBee, IEEE 802.11 (Wi-Fi), 3G, 4G, LTE, CDMA, GSM, and similar. Example wired network interfaces 1360 may include, but are not limited to, IEEE 802.3 (Ethernet), and similar. Unless described otherwise, the construction and operation of the various blocks shown in Figure 13 are of conventional design. As a result, such blocks need not be described in further detail herein, as they will be understood by those skilled in the relevant art. The processor-based system 1300 may include one or more circuits capable of executing processor-readable instructions to provide any number of specialized processing circuits 1312, a system memory 1314 and a system communications link 1316 that bidirectionally communicably couples various system components including the system memory 1314 to the processing circuits 1312. The processing circuits 1312 may include, but are not limited to, any circuit capable of executing one or more processor-readable instruction sets, such as one or more single or multi-core central processing units (CPUs), digital signal processors (DSPs), application-specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), systems on a chip (SOCs), etc. The communications link 1316 may employ any known bus structures or architectures, including a memory bus with memory controller, a peripheral bus, and/or a local bus. The system memory 1314 includes read-only memory ("ROM") 1318 and random access memory ("RAM") 1320. In at least some

implementations, at least a portion of the RAM 1320 may include STT-SHE-MRAM bitcells. In at least some implementations, at least a portion of the RAM 1320 may include 2T-1MTJ- STT-SHE MRAM bitcells 100. A basic input/output system ("BIOS") 1322, which can form part of the ROM 1318, contains basic routines that may cause the transfer information between elements within the processor-based device 1302, such as during start-up.

The processor-based device 1302 may include one or more disk drives 1324, one or more optical storage devices 1328, one or more magnetic storage devices 1330, and/or one or more atomic or quantum storage devices 1332. The one or more optical storage devices 1328 may include, but are not limited to one or more CD-ROM drives. The one or more magnetic storage devices may include, but are not limited to a magnetic floppy disk or diskette. The one or more disk drives 1324, the one or more optical storage devices 1328, the one or more magnetic storage devices 1328, and the one or more atomic/quantum storage devices 1332 may include integral or discrete interfaces or controllers (not shown).

Processor-readable instruction sets may be stored or otherwise retained in whole or in part in the system memory 1314. Such processor-readable instruction sets may include, but are not limited to an operating system 1336, one or more application programs 1338, other programs or modules 1340 and program data 1342. While shown in FIG. 13 as being stored in the system memory 1314, the operating system 1336, application programs 1338, other programs/modules 1340, program data 1342 and browser 1344 can be stored on the one or more disk drives 1324, the one or more optical storage devices 1328, the one or more magnetic storage devices 1330, and/or one or more atomic or quantum storage devices 1332. A system user may enter commands and information into the processor-based device 1302 using one or more physical input devices 1370. Example physical input devices 1370 include, but are not limited to, one or more keyboards 1372, one or more touchscreen I/O devices 1374, one or more audio input devices 1376 (e.g. , microphone) and/or one or more pointing devices 1378. These and other physical input devices 1350 may be communicably coupled the processor-based device 1302 through one or more wired or wireless interfaces such as a wired universal serial bus (USB) connection and/or a wireless BLUETOOTH ^® connection.

The system user may receive output from the processor-based device 1302 via one or more physical output devices 1380. Example physical output devices 1380 may include, but are not limited to, one or more visual or video output devices 1382, one or more tactile or haptic output devices 1384, and/or one or more audio output devices 1386. The one or more video or visual output devices 1382, the one or more tactile output devices 1384, and the one or more audio output devices 1386 may be communicably coupled to the communications link 1316 via one or more interfaces or adapters.

The following examples pertain to embodiments that employ some or all of the described 2T- 1MTJ-STT-SHE MRAM bitcell apparatuses, systems, and methods described herein. The enclosed examples should not be considered exhaustive, nor should the enclosed examples be construed to exclude other combinations of the systems, methods, and apparatuses disclosed herein and which are not specifically enumerated herein.

According to example 1 , there is provided a two transistor, one magnetic tunnel junction (2T-1MTJ), Spin Torque Transfer (STT) Spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) apparatus. The apparatus may include a Spin Hall effect (SHE) electrode. The apparatus may further include a first transistor conductively coupled between the SHE electrode and a data line, the first transistor controlled by a write enable line and a second transistor conductively coupled between the SHE electrode and a source line, the second transistor controlled by a word line. The apparatus may additionally include a magnetic tunnel junction (MTJ) device having a free magnetic layer conductively coupled to the SHE electrode at a location between the conductive coupling to the first transistor and the conductive coupling to the second transistor.

Example 2 may include elements of example 1 where the MTJ device may be conductively coupled to a bitline.

Example 3 may include elements of example 1 where the SHE electrode may include an SHE material having a first end and an opposed second end, the first transistor may conductively couple to the first end of the SHE electrode, and the second transistor may conductively couple to the second end of the SHE electrode.

Example 4 may include elements of example 1 where the source line may be formed on a zero metal (MO) layer.

Example 5 may include elements of example 4 where the data line and the bit line may be formed on a second metal (M2) layer.

Example 6 may include elements of example 1 where the first transistor, the SHE electrode, and the second transistor may form a reversible circuit during write operations.

Example 7 may include elements of example 6 where current flow in a first direction through the SHE electrode may place the free magnet in the MTJ device in a parallel alignment with a fixed magnet in the MTJ device, placing the MTJ device in a low-resistance state.

Example 8 may include elements of example 6 where current flow in a second direction, opposite the first direction, through the SHE electrode may place the free magnet in the MTJ device in an anti-parallel alignment with a fixed magnet in the MTJ device, placing the MTJ device in a high-resistance state.

Example 9 may include elements of any of examples 1 through 8 where the SHE electrode may include a patterned SHE electrode.

Example 10 may include elements of example 9 where the SHE electrode may be fabricated, at least in part, using β-Tantalum (β-Ta), β-Tungsten (β-W), Platinum (Pt), or Copper (Cu).

Example 11 may include elements of example 10 where the SHE electrode may be fabricated using one or more dopants selected from the group consisting of: iridium, bismuth, any group 3d element, any group 4d element, any group 5d element, any group 4f element, any group 5f element, silver, gold, copper, and platinum.

Example 12 may include elements of any of examples 1 through 8 where the SHE electrode may include an elliptical patterned MTJ device having a width and a length.

Example 13 may include elements of any of examples 2 through 8 where the MTJ device may be physically disposed between a zero metal (M0) layer that includes the source line and a second metal (M2) layer that includes the bit line and the data line and where the source line, the bit line, and the data line may be parallel to each other.

According to example 14, there is provided a two transistor, one magnetic tunnel junction (2T-1MTJ), Spin Torque Transfer (STT), Spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) method. The method may include forming a first transistor having a first diffusion region, a second diffusion region, and a gate region and forming a second transistor having a first diffusion region, a second diffusion region, and a gate region. The method may further include forming a source line in a first metal layer and conductively coupling the first diffusion region of the second transistor to the source line. The method may also include forming a SHE electrode and conductively coupling the second diffusion region of the first transistor to the SHE electrode and the second diffusion region of the second transistor to the SHE electrode. The method may additionally include forming an MTJ device that includes a free magnetic layer and a fixed magnetic layer and conductively coupling a free magnetic layer of the MTJ device to the SHE electrode. The method may further include forming a data line and a bit line in a second metal layer, with at least one intervening metal layer between the first metal layer and the second metal layer, conductively coupling a fixed magnetic layer of the MTJ device to the bit line, and conductively coupling the first diffusion region of the first transistor to the data line.

Example 15 may include elements of example 14, and may additionally include conductively coupling the gate region of the first transistor to a write enable line and conductively coupling the gate region of the second transistor to a word line.

Example 16 may include elements of example 15 where conductively coupling a free magnetic layer of the MTJ device to the SHE electrode may include conductively coupling the free magnetic layer of the MTJ device to the SHE electrode at a physical location between the write enable line and the word line.

Example 17 may include elements of example 15 where MRAM method of claim 15 wherein conductively coupling a conductively coupling the free magnetic layer of the MTJ device to the SHE electrode may include conductively coupling the free magnetic layer of the MTJ device to the SHE electrode at a point between the second diffusion region of the first transistor and the second diffusion region of the second transistor.

Example 18 may include elements of example 14, and may additionally include conductively coupling a free magnetic layer of at least one additional MTJ device to the SHE electrode.

Example 19 may include elements of example 14 where forming an MTJ device may include forming a generally elliptical MTJ device in the at least one intervening metal layer, the elliptical MTJ device having a length and a width.

Example 20 may include elements of any of examples 14 through 18 where forming a source line in a first metal layer may include forming the source line in a zero metal (M0) layer. Example 21 may include elements of example 20 where forming a data line and a bit line in a second metal layer may include forming the data line and the bit line in a second metal (M2) layer.

Example 22 may include elements of example 21 where forming an MTJ device in the at least one intervening metal layer may include forming the MTJ device in a first metal (Ml) layer.

Example 23 may include elements of example 14 where forming an SHE electrode may include forming an SHE electrode that includes β-Tantalum (β-Ta), β-Tungsten (β-W), Platinum (Pt), or Copper (Cu).

Example 24 may include elements of example 23 where forming an SHE electrode that includes β-Tantalum (β-Ta), β-Tungsten (β-W), Platinum (Pt), or Copper (Cu) may include forming an SHE electrode that includes β-Tantalum (β-Ta), β-Tungsten (β-W), Platinum (Pt), or Copper (Cu) that includes one or more dopants selected from the group consisting of: iridium, bismuth, any group 3d element, any group 4d element, any group 5d element, any group 4f element, any group 5f element, silver, gold, copper, and platinum.

According to example 25, there is provided a two transistor, one magnetic tunnel junction (2T-1MTJ), Spin Torque Transfer (STT), Spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) method. The method may include selectively writing a binary value to a MRAM cell that includes a MTJ coupled to a SHE electrode by causing a write current to flow through the SHE electrode in either of: a first direction that places a resistance value of an MTJ device magnetically coupled to the SHE electrode in a first state; or a second direction that places the resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state that differs from the first state.

Example 26 may include elements of example 25 where selectively causing a write current to flow through a Spin Hall effect electrode in a first direction may include selectively causing the write current to flow from a data line through a first transistor (write select), through the SHE electrode in the first direction, and through a second transistor (select) to a source line at a lower potential than the data line.

Example 27 may include elements of example 26 where selectively causing a write current to flow through a Spin Hall effect electrode in a second direction may include selectively causing the write current to flow from the source line through the second transistor (select), through the SHE electrode in the second direction, and through a first transistor (write select) to a data line at a lower potential than the source line. Example 28 may include elements of any of examples 26 or 27 where the write current flows through the SHE electrode for about 10 nanoseconds (ns).

Example 29 may include elements of example 25, and may additionally include selectively reading a binary value from the MRAM cell that includes the MTJ coupled to the SHE electrode by causing a read current to flow through the MTJ.

Example 30 may include elements of example 29 where selectively reading a binary value from the MRAM cell by causing a read current to flow through the MTJ may include selectively causing the read current to flow from a bit line through the MTJ, through the SHE electrode, and through the second transistor (select) to a source line.

Example 31 may include elements of any of examples 28 or 29 where selectively reading a binary value from the MRAM cell by causing a read current to flow through MTJ may include floating the potential of the data line.

Example 32 may include elements of example 30 where the write current may include a current value at least five times greater than a current value of the read current.

Example 33 may include elements of example 30 where the write current may be approximately 100 μΑ and the read current may be approximately 10 μΑ.

According to example 34, there is provided a two transistor, one magnetic tunnel junction (2T-1MTJ) Spin Hall effect (SHE) Magnetic Random Access Memory (MRAM) system. The system may include a means for selectively writing a binary value to a MRAM cell that includes a MTJ coupled to a SHE electrode by causing a write current to flow through the SHE electrode in either of: a first direction that places a resistance value of an MTJ device magnetically coupled to the SHE electrode in a first state or a second direction that places the resistance value of the MTJ device magnetically coupled to the SHE electrode in a second state that differs from the first state.

Example 35 may include elements of example 34 where the means for selectively causing a write current to flow through a Spin Hall effect electrode in a first direction may include a means for selectively causing the write current to flow from a data line through a first transistor, through the SHE electrode in the first direction, and through a second transistor to a source line held at a lower potential than the data line.

Example 36 may include elements of example 35 where the means for selectively causing a write current to flow through a Spin Hall effect electrode in a second direction may include a means for selectively causing the write current to flow from the source line through the second transistor (select), through the SHE electrode in the second direction, and through a first transistor (write select) to a data line held at a lower potential than the source line. Example 37 may include elements of example 34, and may additionally include a means for selectively reading a binary value from the MRAM cell that includes the MTJ coupled to the SHE electrode by causing a read current to flow through the MTJ.

Example 38 may include elements of example 37 where the means for selectively reading a binary value from the MRAM cell by causing a read current to flow through the MTJ may include a means for selectively causing the read current to flow from a bit line through the MTJ, through the SHE electrode, and through the second transistor (select) to a source line.

Example 39 may include elements of any of examples 28 or 29 where the means for selectively reading a binary value from the MRAM cell by causing a read current to flow through MTJ may include a means for floating the potential of the data line.

The terms and expressions which have been employed herein are used as terms of description and not of limitation, and there is no intention, in the use of such terms and expressions, of excluding any equivalents of the features shown and described (or portions thereof), and it is recognized that various modifications are possible within the scope of the claims. Accordingly, the claims are intended to cover all such equivalents.