SPIN ORBIT COUPLING BASED MEMORY WITH RESISTIVITY MODULATION

BACKGROUND

[0001] Embedded memory with state retention can enable energy and computational efficiency. However, leading spintronic memory options, for example, spin transfer torque based magnetic random access memory (STT-MRAM), suffer from the problem of high voltage and high write current during the programming (e.g., writing) of a bit-cell. For instance, large write current (e.g., greater than 100 mA) and voltage (e.g., greater than 0.7 V) are required to write a tunnel junction based magnetic tunnel junction (MTJ). Limited write current also leads to high write error rates or slow switching times (e.g., exceeding 20 ns) in MTJ based MRAM. The presence of a large current flowing through a tunnel barrier leads to reliability issues in magnetic tunnel junctions.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] The embodiments of the disclosure will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure, which, however, should not be taken to limit the disclosure to the specific embodiments, but are for explanation and understanding only.

[0003] Fig. 1A illustrates a magnetization response to an applied magnetic field for a ferromagnet.

[0004] Fig. IB illustrates a magnetization response to an applied magnetic field for a paramagnet.

[0005] Figs. 2A-C illustrate a three-dimensional (3D) view, corresponding top view, and resistivity model, respectively, of a device having an out-of-plane magnetic tunnel junction (MTJ) stack coupled to a spin orbit coupling (SOC) interconnect.

[0006] Fig. 3 illustrates a cross-section of the SOC interconnect with electrons having their spins polarized in-plane and deflected up and down resulting from a flow of charge current.

[0007] Fig. 4A illustrates a plot showing write energy-delay conditions for one transistor and one MTJ with spin Hall effect (SHE) material compared to traditional MTJs.

[0008] Fig. 4B illustrates a plot comparing reliable write times for spin Hall MRAM and spin torque MRAM.

[0009] Figs. 5A-C illustrate a 3D view, corresponding cross-section view, and a resistance model, respectively, of a device having a magnetic junction with magnets having perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0010] Figs. 6A-B illustrate a 3D view and corresponding cross-section view, respectively, of a device having a magnetic junction with magnets having in-plane magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0011] Figs. 7A-B illustrate a 3D view and corresponding cross-section view, respectively, of a device having a magnetic junction with magnets having perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0012] Fig. 8A illustrates a cross-section of a device having a magnetic junction with magnets having perpendicular magnetizations, where a free magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC

interconnect, according to some embodiments of the disclosure.

[0013] Fig. 8B illustrates a cross-section of a device having a magnetic junction with magnets having perpendicular magnetizations, where a free magnet structure and a fixed magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0014] Fig. 8C illustrates a cross-section of a device having a magnetic junction with magnets having perpendicular magnetizations, where a fixed magnet structure and one of the free magnets of a free magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0015] Fig. 8D illustrates a cross-section of a device having a magnetic junction with magnets having perpendicular magnetizations, where a fixed magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0016] Fig. 8E illustrates a cross-section of a device having a magnetic junction with magnets having perpendicular magnetizations, where a fixed magnet structure and one of the free magnets of a free magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0017] Fig. 9A illustrates a plot showing spin polarization capturing switching of a free magnet structure coupled to a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0018] Fig. 9B illustrates a magnetization plot associated with Fig. 9A, according to some embodiments of the disclosure.

[0019] Fig. 9C illustrates a plot showing spin polarization capturing switching of the free magnet structure coupled to a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0020] Fig. 9D illustrates a magnetization plot associated with Fig. 9C, according to some embodiments of the disclosure.

[0021] Fig. 10 illustrates a cross-section of a die layout having any of the devices of

Figs. 5-8 formed in metal 3 (M3) and metal 2 (M2) layer regions, according to some embodiments of the disclosure.

[0022] Fig. 11 illustrates a cross-section of a die layout having any of the devices of

Figs. 5-8 formed in metal 2 (M2) and metal 1 (Ml) layer regions, according to some embodiments of the disclosure.

[0023] Fig. 12 illustrates a plot showing an improvement in energy-delay product using any of the device(s) of Figs. 5-8 compared to the device of Fig. 2A, in accordance with some embodiments of the disclosure.

[0024] Fig. 13 illustrates a flowchart of a method for forming a device of Figs. 5-8, in accordance with some embodiments.

[0025] Fig. 14 illustrates a smart device or a computer system or a SoC (System-on-

Chip) with a magnetic junction coupled to a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. DETAILED DESCRIPTION

[0026] Some embodiments describe a spin orbit coupling (SOC) based magnetic memory with efficient conduction through its SOC electrode. In some embodiments, resistivity modulation of spin orbit torque is provided for field-like torque generation. In some embodiments, the resistivity modulation is provided by a magnet inserted between the SOC electrode and a magnetic junction. In some embodiments, the magnet is a paramagnet or a ferromagnet doped with one or more of Ge, Ga, or Si. In some embodiments, the inserted magnet has a free magnetization along the same axis plane as the axis plane for the magnetization of the magnets of the magnetic junction.

[0027] In some embodiments, the magnetic junction comprises a free magnet structure coupled to a fixed magnet structure via a layer which comprises a dielectric or metal. In some embodiments, the free magnet structure of the magnetic junction comprises at least two free magnets that are coupled by a coupling layer. In some embodiments, the coupling layer comprises one or more of: Ru, Os, Hs, Fe, or other similar transition metals from the platinum group of the periodic table. In some embodiments, the coupling layer(s) are removed so that the free magnets of the free magnet structure or stack are directly connected with one another forming a single magnet (or a composite magnet).

[0028] In some embodiments, one or more of the free magnets of the free magnet structure of the magnetic junction comprises a composite magnet. The composite magnet may be a super lattice including a first material and a second material, wherein the first material includes one of: Co, Ni, Fe, or Heusler alloy, and wherein the second material includes one of: Pt, Pd, Ir, Ru, or Ni. In some embodiments, the fixed magnet of the magnetic junction also comprises a composite magnet.

[0029] The term“free” or“unfixed” here with reference to a magnet refers to a magnet whose magnetization direction can change along its easy axis upon application of an external field or force (e.g., Oersted field, spin torque, etc.). Conversely, the term“fixed” or “pinned” here with reference to a magnet refers to a magnet whose magnetization direction is pinned or fixed along an axis and which may not change due to application of an external field (e.g., electrical field, Oersted field, spin torque,).

[0030] Here, perpendicularly magnetized magnet (or perpendicular magnet, or magnet with perpendicular magnetic anisotropy (PMA)) refers to a magnet having a magnetization which is substantially perpendicular to a plane of the magnet or a device. For example, a magnet with a magnetization which is in a z-direction in a range of 90 (or 270) degrees +/- 20 degrees relative to an x-y plane of a device. [0031] Here, an in-plane magnet refers to a magnet that has magnetization in a direction substantially along the plane of the magnet. For example, a magnet with a magnetization which is in an x or y direction and is in a range of 0 (or 180 degrees) +/- 20 degrees relative to an x-y plane of a device.

[0032] The term“device” may generally refer to an apparatus according to the context of the usage of that term. For example, a device may refer to a stack of layers or structures, a single structure or layer, a connection of various structures having active and/or passive elements, etc. Generally a device is a three dimensional structure with a plane along the x-y direction and a height along the z direction of an x-y-z Cartesian coordinate system. The plane of the device may also be the plane of an apparatus which comprises the device.

[0033] There are many technical effects of the various embodiments. For example, in some embodiments, the out-of-plane magnetization switching enables perpendicular magnet anisotropy (PMA) based magnetic devices (e.g., MRAM and logic) comprising spin orbit effects that generate perpendicular spin currents. The perpendicular magnet switch of some embodiments enables low programming voltages (or higher current for identical voltages) enabled by giant spin orbit effects (GSOE) for perpendicular magnetic memory and logic.

The perpendicular magnet switch, of some embodiments, results in lower write error rates which enable faster MRAM (e.g., write time of less than 10 ns). The perpendicular magnet switch of some embodiments decouples write and read paths to enable faster read latencies. The perpendicular magnet switch of some embodiments uses significantly smaller read current through the magnetic junction (e.g., MTJ or spin valve) and provides improved reliability of the tunneling oxide and MTJs. For example, less than 10 mA compared to 100 pA for nominal write is used by the perpendicular magnet switch of some embodiments.

[0034] In various embodiments, the magnet inserted between the SOC interconnect and the magnetic junction allows for spins to pass through the SOC electrode to the magnetic junction while allowing for most of the charge current to pass though the SOC electrode. As such, less input charge current (e.g., write current) is divided between the free magnet of the magnetic junction and the SOC electrode, resulting in overall power and conduction efficiency of the SOC device.

[0035] In the following description, numerous details are discussed to provide a more thorough explanation of embodiments of the present disclosure. It will be apparent, however, to one skilled in the art, that embodiments of the present disclosure may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring embodiments of the present disclosure.

[0036] Note that in the corresponding drawings of the embodiments, signals are represented with lines. Some lines may be thicker, to indicate more constituent signal paths, and/or have arrows at one or more ends, to indicate primary information flow direction. Such indications are not intended to be limiting. Rather, the lines are used in connection with one or more exemplary embodiments to facilitate easier understanding of a circuit or a logical unit. Any represented signal, as dictated by design needs or preferences, may actually comprise one or more signals that may travel in either direction and may be implemented with any suitable type of signal scheme.

[0037] Throughout the specification, and in the claims, the term "connected" means a direct connection, such as electrical, mechanical, or magnetic connection between the things that are connected, without any intermediary devices.

[0038] The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between the things that are connected or an indirect connection, through one or more passive or active intermediary devices.

[0039] The term“adjacent” here generally refers to a position of a thing being next to

(e.g., immediately next to or close to with one or more things between them) or adjoining another thing (e.g., abutting it).

[0040] The term "circuit" or“module” may refer to one or more passive and/or active components that are arranged to cooperate with one another to provide a desired function.

[0041] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data/clock signal. The meaning of "a," "an," and "the" include plural references. The meaning of "in" includes "in" and "on."

[0042] The term“scaling” generally refers to converting a design (schematic and layout) from one process technology to another process technology and subsequently being reduced in layout area. The term“scaling” generally also refers to downsizing layout and devices within the same technology node. The term“scaling” may also refer to adjusting (e.g., slowing down or speeding up - i.e. scaling down, or scaling up respectively) of a signal frequency relative to another parameter, for example, power supply level. The terms “substantially,”“close,”“approximately,”“near, ” and“about,” generally refer to being within +/- 10% of a target value.

[0043] Unless otherwise specified the use of the ordinal adjectives“first,”“second,” and“third,” etc., to describe a common object, merely indicate that different instances of like objects are being referred to, and are not intended to imply that the objects so described must be in a given sequence, either temporally, spatially, in ranking or in any other manner.

[0044] For the purposes of the present disclosure, phrases“A and/or B” and“A or B” mean (A), (B), or (A and B). For the purposes of the present disclosure, the phrase“A, B, and/or C” means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B and C).

[0045] The terms“left,”“right,”“front,”“back,”“top,� �“bottom,”“over,”“under,” and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions.

[0046] For the purposes of present disclosure, the terms“spin” and“magnetic moment” are used equivalently. More rigorously, the direction of the spin is opposite to that of the magnetic moment, and the charge of the particle is negative (such as in the case of electron).

[0047] It is pointed out that those elements of the figures having the same reference numbers (or names) as the elements of any other figure can operate or function in any manner similar to that described, but are not limited to such.

[0048] Fig. 1A illustrates a magnetization hysteresis plot 100 for ferromagnet (FM)

101. The plot shows magnetization response to an applied magnetic field for ferromagnet 101. The x-axis of plot 100 is magnetic field Ή’ while the y-axis is magnetization‘m’. For FM 101, the relationship between Ή’ and‘m’ is not linear and results in a hysteresis loop as shown by curves 102 and 103. The maximum and minimum magnetic field regions of the hysteresis loop correspond to saturated magnetization configurations 104 and 106, respectively. In saturated magnetization configurations 104 and 106, FM 101 has stable magnetizations. In the zero magnetic field region 105 of the hysteresis loop, FM 101 does not have a definite value of magnetization, but rather depends on the history of applied magnetic fields. For example, the magnetization of FM 101 in configuration 105 can be either in the +x direction or the -x direction for an in-plane FM. As such, changing or switching the state of FM 101 from one magnetization direction (e.g., configuration 104) to another magnetization direction (e.g., configuration 106) is time consuming resulting in slower nanomagnets response time. It is associated with the intrinsic energy of switching proportional to the area in the graph contained between curves 102 and 103.

[0049] Fig. IB illustrates magnetization plot 120 for paramagnet 121. Plot 120 shows the magnetization response to an applied magnetic field for paramagnet 121. The x-axis of plot 120 is magnetic field Ή’ while the y-axis is magnetization‘m’. A paramagnet, as opposed to a ferromagnet, exhibits magnetization when a magnetic field is applied to it. Paramagnets generally have magnetic permeability greater or equal to one and hence are attracted to magnetic fields. Compared to plot 100, the magnetic plot 120 of Fig. IB does not exhibit hysteresis which allows for faster switching speeds and smaller switching energies between the two saturated magnetization configurations 124 and 126 of curve 122. In the middle region 125, paramagnet 121 does not have any magnetization because there is no applied magnetic field (e.g., H=0). The intrinsic energy associated with switching is absent in this case.

[0050] In some embodiments, paramagnet 121 comprises a material which includes one or more of: Platinum(Pt), Palladium (Pd), Tungsten (W), Cerium (Ce), Aluminum (Al), Lithium (Li), Magnesium (Mg), Sodium (Na), CnCh (chromium oxide), CoO (cobalt oxide), Dysprosium (Dy), Dy ₂ 0 (dysprosium oxide), Erbium (Er), EnCh (Erbium oxide), Europium (Eu), EU2O3 (Europium oxide), Gadolinium (Gd), Gadolinium oxide (Gd ₂ 03), FeO and Fe ₂ 03 (Iron oxide), Neodymium (Nd), Nd ₂ 03 (Neodymium oxide), K0 ₂ (potassium superoxide), praseodymium (Pr), Samarium (Sm), SrmCh (samarium oxide), Terbium (Tb), Tb ₂ 03 (Terbium oxide), Thulium (Tm), TrmCh (Thulium oxide), or V ₂ 03 (Vanadium oxide). In some embodiments, paramagnet 121 comprises dopants which include one or more of: Ce,

Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb. In various embodiments, the magnet can be either a FM or a paramagnet.

[0051] Figs. 2A-B illustrate a three-dimensional (3D) view 200 and corresponding top view 220, respectively, of device (also referred to device 200) having an out-of-plane magnetic tunnel junction (MTJ) stack coupled to a spin orbit coupling (SOC) interconnect, where the MTJ stack includes a free magnet layer much smaller than a length of the SOC interconnect.

[0052] Here, the stack of layers having magnetic junction 221 is coupled to an electrode 222 comprising spin Hall effect (SHE) or SOC material, where the SHE material converts charge current Iw (or write current) to spin polarized current Is. The device of Fig. 2A forms a three-terminal memory cell with SHE induced write mechanism and MTJ based read-out. The device of Fig. 2A comprises magnetic junction 221, SHE Interconnect or electrode 222, and non-magnetic metal(s) 223a/b. In one example, MTJ 221 comprises layers 22la, 22lb, and 22lc. In some embodiments, layers 22la and 22lc are ferromagnetic layers. In some embodiments, layer 22lb is a metal or a tunneling dielectric.

[0053] For example, when the magnetic junction is a spin valve, layer 22lb is metal or a metal oxide (e.g., a non-magnetic metal such as Al and/or its oxide) and when the magnetic junction is a tunneling junction, then layer 22lb is a dielectric (e.g. MgO, AhCh). One or both ends along the horizontal direction of SHE Interconnect 222 is formed of non magnetic metals 223a/b. Additional layers 22ld, 22 le, 22lf, and 22lg can also be stacked on top of layer 22lc. In some embodiments, layer 22lg is a non-magnetic metal electrode.

[0054] So as not to obscure the various embodiments, the magnetic junction is described as a magnetic tunneling junction (MTJ). However, the embodiments are also applicable for spin valves. A wide combination of materials can be used for material stacking of magnetic junction 221. For example, the stack of layers 22la, 22lb, 22lc, 22ld, 22 le, 22lf, and 22lg are formed of materials which include: Co _x Fe _y B _z , MgO, Co _x Fe _y B _z , Ru, Co _x Fe _y B _z , IrMn, and Ru, respectively, where‘x,’‘y,’ and‘z’ are fractions of elements in the alloys. Other materials may also be used to form MTJ 221. MTJ 221 stack comprises free magnetic layer 22la, MgO tunneling oxide 22lb, a fixed magnetic layer 22lc/d/e which is a combination of CoFe, Ru, and CoFe layers, respectively, referred to as Synthetic Anti- Ferromagnet (SAF), and an Anti-Ferromagnet (AFM) layer 22lf. The SAF layer has the property that the magnetizations in the two CoFe layers are opposite, and allows for cancelling the dipole fields around the free magnetic layer such that a stray dipole field will not control the free magnetic layer.

[0055] In some embodiments, the free and fixed magnetic layers (22la and 22lc, respectively) are formed of CFGG (i.e., Cobalt (Co), Iron (Fe), Germanium (Ge), or Gallium (Ga) or a combination of them). In some embodiments, FM 22la/c are formed from Heusler alloys. Heusler alloys are ferromagnetic metal alloys based on a Heusler phase. Heusler phases are intermetallic with certain composition and face-centered cubic crystal structure. The ferromagnetic property of the Heusler alloys are a result of a double-exchange mechanism between neighboring magnetic ions. In some embodiments, the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[0056] In some embodiments, fixed magnet layer 22 lc is a magnet with perpendicular magnetic anisotropy (PMA). For example, fixed magnet structure 22 lc has a magnetization pointing along the z-direction and is perpendicular to the x-y plane of the device 200. In some embodiments, the magnet with PMA comprises a stack of materials, wherein the materials for the stack are selected from a group consisting of: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO; Mn _x Ga _y ; Materials with Llo symmetry; and materials with tetragonal crystal structure. In some embodiments, the magnet with PMA is formed of a single layer of one or more materials. In some embodiments, the single layer is formed of MnGa.

[0057] Llo is a crystallographic derivative structure of an FCC (face centered cubic lattice) structure and has two of the faces occupied by one type of atom and the comer and the other face occupied with the second type of atom. When phases with the Llo structure are ferromagnetic the magnetization vector usually is along the [0 0 1] axis of the crystal.

Examples of materials with Llo symmetry include CoPt and FePt. Examples of materials with tetragonal crystal structure and magnetic moment are Heusler alloys such as CoFeAl, MnGe, MnGeGa, and MnGa.

[0058] SHE Interconnect 222 (or the write electrode) includes one or more of b-

Tantalum (b-Ta), Ta, b-Tungsten (b-W), W, Pt, Copper (Cu) doped with elements such as Iridium, Bismuth and any of the elements of 3d, 4d, 5d and 4f, 5f periodic groups in the Periodic Table which may exhibit high spin orbit coupling. In some embodiments, SHE interconnect 122 comprises a spin orbit material which includes one or more of: graphene, P8 \ WS ₂ , M0S2, TiSe ₂ , WSe ₂ , MoSe ₂ , B2S3, Sb ₂ S ₃ , Ta S. Re ₂ S?, LaCPS ₂ , LaOAsS ₂ , ScOBiS ₂ , GaOBiS ₂ , AIOB1S2, LaOSbS ₂ , BiOBiS ₂ , YOB1S2, InOBiS ₂ , LaOBiSe ₂ , TiOBiS ₂ , CeOBiS2, PrOBiS2, NdOBiS2, LaOBiS2, or SrFBiS2. In some embodiments, the SHE interconnect 222 comprises spin orbit material which includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material.

[0059] In some embodiments, the 2D materials include one or more of: Mo, S, W, Se,

Graphene, M0S2, WSe2, WS2, or MoSe2. In some embodiments, the 2D materials include an absorbent which includes one or more of: Cu, Ag, Pt, Bi, Fr, or H absorbents. In some embodiments, the SHE interconnect 222 comprises a spin orbit material which includes materials that exhibit Rashba-Bychkov effect. In some embodiments, material which includes materials that exhibit Rashba-Bychkov effect comprises materials ROCh2, where‘R’ includes one or more of: La, Ce, Pr, Nd, Sr, Sc, Ga, Al, or In, and where“Ch” is a chalcogenide which includes one or more of: S, Se, or Te.

[0060] In some embodiments, SHE Interconnect 222 transitions into high

conductivity non-magnetic metal(s) 223a/b to reduce the resistance of SHE Interconnect 222. The non-magnetic metal(s) 223a/b include one or more of: Cu, Co, a-Ta, Al, CuSi, or NiSi.

[0061] In one case, the magnetization direction of fixed magnetic layer 22lc is perpendicular relative to the magnetization direction of free magnetic layer 22la (e.g., magnetization directions of the free and fixed magnetic layers are not parallel, rather they are orthogonal). For example, the magnetization direction of free magnetic layer 22la is in-plane (e.g., along the x-y plane) while the magnetization direction of fixed magnetic layer 22lc is perpendicular (e.g., along the z-axis) to the in-plane. In another case, magnetization direction of fixed magnetic layer 22 la is in-plane while the magnetization direction of free magnetic layer 22 lc is perpendicular to the plane.

[0062] The thickness of a ferromagnetic layer (e.g., fixed or free magnetic layer) may determine its equilibrium magnetization direction. For example, when the thickness of the ferromagnetic layer 22la/c is above a certain threshold (depending on the material of the magnet, e.g. approximately 1.5 nm for CoFe), then the ferromagnetic layer exhibits magnetization direction which is in-plane. Likewise, when the thickness of the ferromagnetic layer 22la/c is below a certain threshold (depending on the material of the magnet), then the ferromagnetic layer 22la/c exhibits magnetization direction which is perpendicular to the plane of the magnetic layer.

[0063] Other factors may also determine the direction of magnetization. For example, factors such as surface anisotropy (depending on the adjacent layers or a multi-layer composition of the ferromagnetic layer) and/or crystalline anisotropy (depending on stress and the crystal lattice structure modification such as FCC (face centered cubic lattice), BCC (body centered cubic lattice), or Llo-type of crystals, where Llo is a type of crystal class which exhibits perpendicular magnetizations), can also determine the direction of magnetization.

[0064] In this example, the applied current I _w is converted into spin current by SHE

Interconnect 222 (also referred to as the spin orbit coupling interconnect). This spin current switches the direction of magnetization of the free layer and thus changes the resistance of MTJ 221. However, to read out the state of MTJ 221, a sensing mechanism is needed to sense the resistance change.

[0065] The magnetic cell is written by applying a charge current via SHE

Interconnect 222. The direction of the magnetic writing in free magnet layer 221 a is decided by the direction of the applied charge current. Positive currents (e.g., currents flowing in the +y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the +x direction. The injected spin current in turn produces spin torque to align the free magnet 22 la (coupled to the SHE layer 222 of SHE material) in the +x direction. Negative currents (e.g., currents flowing in the -y direction) produce a spin injection current with transport direction (along the +z direction) and spins pointing to the -x direction. The injected spin current in turn produces spin torque to align the free magnet 22 la (coupled to the SHE material of layer 222) in the -x direction. In some embodiments, in materials with the opposite sign of the SHE/SOC effect, the directions of spin polarization and thus of the free layer magnetization alignment are reversed compared to the above.

[0066] The resistivity model of Fig. 2C illustrates the impact of current division or splitting when write current I _w (or 1223a) splits between free magnet 22 la and SOC electrode 222. The current through free magnet 221 a is l22ia, where the free magnet 221 a has resistance R.22ia. The remaining current through SOC electrode 222 is I222, where the SOC electrode 222 has resistance R222. The current then combines as it flows towards conductor 223b. This combined current is 1223b which is equal to current 1223a. Generally, to achieve field-like torque from the SOC interconnect 222 on free magnet 22la, the free magnet 22la is directly adjacent to SOC interconnect 222. However, this results in current splitting. The current thought the free magnet 22 la does not produce the field-like torque and may be considered wasted energy.

[0067] Fig. 3 illustrates a cross-section 300 of the SOC interconnect with electrons having their spins polarized in-plane and deflected up and down resulting from a flow of charge current. In this example, positive charge current represented by J _c produces spin-front (e.g., in the +x direction) polarized current 301 and spin-back (e.g., in the -x direction) polarized current 302. The injected spin current l _s generated by a charge current I _c in the write electrode 222 is given by:

where, the vector of spin current I _s = / _T — points in the direction of transferred magnetic moment and has the magnitude of the difference of currents with spin along and opposite to the spin polarization direction, z is the unit vector perpendicular to the interface, P _SHE is the spin Hall injection efficiency which is the ratio of magnitude of transverse spin current to lateral charge current, w is the width of the magnet, t is the thickness of the SHE

Interconnect (or write electrode) 222, _S f is the spin flip length in SHE Interconnect 222,

Q _5HE is the spin Hall angle for SHE Interconnect 222 to free ferromagnetic layer interface. The injected spin angular momentum responsible for the spin torque given by:

S = h T _s /2e . . . (2)

[0068] The generated spin up and down currents 301/302 (e.g., / _s ) are described as a vector cross-product given by:

[0069] This spin to charge conversion is based on Tunnel Magneto Resistance (TMR) which is highly limited in the signal strength generated. The TMR based spin to charge conversion has low efficiency (e.g., less than one).

[0070] Fig. 4A illustrates a plot 420 showing write energy-delay conditions for one transistor and one MTJ with spin Hall effect (SHE) material compared to traditional MTJs.

[0071] Fig. 4B illustrates plot 430 showing write energy-delay conditions for one transistor and one magnetic tunnel junction (MTJ) with spin Hall effect (SHE) material compared to traditional MTJs. Here, x-axis is energy per write operation in femto-Joules (fJ) while the y-axis is delay in nano-seconds (ns).

[0072] Here, the energy-delay trajectory of SHE and MTJ devices are compared for in-plane magnet switching as the applied write voltage is varied. The energy-delay relationship (for in-plane switching) can be written as:

where R _write is the write resistance of the device (resistance of SHE electrode or resistance of MTJ-P or MTJ-AP, where MTJ-P is a MTJ with parallel magnetizations while MTJ-AP is an MTJ with anti-parallel magnetizations, m ₀ is vacuum permeability, e is the electron charge. The equation shows that the energy at a given delay is directly proportional to the square of

M Ve

the Gilbert damping a. Here the characteristic time, t ₀ = Ί varies as the spin

1. _e Rm _B

polarization varies for various SHE metal electrodes (e.g., 423, 424, 425). Plot 420 shows five curves 421, 422, 423, 424, and 425. Curves 421 and 422 show write energy-delay conditions using traditional MTJ devices without SHE material.

[0073] For example, curve 421 shows the write energy-delay condition caused by switching a magnet from anti-parallel (AP) to parallel (P) state, while curve 422 shows the write energy-delay condition caused by switching a magnet from P to AP state. Curves 422, 423, and 424 show write energy-delay conditions of an MTJ with SHE material. Clearly, write energy-delay conditions of an MTJ with SHE material is much lower than the write energy-delay conditions of an MTJ without SHE material. While the write energy-delay of an MTJ with SHE material improves over a traditional MTJ without SHE material, further improvement in write energy-delay is desired.

[0074] Fig. 4B illustrates plot 430 comparing reliable write times for spin Hall

MRAM and spin torque MRAM. There are three cases considered in plot 430. Waveform 431 is the write time for in-plane MTJ, waveform 432 is the write time for PMA MTJ, and waveform 433 is the write time for spin Hall MTJ. The cases considered here assume a 30 X 60 nm magnet with 40 kT energy barrier and 3.5 nm SHE electrode thicknesses. The energy- delay trajectories of the devices are obtained assuming a voltage sweep from 0 V to 0.7 V in accordance to voltage restrictions of scaled CMOS. The energy-delay trajectory of the SHE- MTJ devices exhibits broadly two operating regions A) Region 1 where the energy-delay

M Ve _/

product is approximately constant (z _d < ^s // ¾ and Region 2 where the energy is

M Ve _/

proportional to the delay t _ά > ^s j _j p The two regions are separated by energy

minima at where minimum switching energy is obtained for the spin

torque devices.

[0075] The energy-delay trajectory of the STT-MTJ (spin transfer torque MTJ) devices is limited with a minimum delay of 1 ns for in-plane devices at 0.7 V maximum applied voltage, the switching energy for P-AP and AP-P are in the range of 1 pJ/write. In contrast, the energy-delay trajectory of SHE-MTJ (in-plane anisotropy) devices can enable switching times as low as 20 ps (b-W with 0.7 V, 20 fj/bit) or switching energy as small as 2 fj (b-W with 0.1 V, 1.5 ns switching time).

[0076] Figs. 5A-C illustrate a 3D view 500, corresponding cross-section view 520, and a resistance model 530, respectively, of a device having a magnetic junction with magnets having perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. The device of Fig. 5A is similar to the device of Fig. 2A except that the free magnet 221 a of Fig. 2A is separated from the SOC interconnect 222 by magnet 501. Magnet 501 can be a single layer or a composite layer, in accordance with various embodiments. In some embodiments, resistivity modulation of spin orbit torque is provided for field-like torque generation. In some embodiments, the resistivity modulation is provided by magnet 501 inserted between SOC electrode 222 and a magnetic junction 521.

In some embodiments, magnet 501 is a paramagnet or a ferromagnet doped with one or more of Ge, Ga, Si, O, N, Co, Bi, or Sb. In some embodiments, the inserted magnet has a free magnetization along the same axis plane as the axis plane for the magnetization of the magnets of the magnetic junction 531.

[0077] In some embodiments, the structure replacing free magnet 22 la comprises at least two free magnets 52laa and 52lac with a coupling layer 52lab between them, where one of the free magnet couples to (or is adjacent to) the SOC electrode 222 while the other free magnet of the structure couples to or is adjacent to a dielectric (e.g., when the magnetic junction is an MTJ) or a metal or its oxide (e.g., when the magnetic junction is a spin valve). In some embodiments, the structure comprises a first free magnet 52 laa having perpendicular magnetization that can point substantially along the + z-axis or - z-axis according to an external field (e.g., spin torque, spin coupling, electric field); a coupling layer 52lab; and a second free magnet 52 lac having perpendicular magnetization that can point substantially along the + z-axis or - z-axis. In various embodiments, the second free magnet 52lac is adjacent to layer 22lb (e.g., dielectric or metal/metal-oxide).

[0078] In some embodiments, magnet 501 is adjacent to the first structure (e.g., layers

52laa/ab/ac) of the magnetic junction. In various embodiments, magnet 501 is doped with a material to increase resistivity of the magnet. As such, less current flows through magnet 501 compared to the case described with reference to Figs. 2A-C. Hence, the switching speed of the free magnets in the structure is improved for the same power consumption over the switching speed of the free magnet 22la of Fig. 2A. In some embodiments, magnet 501 has a thickness tm in a range of 0.5 nm to 2 nm, and wherein the thickness extends from the interconnect 222 towards the magnetic junction 521. In some embodiments, the doping material includes one or more of: Ge, Ga, Si, F, O, N, Co, Bi, or Sb. In some embodiments, when magnet 501 is a ferromagnet, it includes one of: Co, Ni, Fe, or Heusler alloy. In some embodiments, the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. For example, magnet 501 is one of: Co2FeGe, Co2FeGeGa, or Co2FeSi and the like.

[0079] In some embodiments, when magnet 501 is a paramagnet, it includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er, Eu, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V. In some embodiments, magnet 501 has a surface area equal or greater than a surface area of the first structure (e.g., layer 52laa) adjacent to the magnet 501. In the example of Fig. 5A, magnet 501 is a free magnet with PMA.

[0080] In some embodiments, the device of Fig. 5A includes an in-plane fixed magnet 524 adjacent to one of the surfaces of the SOC interconnect 222 such that the magnetic junction 521 is formed on the other surface opposite to the surface of the SOC interconnect 222.

[0081] While various embodiments here illustrate the use of magnet structure 501 being adjacent to a spin Hall effect write electrode 222, the embodiments are applicable to a regular spin transfer torque (SOT) electrode (not shown) which can replace spin Hall effect write electrode 222. [0082] In some embodiments, the coupling layer 521 ab includes one or more of: Ru,

Os, Hs, Fe, or other transition metals from the platinum group of the periodic table. In some embodiments, magnets 52laa, 52 lac, and 524 comprise CFGG. In some embodiments, magnets 52laa, 52lac, and 524 are formed from Heusler alloys. In some embodiments, the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. In some embodiments, the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi,

Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu.

[0083] In some embodiments, magnets 52laa and 52 lac with PMA comprises a stack of materials, wherein the materials for the stack are selected from a group comprising: Co and Pt; Co and Pd; Co and Ni; MgO, CoFeB, Ta, CoFeB, and MgO; MgO, CoFeB, W, CoFeB, and MgO; MgO, CoFeB, V, CoFeB, and MgO; MgO, CoFeB, Mo, CoFeB, and MgO;

Mn _x Ga _y ; Materials with Llo symmetry; or materials with tetragonal crystal structure. In some embodiments, the magnet with PMA is formed of a single layer of one or more materials. In some embodiments, the single layer comprises Mn and Ga (e.g., MnGa).

[0084] Compared to in-plane magnets, perpendicular magnets generally allow for easier lithography constraints on the magnetic dots with reduced aspect ratio requirements for shape. Perpendicular magnets (e.g., with out-of-plane magnetization) exhibit higher retention since the magnetic energy barrier is proportional to anisotropy. Another benefit of perpendicular magnets is that they provide greater choice perpendicular anisotropy and super lattices. While the embodiments of Figs. 5A-B are illustrated with reference to magnets having PMA magnetizations, the embodiments are also applicable to magnets having in-plane magnetizations (not shown). In one such embodiment, the free magnets 52laa and 52 lac, and fixed magnet 221 c are in-plane magnets with in-plane magnetizations, while the fixed magnet 524 has perpendicular fixed magnetization to provide an effective out-of-plane field to the in-plane free magnets 521 aa and/or 521 ac.

[0085] The resistive model 520 of Fig. 5C illustrates that by increasing resistivity of magnet 501, more charge current passes through SOC interconnect 222 than magnet 501. As such, more spins are generated that travel along the z-direction towards magnetic junction 521. As more spins travel, the switching speed of free magnet 52laa/ac increases. In this example, the current through magnet 501 is I501, where magnet 501 has resistance R501. The remaining current through SOC electrode 222 is I222, where the SCO electrode 222 has resistance R222. The current then combines as it flows towards conductor 223b. This combined current is 1223b which is equal to current 1223a.

[0086] A typical problem with Spin Orbit torque -MTJ based memory is that low resistivity of the magnet leads to current spreading out from the spin orbit electrode into the adjacent ferromagnet/paramagnet layer. As a result, the torque generated by the Spin-orbit electrode, which is proportional to the current flow through it, is reduced. High resistivity of the magnet means that the current flow will be limited to the Spin-Orbit electrode layer which means an increased efficiency and reduced writing power for the memory.

[0087] In some embodiments, magnet 501 is in-plane magnet (e.g., magnetization along the y-direction) while SOC interconnect 222 is also in-plane (e.g., along the x-y plane) and provides spin orbit torque to magnet 501 when charge current passes through it. In some embodiments, magnet 501 is out-of-plane magnet (e.g., magnetization along the z-direction) while SOC interconnect 222 is in-plane (e.g., along the x-y plane) and provides spin orbit torque to magnet 501 when charge current passes through it. In some embodiments, magnet 501 is in-plane magnet while SOC interconnect 222 provides Rashba-Bychkov effect with spins along the z-direction (e.g., perpendicular to the plane of the device).

[0088] Figs. 6A-B illustrate a 3D view and corresponding cross-section view, respectively, of a device having a magnetic junction with magnets having in-plane magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. The device of Fig. 6A is similar to the device of Fig. 5A, but for using in-plane magnets instead of magnets with PMA. For example, the magnets of magnetic junction 521 are in-plane magnets (e.g., with magnetizations along a plane of a device, here along the y-axis) and magnet 501 is also in-plane magnet. Technical effect wise, the device of Fig. 6A performs similarly to the device of Fig. 5A, and improves switching speed of free magnets 52laa and 52 lac (relative to switching speed of free magnet 22 la of Fig. 2A) for the same input charge current (e.g., write current I _w ) because magnet 501 provides a higher resistivity path.

[0089] Figs. 7A-B illustrate a 3D view 700 and corresponding cross-section view

720, respectively, of a device having a magnetic junction with magnets having perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. The device of Fig. 7A is similar to the device of Fig. 5A, but for using magnetic junction of Fig. 2A such that layer 221 a is adjacent to magnet 501. Technical effect wise, the device of Fig. 7A performs similarly to the device of Fig. 5A, and improves switching speed of free magnets 52laa and 52lac (relative to switching speed of free magnet 22la of Fig. 2A) for the same input charge current (e.g., write current Iw) because magnet 501 provides a higher resistivity path.

[0090] Fig. 8A illustrates a cross-section 800 of a device having a magnetic junction with magnets having perpendicular magnetizations, where a free magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[0091] The magnetic junction here is illustrated by reference sign 821 where the layers under layer 22lb (e.g., dielectric or metal/metal-oxide) together form the structure comprising the free magnet of the junction. The device of Fig. 8A is similar to the device of Fig. 5A except that the free magnets 521 aa and 52lae are replaced with composite magnets having multiple layers.

[0092] In some embodiments, the composite stack of multi-layer free magnet 821 aa includes‘n’ layers of first material and second material. For example, the composite stack comprises layers 82laai- _n and 82labi-n stacked in an alternating manner, where‘n’ has a range of 1 to 10. In some embodiments, the first material includes one of: Co, Ni, Fe, or an Heusler alloy. In some embodiments, the second material includes one of: Pt, Pd, Ir, Ru, or Ni. In some embodiments, the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. In some embodiments, the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu. In some embodiments, the first material has a thickness tl in a range of 0.6 nm to 2 nm. In some embodiments, the second material has a thickness t2 in a range of 0.1 nm to 3 nm. While the embodiments here show first material being at the bottom followed by the second material, the order can be reversed without changing the technical effect.

[0093] In some embodiments, composite stack of multi-layer free magnet 82lbb includes‘n’ layers of first material and second material. For example, the composite stack comprises layers 82laai- _n and 82labi- _n stacked in an alternating manner, where‘n’ has a range of 1 to 10. In some embodiments, the first material includes one of: Co, Ni, Fe, or a Heusler alloy. In some embodiments, the second material includes one of: Pt, Pd, Ir, Ru, or Ni. In some embodiments, the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. In some embodiments, the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu. In some embodiments, the first material has a thickness tl in a range of 0.6 nm to 2 nm. In some embodiments, the second material has a thickness t2 in a range of 0.1 nm to 3 nm. While the embodiments here show first material being at the bottom followed by the second material, the order can be reversed without changing the technical effect.

[0094] Fig. 8B illustrates a cross-section 820 of a device having a magnetic junction with magnets having perpendicular magnetizations, where a free magnet structure and a fixed magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. Here, fixed magnet 221 c of Fig. 8A is replaced with a composite stack. As such, the magnetic junction is labeled as 831.

[0095] In some embodiments, composite stack of multi-layer fixed magnet 821 cc includes‘n’ layers of first material and second material. For example, the composite stack comprises layers 82laai _-n and 82labi- _n stacked in an alternating manner, where‘n’ has a range of 1 to 10. In some embodiments, the first material includes one of: Co, Ni, Fe, or Heusler alloy. In some embodiments, the second material includes one of: Pt, Pd, Ir, Ru, or Ni. In some embodiments, the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. In some embodiments, the Heusler alloy includes one of: Cu ₂ MnAl, Cu ₂ MnIn, Cu ₂ MnSn, Ni ₂ MnAl, Ni ₂ MnIn, Ni ₂ MnSn, Ni ₂ MnSb, Ni ₂ MnGa Co ₂ MnAl, Co ₂ MnSi, Co ₂ MnGa, Co ₂ MnGe, Pd ₂ MnAl, Pd ₂ MnIn, Pd ₂ MnSn, Pd ₂ MnSb, Co ₂ FeSi, Co ₂ FeAl, Fe ₂ VAl, Mn ₂ VGa, Co ₂ FeGe, MnGa, or MnGaRu. In some embodiments, the first material has a thickness t3 in a range of 0.6 nm to 2 nm. In some embodiments, the second material has a thickness t4 in a range of 0.1 nm to 3 nm. While the embodiments here show the first material being at the bottom followed by the second material, the order can be reversed without changing the technical effect.

[0096] Fig. 8C illustrates a cross-section 850 of a device having a magnetic junction with magnets having perpendicular magnetizations, where a fixed magnet structure and one of the free magnets of a free magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. Here, free magnet 82lbb of Fig. 8C is replaced with a non composite free magnet 521 ac. As such, the magnetic junction is labeled as 851.

[0097] Fig. 8D illustrates a cross-section 860 of a device having a magnetic junction with magnets having perpendicular magnetizations, where a fixed magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. Here, free magnet 82laa of Fig. 8D is replaced with a non-composite free magnet 521 aa. As such, the magnetic junction is labeled as 861.

[0098] Fig. 8E illustrates a cross-section 870 of a device having a magnetic junction with magnets having perpendicular magnetizations, where a fixed magnet structure and one of the free magnets of a free magnet structure of the magnetic junction comprises a stack of magnets with perpendicular magnetizations, and a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. Here, free magnet 82laa of Fig. 8B is replaced with a non composite free magnet 521 aa. As such, the magnetic junction is labeled as 871.

[0099] Fig. 9A illustrates a plot 900 showing spin polarization capturing switching of a free magnet structure coupled to a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. Fig. 9B illustrates a magnetization plot 920 associated with Fig. 9A, according to some embodiments of the disclosure. Plot 900 shows switching of the spin orbit torque device with PMA. Here, waveforms 901, 902, and 903 represent the magnetization projections on the x, y, and z axes, respectively. The magnet starts with z-magnetization of - 1. Positive spin orbit torque (SOT) is applied from 5 ns (nanoseconds) to 50 ns. It leads to switching the z-magnetization to 1. Then, a negative spin orbit torque is applied between 120 ns and 160 ns. It leads to switching the z-magnetization to 1. This illustrates change of magnetization in response to write charge current of certain polarity.

[00100] Fig. 9C illustrates plot 930 showing spin polarization capturing switching of the free magnet structure coupled to a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure. Fig. 9D illustrates magnetization plot 940 associated with Fig. 9C, according to some embodiments of the disclosure. Here, waveforms 931, 932, and 933 represent the magnetization projections on x, y, and z axes, respectively. The difference from the case of Fig. 9C is that negative spin orbit torque (SOT) is applied from 5 ns to 50 ns. As a result, the z- magnetization remains close to -1. This illustrates the persistence of magnetization in response to write charge current of opposite polarity.

[00101] Fig. 10 illustrates a cross-section 1000 of a die layout having the device(s) of Figs. 5-8 formed in metal 3 (M3) and metal 2 (M2) layer regions, according to some embodiments of the disclosure. Cross-section 1000 illustrates an active region having a transistor MN comprising diffusion region 1001, a gate terminal 1002, drain terminal 1004, and source terminal 1003. The source terminal 1003 is coupled to SL (source line) via poly or via, where the SL is formed on Metal 0 (M0). In some embodiments, the drain terminal 1004 is coupled to MOa (also metal 0) through via 1005. The drain terminal 1004 is coupled to spin Hall electrode 1022/222 through Via 0-1 (e.g., via connecting metal 0 to metal 1 layers), metal 1 (Ml), Via 1-2 (e.g., via connecting metal 1 to metal 2 layers), and Metal 2 (M2).

[00102] In some embodiments, the magnetic junction (e.g., MTJ 1021 or spin valve) is formed in the metal 3 (M3) region. Here, MTJ 1021 (or spin valve) can be according to any one of devices described with reference to Figs. 5-8. The magnet 1023/501 is between SOC interconnect 1022 and magnetic junction 1021. Referring back to Fig. 10, in some embodiments, the perpendicular free magnet layer (e.g., 52laa or 22la) of the magnetic junction (MTJ 1021 or spin valve) couples to spin Hall electrode 1022 (e.g., electrode 222) via magnet 1023/501 which is doped with one of more of: Ge, Ga, or Si. In some embodiments, the fixed magnet layer of magnetic junction couples to the bit-line (BL) via spin Hall electrode 1022 and magnetic via 1023 through Via 3-4 (e.g., via connecting metal 4 region to metal 4 (M4)). In this example, the bit-line is formed on M4.

[00103] In some embodiments, an n-type transistor MN is formed in the frontend of the die while the spin Hall electrode 1022 is located in the backend of the die. Here, the term “backend” generally refers to a section of a die which is opposite of a“frontend” and where an IC (integrated circuit) package couples to IC die bumps. For example, high level metal layers (e.g., metal layer 6 and above in a ten-metal stack die) and corresponding vias that are closer to a die package are considered part of the backend of the die. Conversely, the term “frontend” generally refers to a section of the die that includes the active region (e.g., where transistors are fabricated) and low-level metal layers and corresponding vias that are closer to the active region (e.g., metal layer 5 and below in the ten-metal stack die example). In some embodiments, the spin Hall electrode 1022 is located in the backend metal layers or via layers for example in Via 3. In some embodiments, the electrical connectivity to the device is obtained in layers M0 and M4 or Ml and M5 or any set of two parallel interconnects. [00104] Fig. 11 illustrates a cross-section 1100 of a die layout having the device of Fig. 5A formed in metal 2 (M2) and metal 1 (Ml) layer regions, according to some embodiments of the disclosure. Compared to Fig. 10, here the magnetic junction (e.g., MTJ 1021 or spin valve) is formed in the metal 2 region and/or Via 1-2 region. In some embodiments, the spin Hall angle electrode 1022 is formed in the metal 1 region while magnetic via is formed in metal 1 or via 0-1 region.

[00105] Fig. 12 illustrates a plot 1200 showing an improvement in energy-delay product using any of the device(s) of Figs. 5-8 compared to the device of Fig. 2A, in accordance with some embodiments of the disclosure. Here, the x-axis is Write Energy (in P) and the y-axis is Delay (in ns). Here, two of the energy-delay trajectories are compared as write voltage is varied— 1201 which is the energy-delay trajectory of device 200, and 1202 is the energy delay trajectory of device(s) of Figs. 5-8. Plot 1200 illustrates that device(s) of Figs. 5-8 provide a shorter (i.e., improved) energy-delay product than device 200.

[00106] Fig. 13 illustrates flowchart 1300 of a method for forming a device having a free magnet structure which is exchanged coupled or biased by a magnetic via under an SOC interconnect, in accordance with some embodiments. While the following blocks (or process operations) in the flowchart are arranged in a certain order, the order can be changed. In some embodiments, some blocks can be executed in parallel.

[00107] At block 1301, a magnetic junction (e.g., 521) is formed. In some

embodiments, forming the magnetic junction comprises forming a stack of structures including: forming a first structure comprising a magnet with a first magnetization; a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with a second magnetization, wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures.

[00108] In some embodiments, the method of forming the magnetic junction comprises: forming a fifth structure between the first and second structures, wherein the fifth structure includes one or more of: Ru, Os, Hs, or Fe. In some embodiments, the method of forming the magnetic junction comprises forming a sixth structure between the second and third structures, wherein the sixth structure includes one or more of: Ru, Os, Hs, or Fe. In some embodiments, the method of forming the first and/or third structures comprises forming a stack including a first material and a second material different from the first material. In some embodiments, the first material includes one of: Co, Ni, Fe, or Heusler alloy, and wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V, and wherein the second material includes one of: Pt, Pd, Ir, Ru, or Ni. [00109] In some embodiments, the first material has a thickness in a range of 0.6 nm to 2 nm, and wherein the second material has a thickness in a range of 0.1 nm to 3 nm. In some embodiments, the dielectric comprises: Mg and O. In some embodiments, the method of forming the first and/or the third structures comprises a forming super lattice including a first material and a second material, wherein the first material includes one of: Co, Ni, Fe, or Heusler alloy; and wherein the second material includes one of: Pt, Pd, Ir, Ru, or Ni. In some embodiments, the method of forming the first and/or third structures comprises forming a stack of three materials including a first material adjacent to the interconnect, a second material adjacent to the first material but not in contact with the interconnect, and third material adjacent to the second material and the second structure, wherein the first material includes one or more of: Co, Ni, Fe, or Heusler alloy, wherein the second material comprises Ru; and wherein the third material includes one or more of Co, Ni, Fe, or Heusler alloy.

[00110] At block 1302, a structure (e.g., magnet 501) adjacent to the magnetic junction is formed. In some embodiments, the structure comprises a magnet doped with a material to increase resistivity of a magnet of the magnetic junction. Here, the structure adjacent to the magnetic junction is the fourth structure. In some embodiments, the fourth structure has a thickness in a range of 0.5 nm to 2 nm, and wherein the thickness extends from the interconnect towards the magnetic junction. In some embodiments, the method of forming the magnet of the fourth structure comprises forming a ferromagnet, and wherein the material includes one or more of: Ge, Ga or Si. In some embodiments, the ferromagnet of the fourth structure includes one of: Co, Ni, Fe, or Heusler alloy. In some embodiments, the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. In some embodiments, the method of forming the magnet of the fourth structure comprises forming a paramagnet, and wherein the material includes one or more of: Ge, Ga or Si. In some embodiments, the paramagnet of the fourth structure includes one or more of: Pt, Pd,

W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er, Eu, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V. In some embodiments, the fourth structure has a surface area equal or greater than a surface area of the first structure adjacent to the fourth structure.

[00111] At block 1303, an interconnect is formed adjacent to the structure, wherein the interconnect comprises a material exhibiting spin. In some embodiments, the interconnect is to generate spin Hall effect (SHE). In some embodiments, the interconnect includes one or more or: b-Tantalum (b-Ta), Ta, b-Tungsten (b-W), W, Platinum (Pt), Copper (Cu) doped with elements including on of Iridium, Bismuth or elements of 3d, 4d, 5d and 4f, 5f periodic groups, Ti, S, W, Mo, Se, B, Sb, Re, La, C, P, La, As, Sc, O, Bi, Ga, Al, Y, In, Ce, Pr, Nd, F, Ir, Mn, Pd, or Fe. In some embodiments, the method of forming the interconnect comprises forming a spin orbit material which includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material. In some embodiments, the method of forming the interconnect comprises forming a spin orbit material which includes materials that exhibit Rashba-Bychkov effect. In some embodiments, the method of forming the magnetic junction comprises forming one of a spin valve or a magnetic tunneling junction (MTJ). In some embodiments, the magnet of the first structure is a paramagnet which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er, Eu, Eu, Gd, Fe,

Nd, K, Pr, Sm, Tb, Tm, or V, or wherein the magnet of the first structure is a paramagnet which comprises dopants which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd,

Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[00112] In some embodiments, the magnet of the first structure has unfixed perpendicular magnetic anisotropy (PMA), wherein the first structure has an anisotropy axis perpendicular to a plane of a device, wherein the magnet of the third structure has fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the first and second magnetizations are substantially perpendicular to the plane of the device. In some embodiments, the magnet of the first structure has unfixed in plane magnetic anisotropy, wherein the first structure has an anisotropy axis along a plane of a device, wherein the magnet of the third structure has fixed in-plane magnetic anisotropy, wherein the third structure has an anisotropy axis along the plane of the device, and wherein the first and second magnetizations are substantially along a plane of the device.

[00113] Fig. 14 illustrates a smart device or a computer system or a SoC (System-on- Chip) with a magnetic junction coupled to a magnet with doped material to increase resistivity, wherein the magnet is adjacent to the SOC interconnect, according to some embodiments of the disclosure.

[00114] For purposes of the embodiments, the transistors in various circuits and logic blocks described here are metal oxide semiconductor (MOS) transistors or their derivatives, where the MOS transistors include drain, source, gate, and bulk terminals. The transistors and/or the MOS transistor derivatives also include Tri-Gate and FinFET transistors, Gate All Around Cylindrical Transistors, Tunneling FET (TFET), Square Wire, or Rectangular Ribbon Transistors, ferroelectric FET (FeFETs), or other devices implementing transistor functionality like carbon nanotubes or spintronic devices. MOSFET symmetrical source and drain terminals i.e., are identical terminals and are interchangeably used here. A TFET device, on the other hand, has asymmetric Source and Drain terminals. Those skilled in the art will appreciate that other transistors, for example, Bi-polar junction transistors (BJT PNP/NPN), BiCMOS, CMOS, etc., may be used without departing from the scope of the disclosure.

[00115] Fig. 14 illustrates a block diagram of an embodiment of a mobile device in which flat surface interface connectors could be used. In some embodiments, computing device 1600 represents a mobile computing device, such as a computing tablet, a mobile phone or smart-phone, a wireless-enabled e-reader, or other wireless mobile device. It will be understood that certain components are shown generally, and not all components of such a device are shown in computing device 1600.

[00116] In some embodiments, computing device 1600 includes first processor 1610 with one or more devices according to any one of devices of Figs. 5-8, according to some embodiments discussed. Other blocks of the computing device 1600 may also include one or more devices according to any one of devices of Figs. 5-8, according to some embodiments. The various embodiments of the present disclosure may also comprise a network interface within 1670 such as a wireless interface so that a system embodiment may be incorporated into a wireless device, for example, cell phone or personal digital assistant.

[00117] In some embodiments, processor 1610 (and/or processor 1690) can include one or more physical devices, such as microprocessors, application processors,

microcontrollers, programmable logic devices, or other processing means. The processing operations performed by processor 1610 include the execution of an operating platform or operating system on which applications and/or device functions are executed. The processing operations include operations related to I/O (input/output) with a human user or with other devices, operations related to power management, and/or operations related to connecting the computing device 1600 to another device. The processing operations may also include operations related to audio I/O and/or display I/O.

[00118] In some embodiments, computing device 1600 includes audio subsystem 1620, which represents hardware (e.g., audio hardware and audio circuits) and software (e.g., drivers, codecs) components associated with providing audio functions to the computing device. Audio functions can include speaker and/or headphone output, as well as microphone input. Devices for such functions can be integrated into computing device 1600, or connected to the computing device 1600. In one embodiment, a user interacts with the computing device 1600 by providing audio commands that are received and processed by processor 1610. [00119] In some embodiments, computing device 1600 comprises display subsystem 1630. Display subsystem 1630 represents hardware (e.g., display devices) and software (e.g., drivers) components that provide a visual and/or tactile display for a user to interact with the computing device 1600. Display subsystem 1630 includes display interface 1632, which includes the particular screen or hardware device used to provide a display to a user. In one embodiment, display interface 1632 includes logic separate from processor 1610 to perform at least some processing related to the display. In one embodiment, display subsystem 1630 includes a touch screen (or touch pad) device that provides both output and input to a user.

[00120] In some embodiments, computing device 1600 comprises I/O controller 1640. I/O controller 1640 represents hardware devices and software components related to interaction with a user. I/O controller 1640 is operable to manage hardware that is part of audio subsystem 1620 and/or display subsystem 1630. Additionally, I/O controller 1640 illustrates a connection point for additional devices that connect to computing device 1600 through which a user might interact with the system. For example, devices that can be attached to the computing device 1600 might include microphone devices, speaker or stereo systems, video systems or other display devices, keyboard or keypad devices, or other I/O devices for use with specific applications such as card readers or other devices.

[00121] As mentioned above, I/O controller 1640 can interact with audio subsystem 1620 and/or display subsystem 1630. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the computing device 1600. Additionally, audio output can be provided instead of, or in addition to display output. In another example, if display subsystem 1630 includes a touch screen, the display device also acts as an input device, which can be at least partially managed by I/O controller 1640. There can also be additional buttons or switches on the computing device 1600 to provide I/O functions managed by I/O controller 1640.

[00122] In some embodiments, I/O controller 1640 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, or other hardware that can be included in the computing device 1600. The input can be part of direct user interaction, as well as providing environmental input to the system to influence its operations (such as filtering for noise, adjusting displays for brightness detection, applying a flash for a camera, or other features).

[00123] In some embodiments, computing device 1600 includes power management 1650 that manages battery power usage, charging of the battery, and features related to power saving operation. Memory subsystem 1660 includes memory devices for storing information in computing device 1600. Memory can include nonvolatile (state does not change if power to the memory device is interrupted) and/or volatile (state is indeterminate if power to the memory device is interrupted) memory devices. Memory subsystem 1660 can store application data, user data, music, photos, documents, or other data, as well as system data (whether long-term or temporary) related to the execution of the applications and functions of the computing device 1600.

[00124] Elements of embodiments are also provided as a machine-readable medium (e.g., memory 1660) for storing the computer-executable instructions (e.g., instructions to implement any other processes discussed herein). The machine-readable medium (e.g., memory 1660) may include, but is not limited to, flash memory, optical disks, CD-ROMs, DVD ROMs, RAMs, EPROMs, EEPROMs, magnetic or optical cards, phase change memory (PCM), or other types of machine-readable media suitable for storing electronic or computer- executable instructions. For example, embodiments of the disclosure may be downloaded as a computer program (e.g., BIOS) which may be transferred from a remote computer (e.g., a server) to a requesting computer (e.g., a client) by way of data signals via a communication link (e.g., a modem or network connection).

[00125] In some embodiments, computing device 1600 comprises connectivity 1670. Connectivity 1670 includes hardware devices (e.g., wireless and/or wired connectors and communication hardware) and software components (e.g., drivers, protocol stacks) to enable the computing device 1600 to communicate with external devices. The computing device 1600 could be separate devices, such as other computing devices, wireless access points or base stations, as well as peripherals such as headsets, printers, or other devices.

[00126] Connectivity 1670 can include multiple different types of connectivity. To generalize, the computing device 1600 is illustrated with cellular connectivity 1672 and wireless connectivity 1674. Cellular connectivity 1672 refers generally to cellular network connectivity provided by wireless carriers, such as provided via GSM (global system for mobile communications) or variations or derivatives, CDMA (code division multiple access) or variations or derivatives, TDM (time division multiplexing) or variations or derivatives, or other cellular service standards. Wireless connectivity (or wireless interface) 1674 refers to wireless connectivity that is not cellular, and can include personal area networks (such as Bluetooth, Near Field, etc.), local area networks (such as Wi-Fi), and/or wide area networks (such as WiMax), or other wireless communication.

[00127] In some embodiments, computing device 1600 comprises peripheral connections 1680. Peripheral connections 1680 include hardware interfaces and connectors, as well as software components (e.g., drivers, protocol stacks) to make peripheral connections. It will be understood that the computing device 1600 could both be a peripheral device ("to" 1682) to other computing devices, as well as have peripheral devices ("from" 1684) connected to it. The computing device 1600 commonly has a "docking" connector to connect to other computing devices for purposes such as managing (e.g., downloading and/or uploading, changing, synchronizing) content on computing device 1600. Additionally, a docking connector can allow computing device 1600 to connect to certain peripherals that allow the computing device 1600 to control content output, for example, to audiovisual or other systems.

[00128] In addition to a proprietary docking connector or other proprietary connection hardware, the computing device 1600 can make peripheral connections 1680 via common or standards-based connectors. Common types can include a Universal Serial Bus (USB) connector (which can include any of a number of different hardware interfaces), DisplayPort including MiniDisplayPort (MDP), High Definition Multimedia Interface (HDMI), Firewire, or other types.

[00129] Reference in the specification to "an embodiment," "one embodiment," "some embodiments," or "other embodiments" means that a particular feature, structure, or characteristic described in connection with the embodiments is included in at least some embodiments, but not necessarily all embodiments. The various appearances of "an embodiment," "one embodiment," or "some embodiments" are not necessarily all referring to the same embodiments. If the specification states a component, feature, structure, or characteristic "may," "might," or "could" be included, that particular component, feature, structure, or characteristic is not required to be included. If the specification or claim refers to "a" or "an" element, that does not mean there is only one of the elements. If the specification or claims refer to "an additional" element, that does not preclude there being more than one of the additional element.

[00130] Furthermore, the particular features, structures, functions, or characteristics may be combined in any suitable manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment anywhere the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[00131] While the disclosure has been described in conjunction with specific embodiments thereof, many alternatives, modifications and variations of such embodiments will be apparent to those of ordinary skill in the art in light of the foregoing description. The embodiments of the disclosure are intended to embrace all such alternatives, modifications, and variations as to fall within the broad scope of the appended claims.

[00132] In addition, well known power/ground connections to integrated circuit (IC) chips and other components may or may not be shown within the presented figures, for simplicity of illustration and discussion, and so as not to obscure the disclosure. Further, arrangements may be shown in block diagram form in order to avoid obscuring the disclosure, and also in view of the fact that specifics with respect to implementation of such block diagram arrangements are highly dependent upon the platform within which the present disclosure is to be implemented (i.e., such specifics should be well within purview of one skilled in the art). Where specific details (e.g., circuits) are set forth in order to describe example embodiments of the disclosure, it should be apparent to one skilled in the art that the disclosure can be practiced without, or with variation of, these specific details. The description is thus to be regarded as illustrative instead of limiting.

[00133] The following examples pertain to further embodiments. Specifics in the examples may be used anywhere in one or more embodiments. All optional features of the apparatus described herein may also be implemented with respect to a method or process.

[00134] Example 1. An apparatus comprising: a magnetic junction including: a stack of structures including: a first structure comprising a magnet with a first magnetization; a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with a second magnetization, wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; a fourth structure adjacent to the first structure of the magnetic junction, the fourth structure comprising a magnet doped with a material to increase resistivity of the magnet; and an interconnect adjacent to the fourth structure of the magnetic junction.

[00135] Example 2. The apparatus of example 1, wherein the fourth structure has a thickness in a range of 0.5 nm to 2 nm, and wherein the thickness extends from the interconnect towards the magnetic junction.

[00136] Example 3. The apparatus of example 1, wherein the magnet of the fourth structure comprises a ferromagnet, and wherein the material includes one or more of: Ge, Ga, Si, F, O, N, Co, Bi, or Sb.

[00137] Example 4. The apparatus of example 3, wherein the ferromagnet of the fourth structure includes one of: Co, Ni, Fe, or Heusler alloy.

[00138] Example 5. The apparatus of example 4, wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. [00139] Example 6. The apparatus of example 1, wherein the magnet of the fourth structure comprises a paramagnet, and wherein the material includes one or more of: Ge, Ga, Si, F, O, N, Co, Bi, or Sb.

[00140] Example 7. The apparatus of example 6, wherein the paramagnet of the fourth structure includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er, Eu, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V.

[00141] Example 8. The apparats according to any one of examples 1 to 5; or 6 or 7, wherein the fourth structure has a surface area equal or greater than a surface area of the first structure adjacent to the fourth structure.

[00142] Example 9. The apparatus according to any of the preceding examples, wherein the magnetic junction comprises: a fifth structure between the first and second structures, wherein the fifth structure includes one or more of: Ru, Os, Hs, or Fe.

[00143] Example 10. The apparatus according to any of the preceding examples, wherein the magnetic junction comprises a sixth structure between the second and third structures, wherein the sixth structure includes one or more of: Ru, Os, Hs, or Fe.

[00144] Example 11. The apparatus of example 1, wherein the first and/or third structures comprises a stack including a first material and a second material different from the first material.

[00145] Example 12. The apparatus of example 11, wherein the first material includes one of: Co, Ni, Fe, or Heusler alloy, and wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V, and wherein the second material includes one of: Pt, Pd, Ir, Ru, or Ni.

[00146] Example 13. The apparatus of example 11, wherein the first material has a thickness in a range of 0.6 nm to 2 nm, and wherein the second material has a thickness in a range of 0.1 nm to 3 nm.

[00147] Example 14. The apparatus of example 1, wherein the dielectric comprises: Mg and O.

[00148] Example 15. The apparatus of example 1, wherein the first and/or the third structures comprises a super lattice including a first material and a second material, wherein the first material includes one of: Co, Ni, Fe, or Heusler alloy; and wherein the second material includes one of: Pt, Pd, Ir, Ru, or Ni.

[00149] Example 16. The apparatus of example 1, wherein the first and/or third structures comprises a stack of three materials including a first material adjacent to the interconnect, a second material adjacent to the first material but not in contact with the interconnect, and third material adjacent to the second material and the second structure, wherein the first material includes one or more of: Co, Ni, Fe, or Heusler alloy, wherein the second material comprises Ru; and wherein the third material includes one or more of Co, Ni, Fe, or Heusler alloy.

[00150] Example 17. The apparatus according to any one of preceding examples, wherein the interconnect is to generate spin Hall effect (SHE).

[00151] Example 18. The apparatus according to any one of preceding examples, wherein the interconnect includes one or more or: b-Tantalum (b-Ta), Ta, b-Tungsten (b-W), W, Platinum (Pt), Copper (Cu) doped with elements including on of Iridium, Bismuth or elements of 3d, 4d, 5d and 4f, 5f periodic groups, Ti, S, W, Mo, Se, B, Sb, Re, La, C, P, La, As, Sc, O, Bi, Ga, Al, Y, In, Ce, Pr, Nd, F, Ir, Mn, Pd, or Fe.

[00152] Example 19. The apparatus according to any one of preceding examples, wherein the interconnect comprises a spin orbit material which includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material.

[00153] Example 20. The apparatus according to any one of preceding examples, wherein the interconnect comprises a spin orbit material which includes materials that exhibit Rashba-Bychkov effect.

[00154] Example 21. The apparatus according to any one of preceding examples, wherein the magnetic junction is one of a spin valve or a magnetic tunneling junction (MTJ).

[00155] Example 22. The apparatus according to any one of preceding examples, wherein the magnet of the first structure is a paramagnet which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er, Eu, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V, or wherein the magnet of the first structure is a paramagnet which comprises dopants which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[00156] Example 23. The apparatus of example 1, wherein the magnet of the first structure has unfixed perpendicular magnetic anisotropy (PMA) with reference to a plane of a device, wherein the magnet of the third structure has fixed PMA with reference to the plane of the device, and wherein the first and second magnetizations are substantially perpendicular to the plane of the device.

[00157] Example 24. The apparatus of example 1, wherein the magnet of the first structure has unfixed in-plane magnetic anisotropy with reference to a plane of a device, wherein the magnet of the third structure has fixed in-plane magnetic anisotropy with reference to the plane of the device, and wherein the first and second magnetizations are substantially along the plane of the device. [00158] Example 25. A system comprising: a memory; a processor coupled to the memory, the processor having a spin wave switch, which comprises an apparatus according to any one of apparatus examples 1 to 24; and a wireless interface to allow the processor to communicate with another device.

[00159] Example 26. An apparatus comprising: a magnetic junction; a structure adjacent to the magnetic junction, the structure comprising a magnet doped with a material to increase resistivity of a magnet of the magnetic junction; and an interconnect adjacent to the structure, wherein the interconnect comprises a spin orbit material.

[00160] Example 27. The apparatus of example 26, wherein the magnetic junction comprises a stack of structures including: a first structure comprising a magnet with a first magnetization; a second structure comprising one of a dielectric or metal; and a third structure comprising a magnet with a second magnetization, wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; wherein the structure adjacent to the magnetic junction is the fourth structure, and wherein the apparatus is according to any one of examples 2 to 23.

[00161] Example 28. A method comprising: forming a magnetic junction including: forming a stack of structures including: forming a first structure comprising a magnet with a first magnetization; forming a second structure comprising one of a dielectric or metal; and forming a third structure comprising a magnet with a second magnetization, wherein the third structure is adjacent to the second structure such that the second structure is between the first and third structures; forming a fourth structure adjacent to the first structure of the magnetic junction, wherein forming the fourth structure comprises forming a magnet doped with a material to increase resistivity of the magnet; and forming an interconnect adjacent to the fourth structure of the magnetic junction.

[00162] Example 29. The method of example 28, wherein the fourth structure has a thickness in a range of 0.5 nm to 2 nm, and wherein the thickness extends from the interconnect towards the magnetic junction.

[00163] Example 30. The method of example 28, wherein forming the magnet of the fourth structure comprises forming a ferromagnet, and wherein the material includes one or more of: Ge, Ga or Si.

[00164] Example 31. The method of example 30, wherein the ferromagnet of the fourth structure includes one of: Co, Ni, Fe, or Heusler alloy.

[00165] Example 32. The method of example 31, wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V. [00166] Example 33. The method of example 28, wherein forming the magnet of the fourth structure comprises forming a paramagnet, and wherein the material includes one or more of: Ge, Ga or Si.

[00167] Example 34. The method of example 33, wherein the paramagnet of the fourth structure includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er,

Eu, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V.

[00168] Example 35. The method according to any one of examples 28 to 32; or 33 or 34, wherein the fourth structure has a surface area equal or greater than a surface area of the first structure adjacent to the fourth structure.

[00169] Example 36. The method according to any of the preceding examples, wherein forming the magnetic junction comprises: forming a fifth structure between the first and second structures, wherein the fifth structure includes one or more of: Ru, Os, Hs, or Fe.

[00170] Example 37. The method according to any of the preceding method examples, wherein forming the magnetic junction comprises forming a sixth structure between the second and third structures, wherein the sixth structure includes one or more of: Ru, Os, Hs, or Fe.

[00171] Example 38. The method of example 28, wherein forming the first and/or third structures comprises forming a stack including a first material and a second material different from the first material.

[00172] Example 39. The method of example 38, wherein the first material includes one of: Co, Ni, Fe, or Heusler alloy, and wherein the Heusler alloy includes one or more of Co, Cu, Fe, Ga, Ge, In, Mn, Al, In, Sb, Si, Sn, Ni, Pd, Ru, or V, and wherein the second material includes one of: Pt, Pd, Ir, Ru, or Ni.

[00173] Example 40. The method of example 38, wherein the first material has a thickness in a range of 0.6 nm to 2 nm, and wherein the second material has a thickness in a range of 0.1 nm to 3 nm.

[00174] Example 41. The method of example 28, wherein the dielectric comprises:

Mg and O.

[00175] Example 42. The method of example 28, wherein forming the first and/or the third structures comprises forming super lattice including a first material and a second material, wherein the first material includes one of: Co, Ni, Fe, or Heusler alloy; and wherein the second material includes one of: Pt, Pd, Ir, Ru, or Ni.

[00176] Example 43. The method of example 28, wherein forming the first and/or third structures comprises: forming a stack of three materials including a first material adjacent to the interconnect; forming a second material adjacent to the first material but not in contact with the interconnect; and forming a third material adjacent to the second material and the second structure, wherein the first material includes one or more of: Co, Ni, Fe, or Heusler alloy, wherein the second material comprises Ru; and wherein the third material includes one or more of Co, Ni, Fe, or Heusler alloy.

[00177] Example 44. The method according to any one of preceding method examples, wherein the interconnect is to generate spin Hall effect (SHE).

[00178] Example 45. The method according to any one of preceding method examples, wherein the interconnect includes one or more or: b-Tantalum (b-Ta), Ta, b- Tungsten (b-W), W, Platinum (Pt), Copper (Cu) doped with elements including on of Iridium, Bismuth or elements of 3d, 4d, 5d and 4f, 5f periodic groups, Ti, S, W, Mo, Se, B,

Sb, Re, La, C, P, La, As, Sc, O, Bi, Ga, Al, Y, In, Ce, Pr, Nd, F, Ir, Mn, Pd, or Fe.

[00179] Example 46. The method according to any one of preceding method examples, wherein forming the interconnect comprises forming a spin orbit material which includes one of a 2D material or a 3D material, wherein the 3D material is thinner than the 2D material.

[00180] Example 47. The method according to any one of preceding method examples, wherein forming the interconnect comprises forming a spin orbit material which includes materials that exhibit Rashba-Bychkov effect.

[00181] Example 48. The method according to any one of preceding method examples, wherein forming the magnetic junction comprises forming one of a spin valve or a magnetic tunneling junction (MTJ).

[00182] Example 49. The method according to any one of preceding method examples, wherein the magnet of the first structure is a paramagnet which includes one or more of: Pt, Pd, W, Ce, Al, Li, Mg, Na, Cr, Co, Dy, O, Er, Eu, Eu, Gd, Fe, Nd, K, Pr, Sm, Tb, Tm, or V, or wherein the magnet of the first structure is a paramagnet which comprises dopants which include one or more of: Ce, Cr, Mn, Nb, Mo, Tc, Re, Nd, Gd, Tb, Dy, Ho, Er, Tm, or Yb.

[00183] Example 50. The method of example 28, wherein the magnet of the first structure has unfixed perpendicular magnetic anisotropy (PMA), wherein the first structure has an anisotropy axis perpendicular to a plane of a device, wherein the magnet of the third structure has fixed PMA, wherein the third structure has an anisotropy axis perpendicular to the plane of the device, and wherein the first and second magnetizations are substantially perpendicular to the plane of the device. [00184] Example 51. The method of example 28, wherein the magnet of the first structure has unfixed in-plane magnetic anisotropy, wherein the first structure has an anisotropy axis along a plane of a device, wherein the magnet of the third structure has fixed in-plane magnetic anisotropy, wherein the third structure has an anisotropy axis along the plane of the device, and wherein the first and second magnetizations are substantially along a plane of the device.

[00185] An abstract is provided that will allow the reader to ascertain the nature and gist of the technical disclosure. The abstract is submitted with the understanding that it will not be used to limit the scope or meaning of the claims. The following claims are hereby incorporated into the detailed description, with each claim standing on its own as a separate embodiment.