BACKGROUND OF THE INVENTION

Embodiments of the present description generally relate to the field of microelectronic devices, and, more particularly, to spin transfer torque memory devices.

BACKGROUND

Higher performance, lower cost, increased miniaturization of integrated circuit components, and greater packaging density of integrated circuits are ongoing goals of the microelectronic industry for the fabrication of microelectronic logic and memory devices. Spin devices, such as spin logic and spin memory, can enable a new class of logic and architectures for microelectronic components. Thus, there is an ongoing drive to improve the design and efficiency of these spin devices.

BRIEF DESCRIPTION OF THE DRAWINGS

The subject matter of the present disclosure is particularly pointed out and distinctly claimed in the concluding portion of the specification. The foregoing and other features of the present disclosure will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings. It is understood that the accompanying drawings depict only several embodiments in accordance with the present disclosure and are, therefore, not to be considered limiting of its scope. The disclosure will be described with additional specificity and detail through use of the accompanying drawings, such that the advantages of the present disclosure can be more readily ascertained, in which:

FIG. 1 is a schematic diagram illustrating a spin transfer torque memory device.

FIG. 2a is a side view schematic illustrating a magnetic tunnel junction with a free magnetic layer having a magnetic orientation anti-parallel to a fixed magnetic layer in accordance with an embodiment of the present description. FIG. 2b is a side view schematic illustrating a magnetic tunnel junction with a free magnetic layer having a magnetic orientation parallel to a fixed magnetic layer in accordance with an embodiment of the present description.

FIG. 3 is a schematic diagram illustrating a spin transfer torque memory device having a spin transfer torque element coupled to a PMOS transistor in accordance with an embodiment of the present description.

FIG. 4 is a flow diagram of a process of fabricating a microelectronic device in accordance with an embodiment of the present description.

FIG. 5 illustrates a computing device in accordance with one implementation of the present description.

DETAILED DESCRIPTION

In the following detailed description, reference is made to the accompanying drawings that show, by way of illustration, specific embodiments in which the claimed subject matter may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the subject matter. It is to be understood that the various embodiments, although different, are not necessarily mutually exclusive. For example, a particular feature, structure, or characteristic described herein, in connection with one embodiment, may be implemented within other embodiments without departing from the spirit and scope of the claimed subject matter. References within this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation encompassed within the present description. Therefore, the use of the phrase "one embodiment" or "in an embodiment" does not necessarily refer to the same embodiment. In addition, it is to be understood that the location or arrangement of individual elements within each disclosed embodiment may be modified without departing from the spirit and scope of the claimed subject matter. The following detailed description is, therefore, not to be taken in a limiting sense, and the scope of the subject matter is defined only by the appended claims, appropriately interpreted, along with the full range of equivalents to which the appended claims are entitled. In the drawings, like numerals refer to the same or similar elements or functionality throughout the several views, and that elements depicted therein are not necessarily to scale with one another, rather individual elements may be enlarged or reduced in order to more easily comprehend the elements in the context of the present description.

The terms "over", "to", "between" and "on" as used herein may refer to a relative position of one layer with respect to other layers. One layer "over" or "on" another layer or bonded "to" another layer may be directly in contact with the other layer or may have one or more intervening layers. One layer "between" layers may be directly in contact with the layers or may have one or more intervening layers.

Embodiments of the present description relate to the fabrication of spin transfer torque memory devices, wherein a spin transfer torque element is connected to a PMOS transistor. In one embodiment, the spin transfer torque element may have a fixed side and a free side with a tunnel barrier layer disposed between the fixed side and the free side, and the PMOS transistor may have a drain structure which is electrically connected to the fixed side of the spin transfer torque element.

FIG. 1 shows a schematic of a microelectronic device illustrated as a spin transfer torque memory cell 100 which includes a spin transfer torque element 110 connected to an NMOS transistor 180. The spin transfer torque element 110 may comprise a top cap/contact or free magnetic layer electrode 120 with a free magnetic layer 130 adjacent the free magnetic layer electrode 120, a bottom cap or fixed magnetic layer electrode 160 adjacent a pinned or fixed magnetic layer 150, and a tunnel barrier layer 140 disposed between and abutting the free magnetic layer 130 and the fixed magnetic layer 150. A dielectric material 145 may be formed adjacent the fixed magnetic layer electrode 160, the fixed magnetic layer 150, and the tunnel barrier layer 140. The free magnetic layer electrode 120 may be electrically connected to a bit line 182. The fixed magnetic layer electrode 160 may be connected to the NMOS transistor 180. The NMOS transistor 180 may be connected to a word line 184 and a signal line 186 in a manner that will be understood to those skilled in the art. The spin transfer torque memory cell 100 may further include additional read and write circuitry (not shown), a sense amplifier (not shown), a bit line reference (not shown), and the like, as will be understood by those skilled in the art, for the operation of the spin transfer torque memory cell 100. It is understood that a plurality of the spin transfer torque memory cells 100 may be operably connected to one another to form a memory array (not shown), wherein the memory array can be incorporated into a non-volatile memory device. The portion of the spin transfer torque element 110 comprising the free magnetic layer 130, the tunnel barrier layer 140, and the fixed magnetic layer 150 is known as a magnetic tunnel junction 170.

Referring to FIGs. 2a and 2b, the magnetic tunnel junction 170 functions essentially as a resistor, where the resistance of an electrical path through the magnetic tunnel junction 170 may exist in two resistive states, either "high" or "low", depending on the direction or orientation of magnetization in the free magnetic layer 130 and in the fixed magnetic layer 150. FIG. 2a illustrates a high resistive state, wherein direction of magnetization in the free magnetic layer 130 and the fixed magnetic layer 150 are substantially opposed or anti- parallel with one another. This is illustrated with arrows 172 in the free magnetic layer 130 pointing downward and with arrows 174 in the fixed magnetic layer 150 aligned in opposition pointing upward. FIG. 2b illustrates a low resistive state, wherein direction of magnetization in the free magnetic layer 130 and the fixed magnetic layer 150 are

substantially aligned or parallel with one another. This is illustrated with arrows 172 in the free magnetic layer 130 and with arrows 174 in the fixed magnetic layer 150 aligned the same direction pointing from upward.

It is understood that the terms "low" and "high" with regard to the resistive state of the magnetic tunnel junction 170 are relative to one another. In other words, the high resistive state is merely a detectibly higher resistance than the low resistive state, and vice versa. Thus, with a detectible difference in resistance, the low and high resistive states can represent different bits of information (i.e. a "0" or a "1").

The direction of magnetization in the free magnetic layer 130 may be switched by the transistor 180 through a process call spin transfer torque ("STT") using a spin-polarized current. An electrical current is generally unpolarized (e.g. consisting of about 50% spin-up and about 50% spin-down electrons). A spin polarized current is one with a great number of electrons of either spin-up or spin-down, which may be generated by passing a current through the fixed magnetic layer 150. The electrons of the spin polarized current from the fixed magnetic layer 150 tunnel through the tunnel barrier layer 140 and transfers its spin angular momentum to the free magnetic layer 130, wherein to free magnetic layer 130 will orient its magnetic direction from anti -parallel, as shown in FIG. 2a, to that of the fixed magnetic layer 150 or parallel, as shown in FIG. 2b. The free magnetic layer 130 may be returned to its origin orientation, shown in FIG. 2a, by reversing the current.

Thus, the magnetic tunnel junction 170 may store a single bit of information ("0" or "1") by its state of magnetization. The information stored in the magnetic tunnel

junction 170 is sensed by driving a current through the magnetic tunnel junction 170. The free magnetic layer 130 does not require power to retain its magnetic orientations; thus, the state of the magnetic tunnel junction 170 is preserved when power to the device is removed. Therefore, the spin transfer torque memory device 100 (see FIG. 1) is non-volatile.

In the spin transfer torque memory cell 100 of FIG. 1, a source structure 192 of the NMOS transistor 180 may be electrically connected to the fixed magnetic layer

electrode 160, a drain structure 194 of the NMOS transistor 180 may be electrically connected to the signal line 186, and the free magnetic layer electrode 120 may be electrically connected to the bit line 182. However, although NMOS transistors 180 are used due to their high speed operation, it has been found that this configuration can result in source

degeneration for parallel to antiparallel switching in the magnetic tunnel junction 170, which can degrade the performance of the magnetic tunnel junction 170.

As will be understood to those skilled in the art, the parallel to antiparallel write current is generally higher than antiparallel to parallel in magnetic tunnel junctions 170 and source degeneration is detrimental because it degrades write current. Thus, since parallel to antiparallel write current is high, there is a doubly detrimental effect, as a degraded current occurs in the situation where the switching current requirements are higher. As previously mentioned, this source degeneration is a problem for a magnetic tunnel junctions 170 having the fixed magnetic layer 150 on the bottom with the NMOS transistor for parallel to antiparallel switching. One solution for this issue may be to reverse the connections, such the source structure 192 of the NMOS transistor 180 is electrically connected to the free magnetic layer electrode 120 and the bit line 182 connected to the fixed magnetic layer electronic 160. However, this solution has its drawbacks as it takes additional space for wiring and contact, which results in a larger spin transfer torque memory cell 100, as will be understood to those skilled in the art.

In one embodiment of the present description, as shown in FIG. 3, a spin transfer torque memory cell 200 may be formed by utilizing a PMOS transistor 210. For the purposes of the present description, a portion of the spin transfer torque element 1 10 on one side of the tunnel barrier layer 140 having the fixed magnetic layer 150 may be referred to as the fixed sidel I OFX and a portion of the spin transfer torque element 1 10 on the other side of the tunnel barrier layer 140 having the free magnetic layer 130 may be referred to as the free side 1 10 _F R.

As further shown in FIG. 3, the fixed side 1 10 _F x of the spin transfer torque

element 1 10 may be electrically connected to a drain structure 212 of the PMOS

transistor 210, a source structure 214 of the PMOS transistor 210 may be electrically connected to the signal line 186, and a gate electrode 216 of the PMOS transistor 210 may be electrically connected to the word line 184. The free side 1 10 _F R of the spin transfer torque element 1 10 may be electrically connected to the bit line 182.

As will be understood to those skilled in the art, the use of the PMOS transistor 210 electrically connected to the fixed side 1 10 _F x of the spin transfer torque element 1 10 results in the parallel to antiparallel switching occurring when the current flows from the source structure 214 to the drain structure 212. In other words, the spin transfer torque element 1 10 is on the drain side for parallel to antiparallel switching, which avoids source degeneration, as previously discussed. As shown, using a PMOS transistor 210 allows for attached to the magnetic tunnel junction 170 with the fixed side 1 10 _FX at the bottom. This is advantageous because the magnetic tunnel junction 170 having its fixed side 1 10 _FX at the bottom have traditionally given the best performance results for magnetic tunnel junctions 170. Thus, the PMOS transistor 210 allows one to retain the performance benefits of having the magnetic tunnel junction 170 with its fixed side 1 10 _FX at the bottom, without introducing source degeneration of parallel to antiparallel switching which occurs with the used of an MOS transistor (absent complex wiring, as discussed above).

In one embodiment of the magnetic tunnel junction 170, as shown in FIG. 3, the free magnetic layer 130 and the fixed magnetic layer 150 may comprise a ferromagnetic layer, such as a cobalt/iron/boron (CoFeB) alloy, and the tunnel barrier layer 140 may comprise an insulative oxide layer, such as magnesium oxide (MgO). An antiferromagnetic layer 155 may be formed between the CoFeB fixed magnetic layer 150 and the fixed magnetic layer electrode 160 to fix or "pin" the CoFeB fixed magnetic layer 150, as will be understood to those skilled in the art. Thus, when the CoFeB free magnetic layer 130 and the CoFeB fixed magnetic layer 150 are magnetically polarized in the same direction, the spins conduct through the insulative MgO tunnel barrier layer 140. It is understood that other layers could be incorporated into the magnetic tunnel junction 170, such as an antiferromagnetic layer between the CoFeB fixed magnetic layer 150 and the fixed magnetic layer electrode 160. When the CoFeB free magnetic layer 130 and the CoFeB fixed magnetic layer 150 are magnetically polarized in opposite directions, the insulative MgO tunnel barrier layer 140 acts so as to block the spin-down minority carriers, and the resistance of the magnetic tunnel junction 170 increases, as will be understood to those skilled in the art.

Although the precise methods of fabricating the spin transfer torque memory cell 200 of FIG. 3 has not been described herein, it is understood that the steps for fabrication may include standard microelectronic fabrication processes such as lithography, etch, thin films deposition, planarization (such as chemical mechanical polishing (CMP)), diffusion, metrology, the use of sacrificial layers, the use of etch stop layers, the use of planarization stop layers, and/or any other associated action with microelectronic component fabrication.

FIG. 4 is a flow chart of a process 300 of fabricating a microelectronic device according to an embodiment of the present description. As set forth in block 302, a spin transfer torque element may be formed by forming a fixed side, forming a free side, and forming a tunnel barrier layer between the fixed side and the free side. A PMOS transistor may be formed having a drain structure, as set forth in block 304. As set forth in block 306, the drain structure of the PMOS transistor may be electrically connected to the fixed side of the spin transfer torque element.

FIG. 5 illustrates a computing device 400 in accordance with one implementation of the present description. The computing device 400 houses a board 402. The board 402 may include a number of components, including but not limited to a processor 404, at least one communication chip 406A, 406B, volatile memory 408, (e.g., DRAM), non-volatile memory 410 (e.g., ROM), flash memory 412, a graphics processor or CPU 414, a digital signal processor (not shown), a crypto processor (not shown), a chipset 416, an antenna, a display (touchscreen display), a touchscreen controller, a battery, an audio codec (not shown), a video codec (not shown), a power amplifier (AMP), a global positioning system (GPS) device, a compass, an accelerometer (not shown), a gyroscope (not shown), a speaker (not shown), a camera, and a mass storage device (not shown) (such as hard disk drive, compact disk (CD), digital versatile disk (DVD), and so forth). Any of the microelectronic components may be physically and electrically coupled to the board 402. In some implementations, at least one of the microelectronic components may be a part of the processor 404.

The communication chip(s) 406A, 406B enable wireless communications for the transfer of data to and from the computing device 400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that may communicate data through the use of modulated electromagnetic radiation through a non-solid medium. The term does not imply that the associated devices do not contain any wires, although in some embodiments they might not. The communication chip(s) 406 A, 406B may implement any of a number of wireless standards or protocols, including but not limited to Wi-Fi (IEEE 802.11 family), WiMAX (IEEE 802.16 family), IEEE 802.20, long term evolution (LTE), Ev-DO, HSPA+, HSDPA+, HSUPA+, EDGE, GSM, GPRS, CDMA, TDMA, DECT, Bluetooth, derivatives thereof, as well as any other wireless protocols that are designated as 3G, 4G, 5G, and beyond. The computing device 400 may include a plurality of communication chips 406A, 406B. For instance, a first communication chip 406A may be dedicated to shorter range wireless communications such as Wi-Fi and Bluetooth and a second communication chip 406B may be dedicated to longer range wireless communications such as GPS, EDGE, GPRS, CDMA, WiMAX, LTE, Ev-DO, and others.

The term "processor" may refer to any device or portion of a device that processes electronic data from registers and/or memory to transform that electronic data into other electronic data that may be stored in registers and/or memory.

Any of the microelectronic components within the computing device 400 may include a spin transfer torque memory cell comprising a spin transfer torque element having a fixed side and a free side with a tunnel barrier layer disposed between the fixed side and the free side and a PMOS transistor having a drain structure electrically connected to the fixed side of the spin transfer torque element, as described above.

In various implementations, the computing device 400 may be a laptop, a netbook, a notebook, an ultrabook, a smartphone, a tablet, a personal digital assistant (PDA), an ultra mobile PC, a mobile phone, a desktop computer, a server, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a digital camera, a portable music player, or a digital video recorder. In further implementations, the computing device 400 may be any other electronic device that processes data.

It is understood that the subject matter of the present description is not necessarily limited to specific applications illustrated in the figures. The subject matter may be applied to other microelectronic device and assembly applications, as well as any appropriate transistor application, as will be understood to those skilled in the art.

The following examples pertain to further embodiments, wherein Example 1 is a microelectronic device, comprising a spin transfer torque element having a fixed side and a free side with a tunnel barrier layer disposed between the fixed side and the free side, and a PMOS transistor having a drain structure electrically connected to the fixed side of the spin transfer torque element.

In Example 2, the subject matter of Example 1 can optionally include the free side of the spin transfer torque element electrically connected to a bit line.

In Example 3, the subject matter of Example 1 can optionally include the PMOS transistor having a source structure electrically connected to a source line and having a gate electrode electrically connected to a word line.

In Example 4, the subject matter of any of Examples 1 to 3 can optionally include the free side of the spin transfer torque element comprising a free magnetic layer abutting the tunnel barrier layer, and the fixed side of the spin transfer torque element comprising a fixed magnet layer abutting the tunnel barrier layer and an antiferromagnetic layer abutting the fixed magnet layer.

In Example 5, the subject matter of Example 4 can optionally include at least one of the free magnetic layer and the fixed magnetic layer comprising a ferromagnetic layer.

In Example 6, the subject matter of Example 5 can optionally include the

ferromagnetic layer comprising a cobalt/iron/boron alloy.

In Example 7, the subject matter of Example 4 can optionally include the tunnel barrier layer comprising an insulative oxide layer.

In Example 8, the subject matter of Example 7 can optionally include the insulative oxide layer comprising magnesium oxide.

The following examples pertain to further embodiments, wherein Example 9 is a method of forming a microelectronic device, comprising forming a spin transfer torque element comprising forming a fixed side, forming a free side, and forming a tunnel barrier layer between the fixed side and the free side; forming a PMOS transistor having a drain structure; and electrically connecting the drain structure of the PMOS transistor to the fixed side of the spin transfer torque element.

In Example 10, the subject matter of Example 9 can optionally include electrically connecting the free side of the spin transfer torque element to a bit line.

In Example 11, the subject matter of Example 9 can optionally include forming the PMOS transistor having a source structure comprises forming the PMOS transistor having the source structure, a drain structure, and a gate electrode, and further comprising electrically connecting the drain structure to a source line; and electrically connecting the gate electrode to a word line.

In Example 12, the subject matter of any of Examples 9 to 11 can optionally include forming the spin transfer torque element comprising forming the fixed side comprises forming an antiferromagnetic layer and forming a fixed magnet layer abutting the

antiferromagnetic layer; forming the tunnel barrier layer abutting the antiferromagnetic layer; and forming the free side comprising forming a free magnetic layer abutting the tunnel barrier layer.

In Example 13, the subject matter of Example 12 can optionally include forming at least one of the free magnetic layer and the fixed magnetic layer comprising forming a ferromagnetic layer.

In Example 14, the subject matter of Example 13 can optionally include forming the ferromagnetic layer comprising forming a cobalt/iron/boron alloy free magnetic layer.

In Example 15, the subject matter of Example 12, wherein forming the tunnel barrier layer comprises forming an insulative oxide tunnel barrier layer.

In Example 16, the subject matter of Example 15 can optionally include forming the insulative oxide tunnel barrier layer comprising forming a magnesium oxide tunnel barrier layer.

The following examples pertain to further embodiments, wherein Example 17 is an electronic system, comprising a board; and a microelectronic device attached to the board, wherein the microelectronic device includes a spin transfer torque element having a fixed side and a free side with a tunnel barrier layer disposed between the fixed side and the free side, and a PMOS transistor having a drain structure electrically connected to the fixed side of the spin transfer torque element.

In Example 18, the subject matter of Example 17 can optionally include the free side of the spin transfer torque element electrically connected to a bit line.

In Example 19, the subject matter of Example 17 can optionally include the PMOS transistor having a source structure electrically connected to a source line and having a gate electrode electrically connected to a word line.

In Example 20, the subject matter of any of Examples 17 to 19 can optionally include the free side of the spin transfer torque element comprising a free magnetic layer abutting the tunnel barrier layer, and the fixed side of the spin transfer torque element comprising a fixed magnet layer abutting the tunnel barrier layer and an antiferromagnetic layer abutting the fixed magnet layer.

In Example 21, the subject matter of Example 20 can optionally include at least one of the free magnetic layer and the fixed magnetic layer comprising a ferromagnetic layer.

In Example 22, the subject matter of Example 21 can optionally include the ferromagnetic layer comprising a cobalt/iron/boron alloy.

In Example 23, the subject matter of Example 20 can optionally include the tunnel barrier layer comprising an insulative oxide layer.

In Example 24, the subject matter of Example 23 can optionally include the insulative oxide layer comprising magnesium oxide layer.

Having thus described in detail embodiments of the present description, it is understood that the present description defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.