Title:
SRAM CIRCUIT AND BUFFER CIRCUIT USING SAME
Document Type and Number:
WIPO Patent Application WO/2007/074517
Kind Code:
A1
Abstract:
A SRAM circuit comprises: a plurality of memory cells each comprising a pair of
storage portions; a plurality of write word lines for specifying the rows of the
memory cells; a plurality of read word line pairs for specifying the rows of the
memory cells; a write row decoder for driving the write word lines common to the
pair of storage portions when writing into the pair of storage portions; a read
row decoder for driving the read word lines connected to the storage portions
when reading from the storage portions; a plurality of write bit line pairs for
specifying the pair of storage portions when writing into the pair of storage
portions, and writing data inputted to each of the pair of storage portions into
both of the pair of storage portions jointly specified together with the write
word lines; and read bit lines (or a read bit line) for specifying the storage portions
when reading from the storage portions and reading data from the storage portions
jointly specified together with the read word lines.
Inventors:
KANARI KATSUNAO (JP)
Application Number:
PCT/JP2005/023917
Publication Date:
July 05, 2007
Filing Date:
December 27, 2005
Export Citation:
Assignee:
FUJITSU LTD (JP)
KANARI KATSUNAO (JP)
KANARI KATSUNAO (JP)
International Classes:
G11C11/41
Foreign References:
| JPH11261017A | 1999-09-24 | |||
| JPH0464990A | 1992-02-28 |
Other References:
NIEL H. EL WESTE; KAMRAN ESHRAGHI, PRINCIPLE OF CMOS VLSI DESIGN FROM A SYSTEM POINT OF VIEW, 1988, pages 310
Attorney, Agent or Firm:
HAYASHI, Tsunenori et al. (Doi & Associates 3rd Floor, Toshou-Bldg. No.3, 3-9-5, Shin-yokohama, Kohoku-k, Yokohama-shi Kanagawa 33, JP)
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