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Title:
SRAM MEMORY UNIT
Document Type and Number:
WIPO Patent Application WO/2017/144887
Kind Code:
A1
Abstract:
There is provided a SRAM memory unit comprising a SRAM memory cell, the memory cell being operatively connected to one or more bit lines, and wherein access for the one or more bit lines to the memory cell during a write operation is controlled by a word line. The memory cell further comprises a positive supply rail for supplying a positive voltage to the memory cell, wherein the positive supply rail is connected to a positive voltage source via a supply switch. The supply switch is provided by a PMOS transistor with a gate of the PMOS transistor being connected to the word line such that the positive supply rail is disconnected from the positive voltage source during a write operation.

Inventors:
MONK TREVOR KENNETH (GB)
Application Number:
PCT/GB2017/050475
Publication Date:
August 31, 2017
Filing Date:
February 23, 2017
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
SURECORE LTD (GB)
International Classes:
G11C11/418; G11C11/419
Foreign References:
US20150029782A12015-01-29
US20140313817A12014-10-23
US20120195111A12012-08-02
US20150109852A12015-04-23
US20070030741A12007-02-08
Other References:
None
Attorney, Agent or Firm:
CHAPMAN, Alan (GB)
Download PDF:
Claims:
CLAIMS

1. A memory unit comprising:

a memory cell, the memory cell being operatively connected to one or more bit lines, and wherein access for the one or more bit lines to the memory cell during a 5 write operation is controlled by a word line;

wherein the memory cell comprises a positive supply rail for supplying a positive voltage to the memory cell;

wherein the positive supply rail is connected to a positive voltage source via a supply switch, the supply switch being provided by a PMOS transistor with a gate of i o the PMOS transistor being connected to the associated word line such that the positive supply rail is disconnected from the positive voltage source during a write operation.

2. The memory unit of claim 1 , wherein each of the plurality of memory cells has at least one dedicated read port such that access to the memory cell during a read operation is

15 controlled by a read word line, the read word line being distinct from the word line that controls access to the memory cell during a write operation.

3. The memory unit of claim 2, wherein each dedicated read port comprises a single-ended read port.

20

4. The memory unit of claim 3, wherein each dedicated read port comprises a data read transistor (MDR) connected to a storage node of the memory cell and a read access transistor (MAR) that is controlled by the read word line.

25 5. The memory unit of claim 2, wherein each dedicated read port comprises a differential/double-ended read port.

6. The memory unit of claim 5, wherein each dedicated read port comprises a first read access transistor (MAR1) operatively connecting a first storage node (N1) of the memory

30 cell to a first (RBLA) of a pair of complimentary read bit lines, and a second read access transistor (MAR2) operatively connecting a second storage node (N2) of the memory cell to a second (RBLB) of the pair of complimentary read bit lines.

7. The memory unit of any preceding claim, wherein each of the plurality of memory cells 35 comprises a pair of cross-coupled inverters having respective first and second storage access nodes, a first access transistor operatively connected to said first storage node, a second access transistor operatively connected to said second storage node, and the word line is connected to a gate on said first access transistor and a gate on said second access transistor for controlling said first access transistor and said second access 5 transistor.

8. The memory unit of claim 7, wherein the positive supply rail is connected to pull-up devices within the cross-coupled inverters. i o 9. The memory unit of claim 8, wherein the pull-up devices within the cross-coupled inverters are PMOS transistors and the positive supply rail is connected to a source of each PMOS transistor pull-up device.

10. The memory unit of any preceding claim, wherein the memory unit comprises a plurality 15 of memory cells, each of the plurality of memory cells sharing a positive supply rail, and wherein access to each of the plurality of memory cells during a write operation is controlled by the word line.

1 1. The memory unit of claim 10, wherein the supply switch is connected to the word line at a 20 location adjacent to an end of the word line.

12. The memory unit of any of claims 10 or 1 1 , wherein the memory unit comprises a further plurality of memory cells, each of the further plurality of memory cells sharing a further positive supply rail, and wherein access to each of the further plurality of memory cells

25 during a write operation is controlled by the word line.

13. The memory unit of claim 12, wherein the further positive supply rail is connected to a positive voltage source via a further supply switch.

30 14. The memory unit of claim 13, wherein the supply switch is connected to the word line at a location adjacent to an end of the word line and wherein the further supply switch is connected to the word line at a location adjacent to an opposite end of the word line.

15. The memory unit according to any preceding claim, wherein the memory unit further

35 comprises a dummy memory cell connected to the positive supply rail, the dummy memory cell comprising access transistors that are controlled by the word line and wherein the dummy memory cell is configured to change state when the word line is driven high.

Description:
SRAM MEMORY UNIT

Technical Field

The present invention relates to memory units providing digital data storage. In particular, the present invention provides an improved memory unit that can implement write-assist whilst minimising reliability and data retention concerns and without consuming too much additional area.

Background

Data storage is an essential requirement for virtually all modern digital electronic systems. Static read/write memory (SRAM) comprises a major part of that function, being relatively easy to integrate into a semiconductor device together with large amounts of logic, thus offering fast access and low power. With the advent of deep sub-micron (DSM) geometry silicon processing, the task of implementing reliable storage whilst simultaneously maintaining low power consumption becomes increasingly problematic, whilst conversely demand rises with the proliferation of battery-powered electronic gadgets requiring progressively larger memories.

The most commonly-used design of SRAM memory cell is the 6-transistor circuit shown in Figure 1 and consists of a storage element made up of two back- to-back/cross-coupled inverters ([MN1 , MP1] and [MN2, MP2]) 1 1a, 1 1 b, 12a, 12b with access transistors (MA 1 and MA2) 16a, 16b which are turned ON by means of a word line control (WL) to form a conducting path between the data storage nodes (N1 and N2) 13, 14 of the cell and the complementary bit lines (BLA and BLB).

A block of memory constructed from conventional 6-transistor memory cells is shown in Figure 2. The block illustrated in Figure 2 contains an array of cells, with the word lines connected across the rows of the array and bit lines running along the columns. By convention the word lines are always said to run along the rows of an array of memory cells whilst the bit lines are always said to run down the columns of an array of memory cells, irrespective of the orientation of the array. Typically, a multiplex structure will be provided at the bottom of the array for selecting which of the columns is to be accessed (for either read or write) according to a set of column select signals which are derived from the address supplied to the memory by the user. Initially before each memory access, the bit lines for all columns are pre-charged into a high state (circuitry not shown).

A write operation, in which a data value is written to a memory cell, is achieved by forcing a high voltage onto one of BLA or BLB whilst simultaneously forcing a low voltage onto the other, and then driving the word line (WL) high to activate the access path allowing the voltage levels held on the bit lines (BLA and BLB) to overcome the state of the storage element. The word line is then driven low to disconnect the memory cell with its data store held in its new state. A read operation in which a data value stored in a memory cell is read, is achieved by initially driving both bit lines to a notionally high voltage level before then driving the word line (WL) high. One of either BLA or BLB will then be pulled low through the access devices (MA1 and MA2) by the low voltage side of the storage element. The complementary bit lines are attached to inputs of a sense amplifier (not shown) that is part of the read circuitry which is used when data is read from the memory. A sense amplifier senses the low level signals present on the bit lines which represent the data value (i.e. either a '1' or a Ό') stored in a given memory cell, and amplifies the small voltage swing to recognisable logic level so that the data can be interpreted properly by logic outside the memory. The difference in voltage levels between the two bit lines can therefore be sensed by the sense amplifier and used to determine the data value (i.e. or Ό'). The decision levels representing a and a Ό' will have been pre-determined during the circuit design phase and applied by the sense amplifier.

One crucial part of the design of the 6-transistor memory cell is the drive strength ratios of the NMOS (n-channel metal-oxide semiconductor field effect transistor) pull down transistors (MN1 and MN2), the NMOS access devices (MA1 and MA2) and the PMOS (p-channel metal-oxide semiconductor field effect transistor) pull up devices (MP1 and MP2). In particular, the access devices need to be sufficiently large relative to the pull-up devices to guarantee that the cell state is over-written during a write, but not so large (relative to the pull-down devices) that the cell becomes over-loaded and unstable during a read thereby causing the stored data value to be lost.

The act of reading a 6-transistor memory cell therefore presents its most challenging operating condition for retaining its data whilst the storage elements are loaded via the access devices (i.e. access devices turned on and both bit lines high). With the inevitable degree of random device variability suffered on DSM technologies due to the very small geometry of the individual devices, simultaneously meeting both writability and read stability criteria on all cells in a very large memory (10's of millions of bits) becomes extremely challenging.

In order to alleviate the difficulty of addressing these conflicting requirements simultaneously, an increasingly common practice is to use memory cells that have dedicated read ports, often referred to as read-decoupled memory cells, that provide a path for accessing a memory cell during a read operation that is separate to that used for write operations. Figures 3 and 4 illustrate two different examples of read-decoupled memory cells.

Figure 3 shows an 8-transistor cell design that separates out the write and read paths of the circuit by the addition a single-ended read port. The single-ended read port comprises a data read transistor (MDR) is connected to a storage node (N2) of the memory cell and a read access transistor (MAR) that is controlled by an associated read word line (RWL). The read word line (RWL) is separate/distinct from the word line (WL) that controls access to the memory cell during a write operation. The NMOS data read transistor (MDR) is configured as a pull-down transistor whose gate is connected to the storage node of the memory cell and whose source is connected to ground. The data read transistor (MDR) is connected in series with the NMOS read access transistor (MAR) whose gate is connected to the read word line (RWL) and whose drain is connected to a read bit line (RBL). The read access transistor (MAR) can thereby provide a conducting path between the data storage node (N2) of the cell and the read bit line (RBL). Write operations on this 8-transistor cell design are identical to those for the 6-transistor cell. For reads, however, instead of the write word line (WWL) being driven high, the single read bit line (RBL) is initially pre-charged to a high voltage and then the read word line (RWL) driven high. That enables the data-dependent discharge path from the read bit line (RBL) through the cell to VSS, and so the read bit line (RBL) will either stay high (due to its capacitance) or be pulled low by the cell. The state of the read bit (RBL) line can then be sensed to determine the data value stored in the selected bit. Whilst this example shows a read-decoupled memory cell comprising conventional 6-transistor cell with the addition of one single-ended read port, it is possible to include multiple single-ended read ports within a single cell.

Figure 4 shows an alternative 8-transistor cell design that separates out the write and read paths of the circuit by the addition a differential/double-ended read port. The differential/double-ended read port comprises a first read access transistor (MAR1) connecting a first storage node (N1) of the memory cell to a first (RBLA) of a pair of complimentary read bit lines, and a second read access transistor (MAR2) connecting a second storage node (N2) of the memory cell to a second (RBLB) of the pair of complimentary read bit lines. The differential/double-ended read port therefore essentially replicates the access transistors of a conventional 6-transistor cell (i.e. that control the connection of the complimentary bit lines to the storage nodes) so that there are separate yet corresponding write and read paths for the cell. As with a conventional 6-transistor cell, during a write operation, the write access transistors (MA1 and MA2) are turned on by means of a write word line to form a conducting path between the data storage nodes (N1 and N2) of the cell and the complementary bit lines (BLA and BLB). Then, during a read operation, the first and second read access transistors (MAR1 and MAR2) are turned on by means of a read word line control (RWL) to form a conducting path between the data storage nodes (N1 and N2) of the cell and the complementary read bit lines (RBLA and RBLB). This design allows the access devices to be sized differently for read and write operations to allow more flexible optimisation, but the internal nodes are still stressed by a read operation. As discussed briefly above, writing data into a memory cell is achieved by forcing a high voltage onto one of BLA or BLB whilst simultaneously forcing a low voltage onto the other, and then driving the word line (WL) high to activate the access path. The low voltage on one of the bit lines therefore needs to be conducted through the associated access transistor (MA1 or MA2) whilst fighting against the corresponding PMOS pull up device (MP1 or MP2). For small 6-transistor cells the sizes of all of the transistors is minimised, and advanced technologies now have PMOS devices of about the same strength as NMOS devices. It can therefore be difficult to ensure that the NMOS access transistor is able to overdrive the corresponding PMOS pull up device during a write operation. Consequently, some means of "write-assist" is now frequently employed in order to ensure reliable operation.

There are three common schemes for providing "write- assist":

• word line (WL) boost - that is used to increase the drive on the gate of the access transistor;

• negative bit line (BL) - that is also used the access transistor to conductor harder; and

• positive supply (VDD) collapse.

The first two schemes work, but are difficult to implement across all process-voltage-temperature (PVT) variations. They also involve voltages outside the normal supply voltage range of 0 to VDD, so there are reliability and ageing concerns.

VDD-collapse operates by reducing the positive voltage supplied to the cell, thereby making the PMOS pull up devices conduct less and thereby assisting the NMOS access transistor win the fight. There are no reliability or ageing concerns in this case because all voltages are within the normal operating range of 0 to VDD. However, implementing VDD-collapse can be difficult. The ideal scenario is for each cell to have its own separately-switched power supply; however, this consumes too much area. Sharing a switched power supply along a column saves area but degrades the cell voltage on all cells not being written. This could lead to data retention failures. Sharing a switched power supply along a row is better, but suffers the same data-corruption risk for any cells not being written.

In view of the above, it will be appreciated that there still exists a requirement for an improved arrangement that provides for the implementation of some form of write-assist for the memory cells within a memory unit, whilst minimising reliability and data retention concerns and without consuming too much additional area. Summary

Therefore, according to a first aspect of the present invention there is provided a memory unit. The memory unit comprises a memory cell, the memory cell being operatively connected to one or more bit lines, and wherein access for the one or more bit lines to the memory cell during a write operation is controlled by a word line. The memory cell further comprises a positive supply rail for supplying a positive voltage to the memory cell. The positive supply rail is connected to a positive voltage source via a supply switch, the supply switch being provided by a PMOS transistor with a gate of the PMOS transistor being connected to the associated word line such that the positive supply rail is disconnected from the positive voltage source during a write operation.

Each of the plurality of memory cells may have at least one dedicated read port such that access to the memory cell during a read operation is controlled by a read word line, the read word line being distinct from the word line that controls access to the memory cell during a write operation.

Each dedicated read port may then comprise a single-ended read port. In this case, each dedicated read port may comprise a data read transistor (MDR) connected to a storage node of the memory cell and a read access transistor (MAR) that is controlled by the read word line.

Alternatively, each dedicated read port may comprise a differential/double-ended read port. In this case, each dedicated read port may then comprise a first read access transistor (MAR1) operatively connecting a first storage node (N1) of the memory cell to a first (RBLA) of a pair of complimentary read bit lines, and a second read access transistor (MAR2) operatively connecting a second storage node (N2) of the memory cell to a second (RBLB) of the pair of complimentary read bit lines.

Each of the plurality of memory cells may comprise a pair of cross-coupled inverters having respective first and second storage access nodes, a first access transistor operatively connected to said first storage node, a second access transistor operatively connected to said second storage node, and the word line is connected to a gate on said first access transistor and a gate on said second access transistor for controlling said first access transistor and said second access transistor. The positive supply rail may then be connected to pull-up devices within the cross-coupled inverters. Preferably, the pull-up devices within the cross-coupled inverters are PMOS transistors and the positive supply rail is connected to a source of each PMOS transistor pull-up device. The memory unit may further comprise a first bit line operatively connected to said first storage node via said first access transistor, and a second bit line operatively connected to said second storage node via said second access transistor.

The memory unit may comprise a plurality of memory cells, each of the plurality of memory cells sharing a positive supply rail, and wherein access to each of the plurality of memory cells during a write operation is controlled by the word line. The shared positive supply rail is then connected to a positive voltage source via the supply switch. Preferably, the supply switch is connected to the word line at a location adjacent to an end of the word line.

The memory unit may comprise an array of memory cells arranged in rows and columns, with the plurality of memory cells being provided in a row of the array.

The memory unit may comprise a further plurality of memory cells, each of the further plurality of memory cells sharing a further positive supply rail, and wherein access to each of the further plurality of memory cells during a write operation is controlled by the word line. The further positive supply rail is then connected to a positive voltage source via a further supply switch. Preferably, the supply switch is connected to the word line at a location adjacent to an end of the word line and wherein the further supply switch is connected to the word line at a location adjacent to an opposite end of the word line.

The memory unit may comprise an array of memory cells arranged in rows and columns and both the plurality of memory cells and the further plurality of memory cells are provided in a row of the array.

The memory unit may further comprise a dummy memory cell connected to the positive supply rail, the dummy memory cell comprising access transistors that are controlled by the word line and wherein the dummy memory cell is configured to change state when the word line is driven high. Brief Description of the Drawings

The present invention will now be more particularly described by way of example only with reference to the accompanying drawings, in which:

Figure 1 illustrates schematically a standard 6-transistor memory cell;

Figure 2 illustrates an example of a block of 6-transistor memory cells;

Figure 3 illustrates schematically an example of an 8-transistor memory cell having a single-ended read port; Figure 4 illustrates schematically an example of an alternative 8-transistor memory cell having a differential/double-ended read port;

Figure 5 illustrates schematically an example of a memory cell of a memory unit described herein; Figure 6 illustrates schematically an example of a non-interleaved array architecture;

Figure 7 illustrates schematically an example of a row of memory cells of the memory unit described herein; and

Figure 8 illustrates schematically an example of a dummy memory cell for use in the memory unit described herein.

Detailed Description

As described above, conventional methods of implementing write-assist for the memory cells within a memory unit create reliability and data retention problems and/or consume too much area. Consequently, there will now be described a memory unit that at least mitigates the problems identified above, and Figure 5 illustrates schematically an example of a memory cell of such a memory unit.

Figure 5 shows the positive supply rail 17 of a memory cell 10. The positive supply rail 17 supplies a positive voltage to the memory cell 10. To do so, the positive supply rail 17 is connected to a positive voltage source 30 by/via a supply switch 20. The supply switch 20 is provided by a PMOS transistor with a gate of the PMOS transistor being connected to the word line that is used to control access to the memory cell 10 during a write operation. The positive supply rail 17 will therefore be disconnected from the positive voltage source 30 during a write operation.

As described above, in an SRAM memory cell the positive supply rail 17 is connected to a source of each of the PMOS transistor pull-up devices within the cross-coupled inverters of the memory cell 10. During a write operation, the word line (WL/VWVL) associated with a memory cell is driven high in order to activate the access path so as to allow the voltage levels held on the bit lines (BLA and BLB) to overcome the state of the storage element. Driving the word line (WL/WWL) high will therefore turn off the supply switch 20 during a write operation, thereby allowing the voltage on the positive supply rail 17 to collapse when loaded, weakening the PMOS pull up devices (decreasing the strength of the cross-coupled inverters) and assisting the NMOS access transistors in writing to the cell.

The memory cell 10 can be a conventional 6-transistor memory cell such as that described above.

However, it is preferable that the memory cell 10 is a read decoupled memory cell. As described above, a read decoupled memory cell has at least one dedicated read port such that access to the memory cell during a read operation is controlled by an associated read word line, the associated read word line being separate/distinct from the associated word line that controls access to the memory cell during a write operation.

For example, such a read decoupled memory cell could comprise one or more single-ended read ports. Figure 3 described above shows an 8-transistor cell design that separates out the write and read paths of the circuit by the addition of a single-ended read port. In this case, each dedicated read port could comprise a data read transistor (MDR) connected to a storage node of the memory cell and a read access device/transistor (MAR) that is controlled by the associated read word line. However, other arrangements for single-ended read ports are known. In addition, whilst Figure 3 only shows one dedicated read port, it is also possible for a read decoupled memory cell to have multiple single-ended read ports that can be driven by either side of the cell.

Alternatively, such a read decoupled memory cell could comprise a differential/double-ended read port. Figure 4 described above shows an 8-transistor cell design that separates out the write and read paths of the circuit by the addition a differential/double-ended read port. In this case, a dedicated read port could comprise a first read access transistor (MAR1) operatively connecting a first storage node (N 1) of the memory cell to a first (RBLA) of a pair of complimentary read bit lines, and a second read access transistor (MAR2) operatively connecting a second storage node (N2) of the memory cell to a second (RBLB) of the pair of complimentary read bit lines.

The above described arrangement provides a straightforward means for disconnecting a memory cell from the positive voltage source during a write operation so as to implement positive supply collapse as a form of write assist. In particular, this approach is easy to implement as it can be achieved by adding just one metal line in the direction of a word line and one or two additional PMOS devices that are timed from existing signals. This approach also reduces the power consumed during a write operation. In this regard, conventional write operations require a current fight through the PMOS pull-up devices. In contrast, this positive supply collapse scheme allows the PMOS pull-up device to weaken until the write can occur. Consequently, the current on the bit lines used for a write operation can be less, whilst still being able to change the cell state, and the total charge pulled by the write driver is less. Of course, when the supply switch is turned on again at the end of a write operation it has to bring the positive supply rail back up to the full positive supply voltage but the total charge drawn from the supply for the whole write operation will be less than that of other conventional write schemes.

Furthermore, if the memory unit is such that all of the memory cells along a row (or partial row) are always written, then it becomes practical to share such a switched positive supply rail between all of the memory cells in a row (or partial row), as there will then be no cells in read mode that need to retain data.

For example, this would be possible in a memory unit having a non-interleaved array. In this regard, most conventional SRAM designs opt for a bit-interleaved array in which bits from multiple words are shared along a row. In contrast, in a non-interleaved array architecture such as that shown in Figure 6 the word lines are segmented such that only single whole words are accessed at a time.

The sharing of the above described switched positive supply rail between a plurality of the memory cells in a row would also be possible for read decoupled memory cells (i.e. cells having one or more dedicated read ports), as there will then be no conflict between occurrences of positive supply collapse for write-assist and cell read provided that there is no clash of read and write addresses. Ensuring no address clash guarantees that the cells to which positive supply collapse is applied during a write operation are not being read at the same time, and also ensures that a memory cell being read has the full positive supply voltage on the positive supply rail.

Figure 7 therefore illustrates schematically an example of the above described memory unit wherein a plurality of memory cells share a switched positive supply rail 17. In this example, the memory unit comprises a plurality of memory cells 100 that share the positive supply rail 17, and wherein access to each of the plurality of memory cells during a write operation is controlled by an associated word line (WL/WWL) 40. In other words, each of the plurality of memory cells that share the positive supply rail 17 are in the same row and share the same word line. The positive supply rail 17 is connected to a positive voltage source (VDD) by/via the supply switch 20 that is controlled by the associated word line (WL/WWL) 40.

Preferably, the supply switch 20 is connected to the associated word line (WL/WWL) 40 at a location adjacent to an end of the associated word line. For example, in Figure 6 the supply switch 20 is connected to the associated word line (WL/WWL) 40 at a location adjacent to a word line driver for the associated word line (WL/WWL) 40. In this regard, it is preferable that the supply switches 20 are located adjacent to the end of the row (or row segment) as conventional memory cell layouts are designed to share contacts with adjacent cells for efficient area layout. Consequently, there is an area penalty involved whenever there is a break in a contiguous chain of cells.

In the example of Figure 7, the memory unit comprises a further, second plurality of memory cells

100' that share a separate, further positive supply rail 17'. Access to each of the further plurality of memory cells 100' during a write operation is controlled by the associated word line (WL/WWL) 40. In other words, each of the further plurality of memory cells that share the further positive supply rail 17' are in the same row and share the same word line, and are also in the same row and share the same word line as the first plurality of memory cells 100. The further positive supply rail 17' is connected to a positive voltage source (VDD) by/via a further supply switch 20' that is controlled by the associated word line (WL/WWL) 40.

Again, it is preferable that the further supply switch 20' is connected to the associated word line 40 at a location adjacent to an end of the associated word line. Consequently, as both the supply switch 20 and further supply switch 20' are connected to the same word line, it is preferable that the further supply switch 20' is connected to the associated word line 40 at a location adjacent to an opposite end of the associated word line 40 to that of the first supply switch 20.

Figure 7 thereby illustrates a row of the memory unit that has been split such that a first subset of the cells in the row share a first positive supply rail 17, whilst a second subset of the cells in the row share a second positive supply rail 17', with both the first positive supply rail 17 and the second positive supply rail 17' being connected to a positive voltage source via switches that are controlled by the word line 40 associated with that row of cells.

In this regard, when implementing positive supply collapse using the above described memory circuits, the amount of voltage drop on a positive supply rail will be dependent upon the number of cells that are connected to that positive supply rail that are changing state. Consequently, the limiting scenario for the speed of the write operation will be that in which only one of these memory cells is changing state. The ratioed fight between the NMOS access transistor and the corresponding PMOS pull up device when writing a "0" discharges the positive supply rail until it is low enough for the PMOS pull up device to be overcome by the NMOS access transistor. Having only one memory cell change state means that the total current being drawn is at a minimum and the positive supply rail will be discharged slowly, with the exact rate of discharge being dependent upon the capacitance of the positive supply rail. The more memory cells that share a positive supply rail, the higher the capacitance and therefore the slower the worst-case discharge rate. For this reason, it is advantageous to subdivide the positive supply rail as much as possible, so that fewer memory cells share it and the capacitance is small, to thereby give the fastest write operation. However, as described above, it is important that the switched positive supply rail is shared between a number of memory cells in order to consume area. Consequently, there is a trade-off between write operation speed and the area consumed by the switched positive supply rails. It is also possible to mitigate against the speed limiting scenario of only a single cell changing state by providing an additional discharge path for the positive supply. For example, a dummy memory cell could be included that is connected to the positive supply rail to ensure that the positive supply rail is discharged at a rate that is faster than the single memory cell scenario. In this regard, Figure 8 illustrates a possible example of such a dummy memory cell 50 that takes the form of a modified 6-transistor memory cell. In this example, the access transistors 56a, 56b of the dummy memory cell 50 connect the storage nodes (N1 and N2) 53, 54 to ground. An inverter 58 is then included between the associated word line and one of the access transistors 56a, such that this access transistor is driven in opposition. Consequently, when the word line is low, the dummy memory cell 50 will switch to its reset state (N1 low), and will subsequently have to change state when the row is selected by the word line being driven high. This dummy cell will therefore change state every time the corresponding row (or partial row) is selected, thereby providing additional discharge on the associated positive supply rail 17/57.

It will be appreciated that individual items described above may be used on their own or in combination with other items shown in the drawings or described in the description and that items mentioned in the same passage as each other or the same drawing as each other need not be used in combination with each other. In addition, any reference to "comprising" or "consisting" is not intended to be limiting in any way whatsoever and the reader should interpret the description and claims accordingly. Furthermore, although the invention has been described in terms of preferred embodiments as set forth above, it should be understood that these embodiments are illustrative only.

Those skilled in the art will be able to make modifications and alternatives in view of the disclosure which are contemplated as falling within the scope of the appended claims. For example, those skilled in the art will appreciate that the above-described invention might be equally applicable to other types of memory.




 
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