The invention relates to an electronic circuit comprising a frequency or phase- locked loop comprising a first input terminal coupled to receive a first input signal; a second input terminal coupled to receive a second input signal; detection means for comparing the frequency or phase of the first input signal with the frequency or phase of the second input signal, respectively, and for supplying directly or via a charge pump a control voltage as a result of the comparison of the first and second input signals; a control transistor having a first main terminal and a control terminal which are coupled to receive the control voltage and having a second main terminal for supplying a control current responsive to the control voltage; a capacitor coupled in between the first main terminal and the control terminal; a current controlled oscillator having an input terminal coupled to receive the control current and having an output terminal for supplying directly or via frequency dividers the second input signal having a frequency or phase which is synchronized with the frequency or phase, respectively, of the first input signal; and a stabilizing circuit for stabilizing the frequency or phase-locked loop by adding a zero to the loop transfer function of the frequency or phase- locked loop.

Such an electronic circuit is generally known from the state of the art, as for example shown in Figure 1. In Figure 1 a phase-locked loop, further denoted as PLL, is shown. Instead of a PLL also a frequency-locked loop circuit can be used if the detection means DMNS comprises a frequency-comparator instead of a phase-comparator. In many applications the detection means DMNS is a combined frequency/phase-comparator. For clarity reasons the invention will only be described as a PLL.

PLLs are widely used in applications requiring controlled loop gains to ensure optimum time response. If a PLL is used in an integrated circuit, the loop gain of the PLL may vary with temperature, supply voltage, and process dependent parameters such as oxide thickness, sheet resistances, implant concentrations, etcetera. The PLL includes a phase comparator DMNS which receives a (self-clocking) signal D from an asynchronous data source. The phase comparator DMNS supplies a frequency incrementing control signal FUP and a frequency decrementing control signal FDN to a charge pump CHPPMP. The charge pump CHPPMP generates a pump output current Ip, which flows in either a positive or

negative direction depending on whether one or the other of the respective frequency incrementing/decrementing signals FUP or FDN, is supplied. The pump output current Ip is generated with modulated fixed-magnitude pulses.

The Ip current pulses will either add charge to or withdraw charge from a charge accumulating capacitor C. Charge accumulation in the capacitor C generates an integrated voltage VCNTRL which is applied to the input of the current controlled oscillator CCO via the control transistor To. The CCO produces a (periodic) signal CLK having a variable frequency fosc which is a function of its input voltage. The signal CLK is fed back to input 2 of the phase comparator DMNS while the signal D which is generally aperiodic and is therefore of unknown phase and frequency is supplied to input 1 of the phase comparator DMNS.

Although the signal D is generally aperiodic, it is self-clocking in the sense that is has a fundamental clock frequency which can be derived by averaging over time. The PLL is designed to derive this fundamental clock frequency and to lock on to the phase of the incoming signal D as well. The operation of the PLL will be explained for the case where the signals CLK lags behind the signal D and then for the case where the signal CLK leads the signal D. In situations where incoming edges of the signal arrive before the corresponding edges of the signal CLK (the signal CLK lags), the phase comparator DMNS outputs the frequency incrementing signal FUP to the charge pump CHPPMP and thereby causes the charge pump CHPPMP to supply a positive value of the pump current Ip (see the direction of the arrow with regard to Ip in Figure 1). Thus the integrating capacitor C accumulates charge.

The input voltage Vosc of the CCO, or in fact the current into the input terminal CCOI, is incremented by the accumulated charge and in response the CCO increases the speed of the signal CLK. The frequency fosc of the signal CLK is incremented to a higher value than the fundamental clock frequency of the signal D. The edges of the faster signal CLK then begin to catch up with the edges of the slower signal D. The output frequency fosc drops back to the value of the fundamental clock frequency as the edges of the signal CLK close in on the edges of the signal D. Once the signal CLK is substantially in phase with the signal D, the phase comparator DMNS ceases to output the frequency incrementing signal FUP and the output frequency fosc is held at a steady-state value which is for practical purposes equal to the fundamental clock frequency of the signal D.

For cases where the signal D edges lag behind the signal CLK edges, the phase comparator DMNS outputs the frequency decrementing signal FDN to the charge pump CHPPMP thereby causing the charge pump CHPPMP to supply a negative value of the pump

current Ip. Thus the capacitor C discharges, thereby reducing Vcntrl and VO5C and causing the frequency fosc of the CCO to decrease. This delays the signal CLK edges until the edges of the signal D catch up and align with the signal CLK. The FDN control signal is shut off once phase alignment has been obtained.

Typically, the charge pump is designed to deliver the pump current Ip in the form of positive or negative rectangular current pulses. The magnitude of the CCO input voltage Vosc, or in fact the current into the input terminal CCOI, is changed by modulating the pulse width of the pump current pulses. A generally linearly combined transfer function results from the counterbalancing effect of the characteristic gain function belonging to the control transistor To, the current controlled oscillator CCO, and the chargepump CHPPMP.

By the way, in many PLL schematic diagrams a voltage controlled oscillator VCO is shown instead of the current controlled oscillator CCO. This is, however, not a real difference; the control transistor To in combination with the CCO of Figure 1 forms in fact a VCO.

For stability reasons, a so-called zero is implemented in the loop transfer function of the PLL. In the general state of the art the zero is usually implemented by the addition of a resistor in series with the capacitor C, as is indicated in Figure 1 by compensation resistor Rz. This has, however, the disadvantage that the control voltage V can easily be disturbed since the control voltage Vcntrl is less effectively decoupled by the capacitor C as a result of the addition of the compensation resistor Rz.

It is an object of the invention to provide an electronic circuit comprising a frequency or phase-locked loop which does away with above disadvantage.

To this end, according to the invention, the stabilizing circuit comprises a further charge pump for delivering a compensation current to the input terminal of the current controlled oscillator, while the compensation current may have an approximately zero value, a negative value, or a possitive value depending on control signals delivered by the detection means, and the absolute value of said positive or negative value roughly linearly depends on the control voltage.

By these measures the desired zero for stability reasons is implemented without using a resistor in series with the capacitor. Therefore, the control voltage cannot easily be disturbed, since the capacitor also functions very effectively as a decoupling means.

US-patent 5,942, 947 shows an alternative solution which needs a digital damping circuit for implementing the zero. The solution according to the invention does not need such digital circuitry.

The stabilizing circuit can be used in several ways. It is for instance possible to apply a transistor in which the drain or collector supplies a reference current for the further charge pump, because a resistor is connected in series with the source or emitter, and the gate or base, and a node of the resistor, which node is not connected to said source or emitter, receives the control voltage across the capacitor. The value of the resistor must be high in comparison with 1/gM of said transistor, or, alternatively, the gM of the transistor must be enhanced by the addition of an amplifier. The enhancement of the gM of a transistor by an amplifier is well known in the prior art.

In an embodiment of the invention a field effect transistor is used as the control transistor, the former having a source, a drain, and a gate which respectively form the first main terminal, the second main terminal, and the control terminal of the control transistor, and the stabilizing circuit further comprises a first field effect transistor; a second field effect transistor ; a third field effect transistor; a fourth field effect transistor ; a current mirror having an input coupled to the drain of the first transistor and an output coupled to the drain of the fourth transistor; and means for supplying a DC-voltage between the drain and the gate of the fourth transistor, the sources of the third and fourth transistors being coupled to the source of the control transistor, the gate of the third transistor being coupled to the gate of the fourth transistor, the source of the first transistor being coupled to the drain of the third transistor, the source of the second transistor being coupled to the drain of the fourth transistor, the gates of the first and second transistors being coupled to the gate of the control transistor, and a reference input of the further charge pump being coupled to the current mirror in a manner that said absolute value is approximately linearly dependent on the current through the input of the current mirror.

This embodiment has the advantage that no resistor is needed at all.

Further advantageous embodiments are specified in further dependent claims.

The invention will be described in more detail with reference to the accompanying drawing, in which: Figure 1 is a circuit diagram of an electronic circuit comprising a known PLL; Figure 2 shows circuit diagrams of current or voltage controlled oscillators which can be used in PLLs ; Figure 3 shows a diagram of a current controlled oscillator and a control transistor for delivering a control current to the current controlled oscillator in response to a control voltage, and figures for indicating the relation of the frequency of the current

controlled oscillator to the control voltage, the current through the current controlled oscillator, and the voltage across the current controlled oscillator; Figure 4 is a circuit diagram of an electronic circuit comprising a PLL according to the invention; Figure 5 is a detailed circuit diagram of an inventive stabilizing circuit which can be applied in the inventive PLL according to Figure 4; Figure 6 is a circuit diagram of a charge pump which can be used in PLLs ; and Figure 7 is a more detailed circuit diagram of the inventive stabilizing circuit according to Figure 5 in which a use of the further charge pump is shown.

In these figures parts or elements having like functions or purposes bear like reference symbols.

Figure 4 shows a PLL according to the invention. The differences with respect to the PLL according to Figure 1 are the removal of the compensation resistor Rz and the addition of the stabilizing circuit STB. A field effect transistor To is used as the control transistor To by way of example. In this situation the current controlled oscillator CCO, further denoted as CCO, is preferably used by one of the circuits shown in Fig. 2A, Fig. 2B, or Fig. 2C. By doing so the frequency lose of the CCO is approximately linearly dependent on the control voltage Vc. tri or the voltage VO5C across the CCO, as is schematically indicated in Figure 3.

The stabilizing circuit STB is demonstrated as a current source (in Figure 4) which can either push (Ip is positive) or pull (Ip is negative) a current into the input terminal CCOI of the CCO, or do not deliver current at all (Ip=0), which is determined by the control signals FUP and FDN. To obtain a good stability, the compensation current Iz is determined by formula: Iz = GMTonp-Rz [1] in which: GMTO is the transconductance of the control transistor To; Ip is the pump output current from the charge pump CHPPMP ; and Rz is the value of the compensation resistor Rz which would have been necessary in well-known prior art PLLs.

With the aid of formula [1] the inventive PLL of Figure 4 is dimensioned as follows for stability purposes : determine the value of the resistor Rz in the prior art PLL of

Figure 1, determine the value of the compensation current Iz by filling in the value of said resistor Rz in formula [1]. So if for example the optimal value of resistor Rz in the prior art would have been 100 Ohm, then the value of the compensation current Iz is determined by: Iz= 100 GMTo Ip Figure 5 shows a detailed circuit diagram of a preferred embodiment of the stabilizing circuit STB. The stabilizing circuit STB comprises a first field effect transistor TI ; a second field effect transistor T2 ; a third field effect transistor T3 ; a fourth field effect transistor T4; a current mirror CM having an input connected to the drain of the first transistor Tl and an output connected to the drain of the fourth transistor T4; and means for supplying a DC-voltage VTUNE between the drain and the gate of the fourth transistor T4, the sources of the third and fourth transistors are T3 and T4 being connected to the source of the control transistor To, the gate of the third transistor T3 being connected to the gate of the fourth transistor T4, the source of the first transistor Tl being connected to the drain of the third transistor T3, the source of the second transistor T2 being connected to the drain of the fourth transistor T4 and the gates of the first and the second transistors Tl and Ta being connected to the gate of the control transistor To. The stabilizing circuit STB further comprises a further charge pump CHPPMPF for delivering a compensation current Iz to the input terminal CCO of the current controlled oscillator CCO.

The current mirror CM comprises a first current mirror transistor cm, having a first main terminal, a second main terminal, and a control terminal, the second main terminal and the control terminal being connected to each other and thereby forming the input of the current mirror CM; and a second current mirror transistor cm2 having a first main terminal connected to the first main terminal of the first current mirror transistor cml, a second main terminal which forms the output of the current mirror CM, and a control terminal which is connected to the control terminal of the first current mirror transistor cml.

The first main terminals of the first current mirror transistor cml and of the second current mirror transistor cm2 are connected to the first power supply terminal Vss.

The sources of the third and fourth transistors T3 and T4 are connected to the second power supply terminal VDD. Field effect transistors or bi-polar transistors may be used as the first and second current mirror transistors cml and cm2.

A reference input Izpp of the further charge pump CHPPMPF is connected to the input of the current mirror CM.

A transistor Ts which is arranged as a diode configuration and which is biased by a current ITUNE is used as the means for supplying the DC-voltage VTUNE by way of example.

The stabilizing circuit STB is dimensioned in a manner that the first and second transistors Tl and Ta are in their saturation region, the third and fourth transistors T3 and T4 are in their linear region, and in a manner that the drain-source voltage of the third transistor T3 is approximately two times as high as the drain-source voltage of the fourth transistor T4. In this way the stabilizing circuit STB delivers a reference current Irnr which is approximately linearly dependent on the control voltage VCNTRL. It in fact"matches"with formula [1] in that Rz is now determined by PRUNE (or 1-ruNE). By the connection of the reference input Izpp of the further charge pump CHPPMPF to the input (gate and drain connection of first current mirror transistor cml) of the current mirror CM the reference current Imr is copied (see Figure 7) into the further charge pump CHPPMPF to serve as the reference current for the further charge pump CHPPMPF.

Figure 6 shows a use for the charge pump CHPPMP which comprises N-type field effect transistors T6, Tg, Tg and Tl2, P-type field effect transistors T7, Tic, and Tll, and a reference current source Iref. The gates of transistor Ts and Tlo are coupled to receive the control signals FUP and FDN, respectively. The sources of transistors T6, Tg, and Tl2 are connected to the first power supply terminal Vss. The sources of transistors T7 and Tlo are connected to the second power supply terminal VDD. The gates of transistors T7 and Tl and the drains of transistors and the drains of transistors T6 and T7 are connected to each other.

The gates of transistors T6, T9, and Tri2, and the drain of transistor T12 are connected to each other. The drain of transistor T8 is connected to the source of transistor Tg. The drain of transistor Tlo is connected to the source of transistor T, 1. The drains of transistors Tg and T are connected to each other to form an output for supplying the pump output current Ip. The reference current source Iref is coupled to supply a reference current Iref through the transistor Tl2.

The charge pump CHPPMP according to Figure 6 operates as follows.

Transistors T12 and T6 form a current mirror which in this example has a mirror ratio of approximately one. Therefore, a reference current Iref is supplied through the transistor T7.

If the control signal FUP has a logic low level and the control signal FDN has a logic high level, both transistors Ts and Tlo are non-conducting. Therefore, also transistors

Tg and Tl are non-conducting. As a consequence, the value of the pump output current Ip is zero.

A substantially zero pump output current Ip can alternatively also be obtained if the control signal FUP has a logic high level and the control signal FDN has a logic low level. All 4 transistors T8-Tlo are conducting in that situation. A higher switching frequency can then be reached compared to the former situation. (By mismatch the pump output current Ip may slightly differ from zero, however.) If the control signal FUP has a logic high level and the control signal FDN has a logic high level, both transistors TIO and T11 are again non-conducting. Transistor T8 is conducting, thereby in fact connecting the source of transistor T9 to the first power supply terminal Vss. In this situation transistors T12 and Tg also form a current mirror which in this example has a mirror ratio of approximately one. Therefore, a reference current Iref is supplied through the transistor Tg. As a consequence, the value of the pump output current Ip is approximately equal to the value +Iref.

If the control signal FUP has a logic low level and the control signal FDN has a logic low level, both transistors T8 and Tg are non-conducting. Transistor Tlo is conducting, thereby in fact connecting the source of transistor Tl l to the second power supply terminal VDD. In this situation transistors T7 and Tu also form a current mirror which in this example has a mirror ratio of approximately one. Therefore, a reference current Iref is supplied through the transistor Tl l. As a consequence, the value of the pump output current Ip is approximately equal to the value-Iref.

Figure 7 shows a more detailed circuit diagram of the inventive stabilizing circuit STB according to Figure 5 in which a use for the further charge pump CHPPMPF is shown. The further charge pump CHPPMPF is basically used in the same way as the charge pump CHPPMP as shown in Figure 6. Transistors Tgp-Tup in Figure 7 correspond to transistors T6-Tll in Figure 6. The reference current Iref and the transistor T12 are not indicated in Figure 7. This is because the gate of transistor T6F, which forms the reference input IZRF of the further charge pump CHPPMPF, is connected to the gate of the transistor cml. Therefore, the transistor cml performs in figure 7 also the function of transistor Tri2, whereby the reference current Imr replaces the reference current Iref. An important difference between the CHPPMP and the further charge pump CHPPMPF is that the reference current Irnr is approximately linearly dependent on the control voltage VCNTRL. Another difference is that the gates of transistors T8F and TIOF are coupled to receive the control signals FDN and FUP, respectively. This is because the compensation current Iz and the control current Icntri

must be in phase, while the control transistor To has an inverting property from its gate to its drain. (See also Figure 4).

The field effect transistors in the charge pump CHPPMP and the further charge pump CHPPMPF may be fully or partly replaced by bi-polar transistors. However, transistors which form a current mirror cannot be different types of transistors. So if, for example, a bi-polar transistor is used as the transistor cml, also transistor cm2 and transistor T6F must be bi-polar transistors.

Current mirror ratios in the charge pump CHPPMP and the further charge pump CHPPMPF need not necessarily be equal to one.

The inventive PLL (or frequency locked-loop) can be used in an integrated circuit or can be built up by discrete components.