Title:
STABLE LOW DROPOUT VOLTAGE REGULATOR
Document Type and Number:
WIPO Patent Application WO/2010/015662
Kind Code:
A3
Abstract:
The present invention relates to a Low-dropout (LDO) voltage regulator (1) comprising: - a Ballast Transistor PBaI (3) of the P-channel MOS or Bipolar type, having a gate (34) and a main conduction path (D-S) connected in a path between the input V
DD
(4) and the output V
ouτ
(5) of the regulator - an Operational Transconductance Amplifier (OTA) (2) being implemented as an adaptative biasing transistor amplifier and having an inverting input coupled to the output V
ouτ
(5) through a voltage divider R1-R2 (61), a non-inverting input coupled to a voltage reference circuit (7) and having an output connected to the gate (34) of the Ballast transistor (3). To stabilize the output (5) and to increase the power supply rejection ratio (PSRR) of the LDO voltage regulator (1), OTA (2) comprises a resistance R
s
, which enables to stabilize the output (5) and to increase the Power Supply Rejection Ratio (PSRR).
Inventors:
GIROUD FREDERIC (CH)
Application Number:
PCT/EP2009/060167
Publication Date:
December 16, 2010
Filing Date:
August 05, 2009
Export Citation:
Assignee:
SUISSE ELECTRONIQUE MICROTECH (CH)
GIROUD FREDERIC (CH)
GIROUD FREDERIC (CH)
International Classes:
G05F3/30
Foreign References:
| EP1111493A1 | 2001-06-27 | |||
| US20040164789A1 | 2004-08-26 | |||
| US6465994B1 | 2002-10-15 |
Attorney, Agent or Firm:
BALLOT, Gabriel (Rue du Puits-Godet 8A, Neuchâtel, CH)
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