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Patent Searching and Data


Title:
STACKED FET WITH INDEPENDENT GATE CONTROL
Document Type and Number:
WIPO Patent Application WO/2023/046013
Kind Code:
A1
Abstract:
Stacked FET devices have independent and shared gate contacts are provided. The stacked FET device includes: a bottom-level FET (s) which has a bottom-level FET gate (902); a top-level FET (s) which has a top-level FET gate (904), wherein an upper portion of the bottom-level FET gate (902) is adjacent to the top-level FET gate (904); a dielectric sidewall spacer (504) in between the upper portion of the bottom-level FET gate (902) and the top-level FET gate (904); and a dielectric gate cap (1102) disposed over the bottom and top-level FET gates (902, 904)that includes a different dielectric material from the dielectric sidewall spacer (504). A device has at least one first stacked FET device and at least one second stacked FET device, and a method of forming a stacked FET device are also provided.

Inventors:
XIE RUILONG (US)
FROUGIER JULIEN (US)
CHENG KANGGUO (US)
LI JUNTAO (US)
PARK CHANRO (US)
Application Number:
PCT/CN2022/120546
Publication Date:
March 30, 2023
Filing Date:
September 22, 2022
Export Citation:
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Assignee:
IBM (US)
IBM CHINA CO LTD (CN)
International Classes:
H01L21/336
Foreign References:
CN101399207A2009-04-01
US20200075409A12020-03-05
US10692768B12020-06-23
US20180130811A12018-05-10
US20180190769A12018-07-05
US20160118404A12016-04-28
Attorney, Agent or Firm:
ZHONGZI LAW OFFICE (CN)
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