Title:
STACKED SEMICONDUCTOR DEVICE AND MULTIPLE CHIPS USED THEREIN
Document Type and Number:
WIPO Patent Application WO/2020/105432
Kind Code:
A1
Abstract:
[Problem] To provide a stacked semiconductor device capable of easily repairing a mounted chip, shortening a manufacturing time, and preventing waste of resources. [Solution] The present invention comprises: a parent substrate 81 in which unit elements are arranged in unit element regions which are divided along a first lattice and which are defined on a first main surface, and the first main surface is divided into chip mounting regions along a second lattice; chips Xij mounted on the first main surface side, and facing the chip mounting regions; and bump connectors Buv, which are arranged along a third lattice corresponding to the array of the unit elements, temporarily connect the parent substrate and each of the plurality of chips to independently transmit signals from the plurality of unit elements to circuits integrated on the plurality of chips, and couple the parent substrate and the chips through a main connection lower than the height of the temporary connection. The bump connector can be separated into a substrate-side connector and a chip-side connector.
Inventors:
MOTOYOSHI MAKOTO (JP)
Application Number:
PCT/JP2019/043453
Publication Date:
May 28, 2020
Filing Date:
November 06, 2019
Export Citation:
Assignee:
TOHOKU MICROTEC CO LTD (JP)
International Classes:
H01L21/60; H01L23/12
Domestic Patent References:
| WO2017081798A1 | 2017-05-18 | |||
| WO2014136241A1 | 2014-09-12 | |||
| WO2014006812A1 | 2014-01-09 |
Foreign References:
| JPH08340000A | 1996-12-24 | |||
| JPH07211720A | 1995-08-11 | |||
| JP2017081891W |
Other References:
See also references of EP 3796367A4
Attorney, Agent or Firm:
AMBO Aiko (JP)
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