BACKGROUND

[0001] Many of the control logic in print heads (PHs), such as integrated print heads (IPHs), including print heads with cartridges and print heads without cartridges, are formed using dynamic n-channel metal-oxide-semiconductor field effect transistor (NMOS) based logic. For example, dynamic NMOS based logic may include a pull-down network including a number of NMOS transistors to couple the output to a first supply voltage that may be associated with one logic value. The dynamic NMOS based logic may also include another load that connects the output to the second supply voltage that may be associated with a second logic value.

BRIEF DESCRIPTION OF THE DRAWINGS

[0002] Examples are described in the following detailed description and in reference to the drawings, in which:

[0003] Fig. 1 depicts an example block diagram of a printer system in accordance with one example of the present specification;

[0004] Fig. 2 depicts an example block diagram of an IPH in accordance with one example of the present specification;

[0005] Fig. 3 depicts an example block diagram of static NMOS based logic with a high impedance load in accordance with one example of the present specification; and [0006] Figs. 4A - 4C illustrates example inverters that are memristor load based static NMOS logic used in an IPH, such as those shown in Figs. 1 and 2, in accordance with one example of the present specification.

DETAILED DESCRIPTION

[0007] CMOS circuits implement both p-channel metal-oxide-semiconductor field effect transistor (PMOS) and NMOS circuits to generate a logic value output. For example, an NMOS circuit may be coupled to a first supply voltage and an output. Similarly, a PMOS circuit may be coupled to a second supply voltage and the output. Because CMOS uses both NMOS and PMOS circuits, each PMOS circuit is in series with an NMOS circuit such that when one is in an open state the other is in a closed state, preventing current flow. It is when the PMOS and NMOS circuits are changing states that significant amount of current may flow through the CMOS circuit. Because of the reduced power consumption of CMOS circuits and the attendant reduction in heating, CMOS architecture has seen widespread use in electronics. However, while CMOS circuits may be beneficial, some characteristics may prevent their expanded use. Such dynamic NMOS based logic may be beneficial in providing a reduced foot print, and consequently higher density, compared to complementary metal oxide semiconductor (CMOS) and pseudo-NMOS logic based circuits.

[0008] For example, CMOS circuits, by incorporating both NMOS circuits and

PMOS circuits, may have a greater quantity of transistors, and more complicated, operations to fabricate and accordingly may be more expensive. Accordingly, a pulldown network including a number of NMOS transistors may be used instead of CMOS circuit to couple to the output to the first supply voltage that may be associated with one logic value. The pull-down network also includes another load that connects the output to the second supply voltage that may be associated with a second logic value. Such pulldown networks may offer manufacturing advantages over CMOS due to the reduced number of manufacturing operations during wafer fabrication. Moreover, such pull-down networks may also utilize smaller logic elements. While such pull-down networks may be beneficial, they may have some restraints on expanded use. For example, the other load on the pull-down network may take up significant space on the circuit due in part to the large resistance used for a pseudo-pull-up network. Further, such pull-down network (i.e., dynamic NMOS based logic) may involve more signal lines and a dedicated specification specific integrated circuit (ASIC). Further, the speed and power dissipation of such NMOS based logic may need to be simulated and optimized. For example, existing IPHs= use CMOS logic with other analog functions and have fewer circuit designs and bond pads. However, they may result in using more complicated and expensive processes, since both PMOS and NMOS logic may need to be integrated during the fabrication process.

[0009] Accordingly, present specification discloses techniques to alleviate these and other complications that may arise in the control logic used in IPHs. More specifically, the present specification describes a pull-down network that includes a high impedance load that is much smaller in size than other high impedance loads. Resistor dimensions are defined by length and width and for example, for a given width, the length of the resistor may have to be increased to increase the resistance and vice versa. The term "high impedance load" refers to an electrical load having high impedance. Example electrical load is an electrical component or a portion of a circuit that consumes electrical power. The high impedance load may be a memristor. The memristor is a two connection electronic component whose resistance is dependent upon its current history. A memristor may also be used as a memory element of the IPH to store a logic value based on a resistance of the memristor. A memristor is non-volatile, meaning that data in the resistance state are retained even when power is not applied to the memristor. As will be described below, memristors may have a metal-insulator-metal structure that occupies a relatively small amount of surface area on a chip, making them attractive for use in an inverter and memory for IPHs in printing systems. In some examples, memristor can be 4F ² size. Still further, memristors can be manufactured and implemented relatively cheaply, thereby reducing the cost associated with production. Memristors may be added to wafer with few or no additional manufacturing operations. Furthermore, use of memristors in the control logic may reduce the number of bond pads needed in the control logic and thereby increasing circuit features/bond pads ratio. In addition, memristors, being compact in layout and having tunable resistance property, can be easily integrated into static logic.

[00010] Memristors can be made in a number of geometries and using a variety of materials. One form is a metal-insulator-metal memristor. The term "metal" is meant to refer broadly to indicate a conductor, for instance doped silicon. A memristor may include a bottom electrode (metal), a switching oxide (insulator), and a top electrode (metal). The bottom electrode, which may be part of another electronic component, can be coated with an insulator to form a switching oxide. This switching oxide insulator is then coated with a layer of another conductive material to form a top electrode. The switching oxide of the memristor may be doped with p type impurities and thus having holes. When an electrical field is applied to the memristor in one direction, the holes spread throughout the switching oxide, rendering it conductive. When an electrical field is applied to the memristor in the opposite direction, the holes are collected on one side, rendering the switching oxide non-conductive.

[00011] In this manner, the specification of an electrical field can shift a memristor from high resistance to low resistance (or vice versa). Absent an applied field, the holes are stable, and thus the resistance state of the memristor can be used to store data without a continuous supply of power. The memristor can be used to provide high impedance values in the high resistant state. The thickness, composition, and structure of the insulating switching oxide can be controlled during deposition to generate a desired resistance.

[00012] The present specification describes control logic in an IPH having inverters with a high impedance load. The control logic in the IPHs includes an output and a pull-down network serially-coupled between a first voltage and the output. The control logic in the IPHs also include high impedance load serially coupled between a second supply voltage and the output. The high impedance load being a memristor that is smaller in size than a transistor based load, such as PMOS based electrical component in the pull-down network.

[00013] The present specification describes a printing system having such pulldown network with a high impedance load. The printing system includes a first supply voltage, a second supply voltage, and an output. The printing system also includes at least one n-channel metal-oxide semiconductor field effect transistor (NMOSs) serially- coupled between the first supply voltage and the output and a high impedance load serially-coupled between the second supply voltage and the output. The high impedance load is disposed on a drain of an NMOS. Such memristor based NMOS logic for IPHs enable more on-chip functionality like serial to parallel convention, registers operation and so on. This enables reduced die cost and non-Au bonding as it facilitates easier DFM capability and may alleviate the need for analog-ASIC by including analog-to-digital converter (ADC) capability from other ASIC, such as digital ASIC for terminate and stay resident (TSR) and memory ADC function.

[00014] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present specification. It will be apparent, however, that the present apparatus, devices and systems may be practiced without these specific details. Reference in the specification to "an example" or similar language means that a particular feature, structure, or characteristic described is included in at least that one example, but not necessarily in other examples.

[00015] The terms "logic" and "circuit" are being used interchangeably throughout the document. Also the terms "static NMOS circuit" is also referred to as "static NMOS logic" or "ratioed NMOS logic".

[00016] Fig. 1 depicts an example printer system 100 and a host system 102, according to one example of the principles described herein. To achieve its desired functionality, the printer system 100 comprises various hardware components. Among those components, the printer system 100 may include a controller 104, an ink supply device 106, a power supply 108, and an IPH 110. As shown in Fig. 1, the ink supply device 106 may include memory 107. In one example, the memory 107 may store information associated with ink to be supplied for printing. In this case, the information may include the quantity of ink in the ink supply device 106, ink manufacturer, expiration date of the ink, color of the ink, conductivity of the ink, and the like. Further as shown in Fig. 1, the IPH 110 may include memory 114 and nozzle control logic 112. In one example, the memory 114 may store data associated with the printing operation. (Example, data include a document and or a file to be printed. As used herein, the term "memories 107 and 114" include any type of integrated circuit or other storage device for storing digital data including, without limitation, ROM, PROM, EEPROM, DRAM, Mobile DRAM, SDRAM, DDR 2 SDRAM, EDO/FPMS. RLDRAM, SRAM, "flash" memory (e.g., NAND/NOR), memristor memory, and PSRAM.

[00017] In addition, the nozzle control logic 112 may include a data processor

116 and a driver head 118. In one example, the data processor 116 may be in electrical communication with the driver head 118. In operation, the data processor 116 may instruct the driver head 118 to drive printer nozzles to fire the ink. As used herein, the term "data processor" means generally to include all types of digital processing devices including, without limitation, digital signal processors (DSPs), reduced instruction set computers (RISC), general-purpose (CISC) processors, microprocessors, gate arrays (e.g., field programmable gate arrays (FPGAs)), PLDs, reconfigurable computer fabrics (RCFs), array processors, secure microprocessors, and application-specific integrated circuits (ASICs). Such digital processors may be contained on a single unitary IC die, or distributed across multiple components.

[00018] Fig. 2 depicts the example IPH 110, according to one example of the principles described herein. As shown in Fig. 2, the IPH 110 may include a nozzle control logic 112 that is communicatively coupled to each of primitive logics 1-N 210 to send associated data addresses. The IPH 110 may include a memory array 114 and memory control logic 220. Further as shown in FIG. 2, each logic (i.e., nozzle control logic 112, primitive logics 1-N 210, memory control logic 220, and the like) includes a static NMOS logic 230 with a high impedance load 312 (shown in Fig. 3).

[00019] Fig 3 depicts the example block diagram of the static NMOS logic also referred to as ratioed logic 230 including a high impedance load 312. The static NMOS logic 230 may refer to circuitry that connects an output 317 to either first supply voltage 314, which may be ground, negative, or less than a second supply voltage 315, which second supply voltage 315 may be positive. More specifically, the static NMOS logic 230 implements pull up devices and pull down devices of different strengths to pass either a high or low output 317. The static NMOS logic 230 is included in circuitry, such as nozzle control logic, primitive logic, memory control logic and the like in the IPH 110 to carry out operations. The static NMOS logic 230 may be included in any type of element that is used in performing logic functions in the IPH 110 and among other integrated circuits in the printer system 100.

[00020] In general, the static NMOS logic 230 generates an output 317. The output 317 may reflect one of two voltages (314 and 315) - either the first supply voltage

314 or the second supply voltage 3 5. One of these supply voltages (314 and 315) may be used to represent and transmit a logical 1 and the other a logical 0. The pull-down network 313 may be a collection of logic elements. The pull-down network 313 receives input from control signals 316, which determines the state of pull-down network 313. Depending on the logic elements making up the pull-down network 313 and the control signals 316 provided, the pull-down network 313 is in either an open state or a closed state. When the pull-down network 313 is in open state, there is no electrical connection between the output 317 and the first supply voltage 314, so the voltage on the output 317 may reflect the second supply voltage 315. When the pull-down network 313 is in closed state, an electrical connection is established between the first supply voltage 314 and the output 317. Because the high impedance load 312 may limit the flow of current from the second supply voltage 315, while no similar limit exists between the first supply voltage 314 and the output 317, the output 317 may reflect the first supply voltage 314. Accordingly, depending on the state of the pull-down network 313, the output value may reflect either the first supply voltage 314 or the second supply voltage 315. The pulldown network 313 may be in an open or closed state when the high impedance load 312 is in a closed state.

[00021] Accordingly, the first supply voltage 314 and the second supply voltage

315 provide the two states, 0 and 1 , that are available as outputs 317. In some examples, the first supply voltage 314 is a ground, negative, or positive but of a lower voltage value than the second supply voltage 315.

[00022] The pull-down network 313 can take a variety of forms. In one example, it is a number of NMOSs formed as a multi-enclosed transistor. In another example, the NMOSs include a number of double enclosed NMOSs, in which a drain for a first NMOS functions as a source for a second NMOS. The NMOSs may be connected so as to perform a variety of logic operations on the control signals 316. The pull-down network 313 may contain other electronic components besides NMOSs to facilitate the printer system 100 operations.

[00023] As described above, the static NMOS logic includes a high impedance load 312. The high impedance load 312 allows the output 317 to be generated based on the second supply voltage 315 which may be a positive supply voltage greater than the first supply voltage 314. The high impedance load 312 may reduces the total current consumed by reducing flow between the first supply voltage 314 and the second supply voltage 3 5. The high impedance load 312 also allows the output 317 to reflect either voltage (314, 315) using a single switch. Without the high impedance load 312, the load from the pull-down network 313 may prevent the output 317 from reading the first supply voltage 314. The static N OS logic as described herein may provide reduced amounts of current from the second supply voltage 315 to the output 317 due to the high impedance load 312 being connected in series with the pull-down network 313. However, if a large current is needed from the second supply voltage 315, the output 317 can be used to control a transistor directly connected to the second supply voltage 315. Alternatively, in an example where each transistor or group of transistors has a high impedance load 312, the resistance of the high impedance loads 312 can be varied to control the fan-out and to optimize the response time of the controlled logic.

[00024] In some examples, the high impedance load 312 is a memristor in a high resistance state. In another example, the high impedance load 312 is a plurality of memristors, where some are in a high resistance state. The memristor may be non- rewritable. This allows the memristor to be included independent of switching controls for the memristor, which further simplifies the device. This is advantageous in that the memristor cannot be set to the wrong value and cannot be accidentally changed to the wrong value. The memristor state may be set during manufacturing or may be set later.

[00025] Figs. 4A through 4C depict example circuit diagrams of static NMOS logics 400A to 400Cwith respective memristors 416-1 to 416-3 according to examples of the principles described herein. The NMOS logics 400A to 400C may refer to circuits that connect outputs 317-1 to 317-3 to either first supply voltages 314-1 to 314-3 or second supply voltages 315-1 to 315-3, respectively. Specifically, Fig. 4A depicts the static NMOS logic 400A to perform an "AND" function that relies on inputs 419-1 and 419-2. As described above, the memristor 416-1 is a memory element that indicates a logic value based on a resistance level of the memristor 416-1. Fig. 4B depicts the static NMOS logic 416-2 implementing an AND as well as an OR function that relies on inputs 419-3 to 419-5. Fig. 4C depicts the static NMOS logic 416-3 implementing a NOT function. Implementing a NOT function relies on a single input 419-6 which may be indicated as a sixth input 419-6 to distinguish between the inputs 419-1 to 419-5 shown in Figs. 4A and 4B.

[00026] Because memristors (Figs. 4A-C, 416-1 to 416-3) may add benefits to IPH (Fig. 2, 110), including potentially high memory densities, simple formation, non-volatile memory, and low costs, using a high impedance load (Fig. 3. 312) comprising memristor (Figs. 4A-C, 416-1 to 416-3) components may be incorporated into some designs without additional process operations or production costs. The compact design of memristor (Figs. 4A-C, 416-1 to 416-3) being built into the size of the transistor offers the advantage of a high impedance load (Fig. 3, 312) without occupying additional space.

[00027] In some examples, it may be possible to further simplify the memristor (Fig. 4, 416-1 to 416-3) functioning as a high impedance load (Fig. 3, 312). For instance, some control elements that would otherwise be desired to set or clear the memristor (fig. 4, 416-1 to 416-3) memory may not be included. Because the memristor (Fig. 4, 416-1 to 416-3) does not serve as a low resistance element, the electrical contacts can be relatively poor conductors and still perform their function.

[00028] The IPH (Fig. 2, 110) with multi enclosed transistors and circuits (112, 114 and 210) to allow functioning of a static N OS pull-down logic (Fig. 2, 230) may have a number of advantages, including: reduced manufacturing costs, fewer process operations, ability to vary the high impedance load (Fig. 3, 312) from area to area of the circuit, smaller geometries for the logic, significant reduction in bond pads, shorter connection distances between elements, and slimmer die. Further, such multi enclosed transistors and circuits (112, 114 and 210) to allow functioning of a static NMOS pulldown logic (Fig. 2, 230) may enable more on-chip digital functions like serial and parallel convention, registers operation and so on, which can result in more efficient circuit operation and fewer bond pad counts, which may further reduce die cost and enable non-Au bonding as it can facilitate design-for-manufacturing (DFM) easily. This can furthermore result in alleviating the need for analog-ASIC by obtaining analog-to-digital (ADC) capability from other ASIC like digital ASIC for terminate and stay resident (TSR) and memory ADC function.

[00029] In this manner, the present specification discloses techniques to use memristors in static NMOS logic used in print heads such as IPHs including print heads with cartridge and print heads without cartridges. Even though the present specification discloses techniques to use memristors in IPH and printer system, it can be envisioned that the disclosed techniques may be used in any other electronic devices.

[00030] The foregoing describes a novel and previously unforeseen approach for storage management. While the above specification has been shown and described with reference to the foregoing examples, it should be understood that other forms, details, and implementations may be made without departing from the spirit and scope of this specification.